Games / Command flash cards / SDC (Synopsys Design Constraints) / Object access

Object access

The cards come in more than one shape: a command to explain, and a snippet with a fault to find. A missed card returns later in the round and starts the schedule over. A card answered correctly moves up the schedule and next appears after 1, 3, 7, then 21 days. Keys 1 to 4 choose an option, h shows a hint, and Enter moves on. A hint keeps the card where it is on the schedule. An ordering card is answered by clicking its items in order, and one wrong click ends it. Time values are in nanoseconds. Progress is stored in this browser.

SourceThese cards follow SDC (Synopsys Design Constraints) as implemented by OpenSTA, the open-source static timing analyzer used by OpenROAD, and each answer links to that command in the OpenSTA command reference. Commercial timers accept the same commands but can differ in details; where OpenSTA reads a command without acting on it, the card says so. Reference: OpenSTA command reference (OpenSTA on GitHub).
All 17 cards in this section, with answers
  • get_ports data*
    Returns the top-level ports whose names start with data.

    Hint: A port belongs to the design's boundary, not to an instance.

    A port is a pin of the top-level design itself, where the block meets the outside. Pins of instances inside the design are found with get_pins. OpenSTA reference

  • get_pins u_alu/*
    Returns every pin of the instance u_alu.

    Hint: A pin belongs to an instance. Ask what u_alu/* covers.

    A pin name is the instance name, the hierarchy separator, and the pin name, as in u_alu/A. When u_alu is a hierarchical block, its pins are the block's boundary pins. OpenSTA reference

  • get_clocks clk*
    Returns the defined clocks whose names start with clk, not ports or pins.

    Hint: A clock is a constraint object with its own name, separate from the port.

    A clock is a constraint object with its own name, which need not match the port it is defined on. Commands such as set_clock_uncertainty and set_false_path -from expect clock objects; passing a port applies the constraint at that point instead. OpenSTA reference

  • get_cells -hierarchical *_reg*
    Returns instances matching *_reg* at every level below this one.

    Hint: Ask what the pattern would match without the flag.

    Without -hierarchical, a pattern is matched only at the current level of hierarchy. With it, the search descends into every block below. OpenSTA reference

  • get_nets -of_objects [get_pins u1/Z]
    Returns the net connected to pin u1/Z.

    Hint: It walks connectivity rather than matching a name.

    -of_objects walks the connectivity instead of matching names: the net of a pin, the pins of a net, or the pins of a cell. OpenSTA reference

  • all_inputs
    Returns every input port of the design, including clock inputs.

    Hint: Ask whether the clock port counts as an input.

    The clock port is an input too, so set_input_delay applied to all_inputs also puts an input delay on the clock. Flows remove the clock port from the list first. OpenSTA reference

  • set_output_delay -clock clk 0.5 [all_outputs]
    Applies a 0.5 ns output delay relative to clk to every output port.

    Hint: Ask what set of ports the command returns, and what it leaves out.

    all_outputs returns the top-level output ports. Combined with a single output delay it is the usual first-pass boundary constraint, refined later for ports with different external timing. OpenSTA reference

  • all_registers -clock clk_a
    Returns the registers and latches clocked by clk_a.

    Hint: By default it returns instances. Ask whether latches are among them.

    By default the result is register instances, both flip-flops and latches. -clock_pins, -data_pins, -async_pins, and -output_pins return pins instead; -edge_triggered and -level_sensitive pick one kind. OpenSTA reference

  • all_clocks
    Returns every defined clock, including generated and virtual clocks.

    Hint: Ask whether a clock with no pin still counts.

    The result is clock objects: every clock from create_clock and create_generated_clock, whether it sits on a port, on an internal pin, or on nothing (a virtual clock). OpenSTA reference

  • current_design top
    Makes top the design that the following commands apply to.

    Hint: Several designs can be loaded. Ask what the command picks.

    With several designs loaded, constraints apply to the current one. Constraint files often begin with it so they are read in the right context. OpenSTA reference

  • get_lib_cells */BUF_*
    Returns the library cells named BUF_* in every loaded library.

    Hint: The pattern names a library. Ask whether the result is in the design.

    No instances are returned. Library objects are the cell definitions; design objects are the instances of them in the netlist. A library cell is named with its library, as in lib/BUF_X2. OpenSTA reference

  • get_lib_pins */BUF_X2/Z
    Returns the Z pin of the library cell BUF_X2, not a pin of any instance.

    Hint: The pattern names a library cell's pin. Ask which pin it is.

    A library pin belongs to the cell definition. It carries the pin's library data, such as its capacitance and design-rule limits. OpenSTA reference

  • get_libs *ss*
    Returns the loaded libraries whose names contain ss.

    Hint: Ask whether this searches files on disk or what is already loaded.

    It searches libraries already loaded, for example to pick the slow-corner library by name. Reading a library from disk is a tool command, not part of SDC (Synopsys Design Constraints). OpenSTA reference

  • get_pins -of_objects [get_nets n1] -filter "direction==output"
    Returns the driver of net n1, the pin on it whose direction is output.

    Hint: A net has one output pin among its pins. Ask what that pin is.

    -filter keeps only objects whose properties match the expression. Combined with -of_objects, this is the usual way to find the pin that drives a net. OpenSTA reference

  • get_ports -regexp {data\[[0-3]\]}
    Returns the ports data[0] through data[3], using a regular expression.

    Hint: Ask what the brackets mean once the pattern is a regular expression.

    Without -regexp, patterns are wildcard patterns in which * matches any text and ? one character. -regexp switches to regular expressions, and -nocase then makes matching case-insensitive. OpenSTA reference

  • get_cells -quiet u_spare*
    Returns the matching cells, or an empty list with no error if none match.

    Hint: Ask what normally happens when a pattern matches nothing.

    A pattern that matches nothing normally reports an error. -quiet suits constraints shared between designs where some objects may not exist. OpenSTA reference

  • set_false_path -from [get_pins dpath/a_reg[9]/Q]
    The bus index is taken as a command, so the line fails.

    Hint: Count the square brackets and ask what each pair means to the interpreter.

    Square brackets are command substitution, so the interpreter tries to run a command named 9. The name has to be braced or escaped, as in {dpath/a_reg[9]/Q}, or built with a variable that is passed straight through. This is the commonest mistake in a constraints file. OpenSTA reference