Games / Command flash cards / SDC (Synopsys Design Constraints) / Input and output

Input and output

The cards come in more than one shape: a command to explain, a description whose command you name, a snippet with a fault to find, and a command with a gap to fill. A missed card returns later in the round and starts the schedule over. A card answered correctly moves up the schedule and next appears after 1, 3, 7, then 21 days. Keys 1 to 4 choose an option, h shows a hint, and Enter moves on. A hint keeps the card where it is on the schedule. An ordering card is answered by clicking its items in order, and one wrong click ends it. Time values are in nanoseconds. Progress is stored in this browser.

SourceThese cards follow SDC (Synopsys Design Constraints) as implemented by OpenSTA, the open-source static timing analyzer used by OpenROAD, and each answer links to that command in the OpenSTA command reference. Commercial timers accept the same commands but can differ in details; where OpenSTA reads a command without acting on it, the card says so. Reference: OpenSTA command reference (OpenSTA on GitHub).
All 15 cards in this section, with answers
  • set_input_delay -clock clk 0.6 [get_ports data_in]
    Says data_in arrives 0.6 ns after the rising edge of clk.

    Hint: The delay describes what happens outside the block, before the port.

    The input delay models the part of the path outside the block: from the launching register off-chip, through external logic and the board, to the port. The timer gives the on-chip path what is left of the cycle. Without -max or -min, the value is used for both setup and hold. OpenSTA reference

  • set_output_delay -clock clk 0.8 [get_ports data_out]
    Requires data_out to be valid 0.8 ns before the next capturing edge of clk.

    Hint: The delay describes what happens after the port, outside the block.

    The output delay is the external path after the port plus the setup time of the register that captures it off-chip. The on-chip path from the launching register to the port must finish in the period minus 0.8 ns. OpenSTA reference

  • set_input_delay -clock clk -max 1.2 [get_ports din] set_input_delay -clock clk -min 0.3 [get_ports din]
    Gives din a latest arrival of 1.2 ns for setup and an earliest of 0.3 ns for hold.

    Hint: Two commands, two flags. Ask which check uses each.

    A setup check uses the latest possible arrival and a hold check uses the earliest, so real interfaces constrain both. -max and -min set separate values and do not replace each other. -rise and -fall are the options that split the value by data transition. OpenSTA reference

  • set_input_delay -clock clk_a 1.0 [get_ports din] set_input_delay -clock clk_b 2.0 -add_delay [get_ports din]
    Gives din two arrival times, one relative to clk_a and one to clk_b, both timed.

    Hint: Two clocks, and a flag on the second command. Ask what it prevents.

    Without -add_delay, a second input delay on the same port replaces the first. With it, both are kept, which models a port driven by devices on two different clocks. OpenSTA reference

  • set_input_delay -clock clk -clock_fall 0.5 [get_ports din]
    Says din arrives 0.5 ns after the falling edge of clk.

    Hint: Distinguish -clock_fall from -fall: one is about the clock, the other the data.

    -clock_fall chooses which edge of the clock the delay is measured from. -fall is different: it restricts the value to falling transitions of the data signal. A falling-edge reference models an external device that launches data on the falling edge, as in DDR (Double Data Rate) interfaces. OpenSTA reference

  • set_output_delay -clock clk -min -0.2 [get_ports dout]
    Requires data to reach dout no sooner than 0.2 ns after the clk edge.

    Hint: A negative value on a minimum delay. Ask which check uses min, and which way it moves.

    The value is used for the hold check. There, the minimum output delay is the external minimum path delay minus the external register's hold time. A negative value means that hold time is longer than the external path, so the on-chip path to the port must supply the difference: data launched at the edge must not reach dout sooner than 0.2 ns. OpenSTA reference

  • set_driving_cell -lib_cell BUF_X2 -pin Z [all_inputs]
    Models every input port as driven by a BUF_X2 output pin.

    Hint: SDC (Synopsys Design Constraints) cannot change the netlist. Ask what the cell is used for.

    SDC (Synopsys Design Constraints) does not change the netlist. The port's slew now depends on its load: the timer uses the library tables of BUF_X2 to compute the delay and transition at each port from the load that port actually drives. This is more realistic than a fixed set_input_transition. The clock port is usually excluded and constrained separately. OpenSTA reference

  • set_input_transition 0.08 [get_ports din]
    Sets a fixed 0.08 ns transition at din, whatever load it drives.

    Hint: Compare it with set_driving_cell: ask whether this value depends on the load.

    The slew is fixed and does not depend on the load. A load-dependent slew comes from set_driving_cell, and a transition limit comes from set_max_transition. OpenSTA reference

  • set_load 0.02 [get_ports data_out]
    Adds 0.02 pF (picofarads) of off-chip capacitance on data_out for its driver.

    Hint: The port is an output. Ask what is on the other side of it.

    The load models the board trace and the receiving pin outside the block. The on-chip cell that drives the port must charge it, which increases that cell's delay and output slew. Capacitance is in the library's unit, which varies: picofarads in many libraries, femtofarads in others such as Nangate45. report_units shows which. A limit on load is set_max_capacitance. OpenSTA reference

  • set_drive 0.5 [get_ports din]
    Models the external driver of din as a 0.5 kilohm resistance.

    Hint: The unit is resistance. Ask which end of the input it describes.

    The drive resistance and the port's load set the input slew and delay. It is the older, simpler alternative to set_driving_cell, which uses a real cell's delay and slew tables and is usually preferred. Resistance is in the library's unit, usually kilohms. OpenSTA reference

  • set_driving_cell -lib_cell NAND2_X1 -from_pin A1 [get_ports din]
    Models din as driven by a NAND2_X1 through its arc from A1.

    Hint: A NAND has more than one input. Ask which arc the option picks.

    The delay and slew come from the NAND2_X1 arc that starts at input A1 and ends at its output. A cell with several inputs has a different delay arc from each one. -from_pin picks the arc, and -input_transition_rise and -input_transition_fall set the slew assumed at that input. OpenSTA reference

  • set_load 0.015 [get_nets n_long]
    Sets the wire capacitance of n_long to 0.015 pF, replacing extracted values.

    Hint: The object is a net, not a port. Ask what part of the net's capacitance this sets.

    On a port the value is external load; on a net it is the net's wire capacitance, in picofarads here. It overrides parasitics read from a SPEF (Standard Parasitic Exchange Format) file for that net. OpenSTA reference

  • You are constraining a block. Outside it, the logic between this output port and the register that captures it takes 0.4 nanoseconds.
    set_output_delay 0.4 -clock clk [get_ports out]

    Hint: The delay being described happens after the port, not before it.

    The number is the external delay the block must leave room for, so it is subtracted from the period when the path to the port is checked. A maximum delay would instead replace the clock-based check entirely, and a load is a capacitance, not a time. OpenSTA reference

  • set_input_delay 0.5 [get_ports data_in]
    No clock is named, so the delay has no edge to be relative to.

    Hint: An arrival time is always measured from something.

    An input delay says how late the data arrives after an edge of some clock, so the clock has to be named. Without it the command is an error, and in a script that ignores errors the port is left unconstrained and quietly never checked. OpenSTA reference

  • set_input_delay 0.4 ____ clk [get_ports data_in]
    -clock

    Hint: The missing word names which clock the arrival is measured against.

    Every port constraint is relative to a clock edge, and this is the option that names it. Its companions are -clock_fall for an arrival relative to the falling edge, and -add_delay to keep an earlier constraint on the same port rather than replacing it. OpenSTA reference