Games / Command flash cards / SDC (Synopsys Design Constraints) / Timing exceptions

Timing exceptions

The cards come in more than one shape: a command to explain, a description whose command you name, and a snippet with a fault to find. A missed card returns later in the round and starts the schedule over. A card answered correctly moves up the schedule and next appears after 1, 3, 7, then 21 days. Keys 1 to 4 choose an option, h shows a hint, and Enter moves on. A hint keeps the card where it is on the schedule. An ordering card is answered by clicking its items in order, and one wrong click ends it. Time values are in nanoseconds. Progress is stored in this browser.

SourceThese cards follow SDC (Synopsys Design Constraints) as implemented by OpenSTA, the open-source static timing analyzer used by OpenROAD, and each answer links to that command in the OpenSTA command reference. Commercial timers accept the same commands but can differ in details; where OpenSTA reads a command without acting on it, the card says so. Reference: OpenSTA command reference (OpenSTA on GitHub).
All 19 cards in this section, with answers
  • set_false_path -from [get_clocks clk_a] -to [get_clocks clk_b]
    Stops timing paths launched by clk_a and captured by clk_b, in that direction only.

    Hint: -from and -to are given. Ask whether the reverse direction is covered too.

    A false path is directional. Paths from clk_b back to clk_a are still timed unless a second command covers them; set_clock_groups covers both directions at once. A path should be declared false only when its timing can never matter, for example a crossing handled by a synchronizer. OpenSTA reference

  • set_false_path -from [get_ports rst_n]
    Removes every timing path that starts at the reset port rst_n.

    Hint: Only -from is given. Ask which checks at the far end also disappear.

    With only -from, every path from the port is removed, including the recovery and removal checks at the registers it resets. That is safe only when the release of reset is synchronized inside the block. Holding a pin constant is set_case_analysis; an ideal network is set_ideal_network. OpenSTA reference

  • set_multicycle_path 2 -setup -from [get_cells a_reg] -to [get_cells b_reg]
    Gives the path from a_reg to b_reg two clock cycles for setup instead of one.

    Hint: The setup edge moves a cycle later. Ask what happens to the hold check by default.

    The setup capture edge moves one cycle later. The hold check moves with it by default, to one cycle after the launch edge, which demands a very long minimum delay. That is why a setup multicycle is almost always paired with a hold multicycle of one less. OpenSTA reference

  • set_multicycle_path 2 -setup -from [get_cells a_reg] -to [get_cells b_reg] set_multicycle_path 1 -hold -from [get_cells a_reg] -to [get_cells b_reg]
    Allows two cycles for setup and moves the hold check back to the launch edge.

    Hint: Two commands, N and N-1. Ask where the hold check ends up.

    The hold multiplier counts how many cycles the hold check moves back from its default position. After -setup N, the rule is -hold N-1, which returns the hold check to the launch edge, the same as a normal single-cycle path. OpenSTA reference

  • set_multicycle_path 2 -setup -start -from [get_clocks clk_fast] -to [get_clocks clk_slow]
    Counts the two setup cycles in periods of the launching clock, clk_fast.

    Hint: Launch and capture clocks differ. Ask which one's period the multiplier counts.

    When the launch and capture clocks differ, the multiplier needs a reference clock. -start uses the launching clock and -end the capturing clock. By default setup multipliers count capture periods (-end) and hold multipliers count launch periods (-start). OpenSTA reference

  • set_max_delay 2.0 -from [get_ports in_a] -to [get_ports out_b]
    Requires the path from in_a to out_b to take at most 2.0 ns.

    Hint: A combinational path between two ports has no clock to constrain it.

    A typical use is a combinational feedthrough from an input port to an output port, which has no register to define a clock-based requirement. On a path that already has a clock requirement, the value replaces it. set_min_delay is the matching lower bound. OpenSTA reference

  • set_min_delay 0.3 -from [get_ports in_a] -to [get_ports out_b]
    Requires the path from in_a to out_b to take at least 0.3 ns.

    Hint: The mirror of a maximum delay. Ask which direction it bounds.

    The minimum delay is checked like a hold requirement. The command states the requirement; an optimization tool may then add delay to meet it, but the constraint itself inserts nothing. OpenSTA reference

  • group_path -name io_in -from [all_inputs]
    Puts every path from an input port into a group reported apart from others.

    Hint: Ask what a report shows per group, and what that hides when everything is in one.

    Each path group has its own worst path. A failing input path in its own group cannot hide the register-to-register paths in theirs, and optimization tools work on the worst path of every group. Commercial tools also accept -weight to set a group's optimization priority. OpenSTA reference

  • set_disable_timing -from A -to Z [get_cells u_mux]
    Deletes the timing arc from pin A to pin Z of u_mux, so no path uses it.

    Hint: Compare it with a false path: ask what happens to the arc itself.

    The arc is removed from the timing graph, so no path of any kind passes through it. Other arcs of the cell stay. Typical uses are breaking a combinational loop and removing an arc that the design never exercises. OpenSTA reference

  • set_case_analysis 0 [get_ports test_mode]
    Holds test_mode at 0 and propagates the constant through the logic.

    Hint: The pin is a mode select. Ask what happens to logic downstream of it.

    The constant propagates through downstream logic, so paths used only in test mode drop out. A multiplexer whose select is 0 passes only its 0 input, so paths through its 1 input disappear. This is how one netlist is timed separately in functional and test modes. A false path from the port would remove only paths starting there; the downstream logic would stay unconstrained by the mode. OpenSTA reference

  • set_max_time_borrow 0.3 [get_cells lat_*]
    Limits the latches lat_* to borrowing at most 0.3 ns after they open.

    Hint: Borrowing is a latch's ability to accept late data. Ask what the number caps.

    Time borrowing is data arriving at a transparent latch after it opens; the late arrival is passed on to the next stage. Capping it keeps the next stage's budget predictable. OpenSTA reference

  • set_data_check -from [get_pins u1/STROBE] -to [get_pins u1/D] -setup 0.1
    Requires u1/D to arrive at least 0.1 ns before u1/STROBE does.

    Hint: Neither pin is a clock. Ask what the -from pin acts as.

    This is a setup check between two data pins. A normal setup check compares data with a clock; a data check compares two data signals: the -from pin is the reference and the -to pin is checked against it. It suits a strobe and the data it samples, or the inputs of a custom macro. OpenSTA reference

  • set_min_pulse_width -high 0.4 [get_clocks clk]
    Requires each high pulse of clk to last at least 0.4 ns.

    Hint: The clock tree can shrink a pulse on its way to the registers.

    The check applies at the register clock pins. Unequal rise and fall delays in the clock tree can shrink a pulse on its way there. The check catches a pulse too narrow for a register to respond to. Without -high or -low, it applies to both. OpenSTA reference

  • set_max_delay 1.0 -from [get_ports din] -to [get_cells cap_reg]
    Requires data from din to meet cap_reg's check within 1.0 ns, setup time included.

    Hint: The path ends at a register, not a port. Ask what else is in the path then.

    When the path ends at a timing check, the check's setup time counts as part of the path, so the data must arrive earlier than 1.0 ns by that amount. The same holds for set_min_delay with the hold time. OpenSTA reference

  • group_path -default -from [all_inputs]
    Returns the paths from input ports to their default path group.

    Hint: The flag is -default. Ask what it undoes.

    group_path -default undoes an earlier grouping for the matching paths. By default a path belongs to the group of the clock that captures it. OpenSTA reference

  • set_disable_timing [get_cells u_ro]
    Disables every timing arc through u_ro but keeps its checks.

    Hint: A whole instance, no -from or -to. Ask whether its internal checks go too.

    With an instance and no -from or -to, all arcs through it are disabled; the timing checks inside it, such as a register's setup and hold, stay. A typical use is breaking the loop of a ring oscillator. OpenSTA reference

  • set_case_analysis rising [get_pins u_sel/S]
    Times only rising transitions at u_sel/S and drops its falling ones.

    Hint: The value is a transition, not a constant. Ask what still switches.

    Besides constants 0 and 1, case analysis accepts rising and falling. A transition value keeps the pin switching but limits it to one direction, for a signal that is only ever asserted one way during operation. OpenSTA reference

  • A path between two registers on the same clock is allowed two clock cycles to settle, rather than one.
    set_multicycle_path 2 -setup -from [get_pins a_reg/CK] -to [get_pins b_reg/D]

    Hint: One of these relaxes the check; the others remove it or replace it.

    The path is still checked, against a capture edge two cycles later. A false path would stop it being checked at all, and a maximum delay of 2 would set an absolute limit in nanoseconds unrelated to the clock. The hold form moves the hold check instead, which is the companion command, not this one. OpenSTA reference

  • set_multicycle_path 2 -setup -from [get_pins a_reg/CK] -to [get_pins b_reg/D]
    Without a matching hold exception, hold is now checked a cycle late.

    Hint: Ask which check moved when the setup edge moved.

    Moving the capture edge for setup moves the hold check with it, so hold is checked against the edge before the new capture edge, one full cycle after launch. Almost nothing meets that. The usual pair is a setup value of N with a hold value of N minus one. OpenSTA reference