Games / Command flash cards / SDC (Synopsys Design Constraints) / Environment and derating

Environment and derating

The cards come in more than one shape: a command to explain, and a command with a gap to fill. A missed card returns later in the round and starts the schedule over. A card answered correctly moves up the schedule and next appears after 1, 3, 7, then 21 days. Keys 1 to 4 choose an option, h shows a hint, and Enter moves on. A hint keeps the card where it is on the schedule. An ordering card is answered by clicking its items in order, and one wrong click ends it. Time values are in nanoseconds. Progress is stored in this browser.

SourceThese cards follow SDC (Synopsys Design Constraints) as implemented by OpenSTA, the open-source static timing analyzer used by OpenROAD, and each answer links to that command in the OpenSTA command reference. Commercial timers accept the same commands but can differ in details; where OpenSTA reads a command without acting on it, the card says so. Reference: OpenSTA command reference (OpenSTA on GitHub).
All 5 cards in this section, with answers
  • set_timing_derate -late 1.05
    Scales late delays up by 5%, to model slow on-chip variation.

    Hint: Late values are the ones that hurt when larger. Ask which paths those are.

    Late values are the ones that hurt when larger: the data path of a setup check and the capture clock path of a hold check. Without -clock or -data, both clock and data paths are derated; without -cell_delay or -net_delay, both kinds of delay are. OpenSTA reference

  • set_timing_derate -early 0.95 -cell_delay
    Scales early cell delays down by 5%, leaving net delays unchanged.

    Hint: Two restrictions: early paths, and one kind of delay.

    An early derate below 1 and a late derate above 1 make the analysis pessimistic in both directions at once. On a clock path shared by launch and capture, the two derates cannot both be true; CRPR (Clock Reconvergence Pessimism Removal) removes that part. OpenSTA reference

  • set_operating_conditions ss_0p72v_125c
    Selects the operating condition ss_0p72v_125c from a loaded library.

    Hint: The name looks like a corner. Ask where such a condition is defined.

    An operating condition (process, voltage, temperature) is defined inside a loaded library; the command picks one by name for delay calculation. Current flows usually load one library per corner instead, and analyze several corners. OpenSTA reference

  • set_operating_conditions -analysis_type on_chip_variation -min ff_cond -max ss_cond
    Times setup with slow data and a fast clock, and hold the reverse.

    Hint: On-chip variation assumes both conditions at once. Ask which side gets which.

    On-chip variation assumes both conditions can occur on the same die at once. A setup check takes the max condition for data and the min for the clock; a hold check takes the reverse. The bc_wc type instead applies one condition to both clock and data. OpenSTA reference

  • set_timing_derate ____ 1.05
    -late

    Hint: The paths being slowed are the late ones, whichever check they serve.

    Derating is expressed as early and late, not as minimum and maximum, because the same path can be the late one in a setup check and the early one in a hold check. A factor above one slows the late paths; the early ones take a factor below one. OpenSTA reference