Design rules
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All 7 cards in this section, with answers
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set_max_transition 0.15 [current_design]Sets a 0.15 ns slew limit on every pin of the design, as a rule to fix.
Hint: Ask whether this describes the design or constrains it.
A slow transition increases delay, short-circuit power, and sensitivity to noise. Violations are fixed by buffering or upsizing, usually before timing optimization. Library pins carry their own limits as well. OpenSTA reference
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set_max_transition 0.5 [current_design] ;# library pin limits are 0.3Leaves the library's 0.3 ns limit in force on those pins.
Hint: Two limits now exist on those pins. Ask which one wins.
The stricter limit applies. A design rule can come from the library (per pin) and from the constraints (per design, port, or clock). Where both exist, the tighter one is checked, so an SDC (Synopsys Design Constraints) limit can tighten the library value but never relax it. OpenSTA reference
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set_max_transition -clock_path 0.08 [get_clocks clk]Sets a 0.08 ns slew limit on the clock network of clk only.
Hint: The object is a clock and the flag narrows it further. Ask to what.
On a clock object the limit applies to every pin in that clock's domain;
-clock_pathnarrows it to the clock network. Clock slews affect skew, pulse width, and power, so they are usually held tighter than data slews. OpenSTA reference -
set_max_capacitance 0.1 [current_design]Sets 0.1 pF (picofarads) as the most load any driver may drive.
Hint: The load a driver sees is wire plus pins. Ask what the limit protects.
The load is the net's wire capacitance plus the input pins it drives. A cell's delay tables cover a limited range of loads; beyond it the delay is extrapolated and unreliable. Violations are fixed by buffering or upsizing the driver. OpenSTA reference
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set_max_fanout 16 [current_design]Limits every driver in the design to a fanout of 16.
Hint: Fanout counts loads, not length. Ask how a violation is fixed.
Violations are fixed by splitting the net with buffers. Fanout adds up the fanout load of the pins a driver drives, usually 1 each. It is a coarse stand-in for capacitance and slew, so many flows rely on the transition and capacitance limits instead. OpenSTA reference
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set_min_capacitance 0.002 [get_ports dout]Requires the driver of dout to see at least 0.002 pF (picofarads) of load.
Hint: A minimum, not a maximum. Ask when too little load is a problem.
A minimum load is uncommon. It applies when a cell is characterized, or stable, only above some load. The fix is to add load, for example a larger wire or an extra pin. OpenSTA reference
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No pin in the design may be driven with a transition slower than 0.15 nanoseconds, whatever the library allows.set_max_transition 0.15 [current_design]
Hint: The limit is on how sharp an edge is, not on what it drives.
This is a design rule, checked at every pin and repaired by sizing and buffering. The capacitance form limits load instead, the clock form sets an assumed transition on an ideal clock, and the input form describes what drives the ports. OpenSTA reference