Games / Command flash cards / SDC (Synopsys Design Constraints) / Clocks

Clocks

The cards come in more than one shape: a command to explain, a description whose command you name, a snippet with a fault to find, and a command with a gap to fill. A missed card returns later in the round and starts the schedule over. A card answered correctly moves up the schedule and next appears after 1, 3, 7, then 21 days. Keys 1 to 4 choose an option, h shows a hint, and Enter moves on. A hint keeps the card where it is on the schedule. An ordering card is answered by clicking its items in order, and one wrong click ends it. Time values are in nanoseconds. Progress is stored in this browser.

SourceThese cards follow SDC (Synopsys Design Constraints) as implemented by OpenSTA, the open-source static timing analyzer used by OpenROAD, and each answer links to that command in the OpenSTA command reference. Commercial timers accept the same commands but can differ in details; where OpenSTA reads a command without acting on it, the card says so. Reference: OpenSTA command reference (OpenSTA on GitHub).

All 27 cards in this section, with answers

create_clock -name clk -period 2.0 [get_ports clk]

Defines a 2.0 ns clock on port clk, rising at 0 and falling at 1.0.

Hint: Ask what -period covers, and where the falling edge goes when no waveform is given.

-period is the full cycle time, and -name gives the clock a name separate from the port. With no -waveform, the clock rises at 0 and falls at half the period, a 50% duty cycle. OpenSTA reference
create_clock -name vclk -period 2.0

Defines a clock on no pin or port, used as a reference for I/O (Input/Output) delays.

Hint: Nothing follows the period. Ask what the clock is attached to.

With no object list the clock is virtual. It models the clock of an off-chip device, so set_input_delay -clock vclk and set_output_delay -clock vclk can time the chip's I/O (Input/Output) paths against it. OpenSTA reference
create_clock -name clk -period 10 -waveform {0 3} [get_ports clk]

Defines a 10 ns clock that rises at 0 and falls at 3, a 30% duty cycle.

Hint: Two numbers in the waveform. Ask which edge each one is.

The waveform list gives the rise time first and the fall time second, both within one period. {0 3} means high from 0 to 3 and low from 3 to 10. OpenSTA reference
create_clock -name clk_test -period 20 -add [get_ports clk]

Defines a second clock on port clk, keeping the clock already there.

Hint: A clock already exists on that port. Ask what the flag protects.

Defining a clock on a pin that already has one replaces it. -add keeps both, which models one port that carries different clocks in different modes (functional and test). Such clocks are usually then separated with set_clock_groups. OpenSTA reference
create_generated_clock -name clk_div2 -source [get_ports clk] -divide_by 2 [get_pins div_reg/Q]

Declares a clock at div_reg/Q, derived from clk, with twice its period.

Hint: Dividing the frequency does the opposite to the period.

SDC (Synopsys Design Constraints) describes the circuit; it does not build it. The divider flip-flop already exists, and this command tells the timer what clock appears at its output. Because the clock is derived from clk, its edges stay aligned with clk and paths between the two clocks are timed. OpenSTA reference
create_generated_clock -name clk_pll -source [get_pins pll/REF] -multiply_by 4 [get_pins pll/OUT]

Declares a clock at the PLL (Phase-Locked Loop) output with one quarter of the reference clock's period.

Hint: Multiplying the frequency does the opposite to the period.

-multiply_by multiplies the frequency, so the period is divided. A PLL (Phase-Locked Loop) output cannot be traced through the netlist, so a generated clock declares it. OpenSTA reference
set_clock_uncertainty -setup 0.15 [get_clocks clk]

Makes setup checks on clk 0.15 ns stricter, as margin for jitter and skew.

Hint: Ask which direction uncertainty pushes a setup check, and what the flag narrows it to.

For a setup check the uncertainty moves the required time earlier, which reduces setup slack by that amount. The -setup flag limits it to setup checks. Before CTS (Clock Tree Synthesis) the value usually includes a skew estimate. After CTS (Clock Tree Synthesis) the real skew is computed, and the value is reduced to jitter plus margin. OpenSTA reference
set_clock_uncertainty 0.1 [get_clocks clk]

Applies 0.1 ns of uncertainty to both setup and hold checks on clk.

Hint: No -setup and no -hold. Ask which checks are left.

Without -setup or -hold the value applies to both checks. Setup and hold usually need different margins, so production constraints often set them separately. OpenSTA reference
set_clock_latency -source 0.4 [get_clocks clk]

Models 0.4 ns of delay from the clock's origin to its definition point.

Hint: Source latency is measured on one side of the clock definition point. Ask which.

Source latency is the delay before the clock definition point, for example from an off-chip oscillator to the clock port. Network latency (the same command without -source) is the delay from the definition point to the register clock pins. Source latency still applies after the clocks are propagated; ideal network latency is replaced by the computed tree delay. OpenSTA reference
set_clock_latency 0.8 [get_clocks clk]

Estimates 0.8 ns of on-chip clock tree delay while clk is still ideal.

Hint: Without -source, the latency is on the other side of the definition point.

Before CTS (Clock Tree Synthesis) no tree exists, so its delay is estimated. The latency is added to both launch and capture edges, so it cancels on paths within clk but shifts I/O (Input/Output) paths and paths to other clocks. After set_propagated_clock the computed tree delay is used instead. OpenSTA reference
set_propagated_clock [all_clocks]

Makes timing use the calculated delay through the built clock tree.

Hint: Ask what a clock's delay is before this command, and after it.

The command switches clocks from ideal to propagated. An ideal clock reaches every register at the same time, plus any estimated latency. A propagated clock carries the real buffer and wire delays, so real skew appears in the timing report. It is applied after CTS (Clock Tree Synthesis). OpenSTA reference
set_clock_transition 0.05 [get_clocks clk]

Sets the slew assumed at register clock pins while clk is ideal.

Hint: An ideal clock has no buffers. Ask where a slew would otherwise come from.

An ideal clock has no buffers from which to compute a slew, so this value stands in for one. It affects register clock-to-output delay and setup and hold times. After propagation the computed slews replace it. The design-rule limit is a different command, set_max_transition. OpenSTA reference
set_clock_groups -asynchronous -group [get_clocks clk_a] -group [get_clocks clk_b]

Declares clk_a and clk_b asynchronous, so paths between them are not timed.

Hint: Two groups, no phase relation. Ask what the timer should do with paths between them.

The effect is a false path in both directions between the groups. Signals that cross between asynchronous clocks cannot be closed by timing analysis; they need CDC (Clock Domain Crossing) synchronizers, which are verified separately. OpenSTA reference
create_generated_clock -name clk_e -source [get_ports clk] -edges {1 3 5} [get_pins div/Q]

Declares a clock at div/Q with twice the period of clk.

Hint: Edges are numbered from 1: rise, fall, rise. Count 1 to 5.

The waveform is built from clk edges 1, 3, and 5. The source clock's edges are numbered from 1: rise, fall, rise, and so on. The generated clock rises at edge 1, falls at edge 3, and rises again at edge 5, so its period covers two source periods. -edges describes waveforms that -divide_by cannot, such as a non-50% duty cycle. OpenSTA reference
create_generated_clock -name clk_n -source [get_ports clk] -divide_by 1 -invert [get_pins u_gen/CLKN]

Declares the clock at u_gen/CLKN as clk inverted, with the same period.

Hint: Divide by one changes nothing; ask what -invert adds.

The timer already propagates a clock through a plain inverter. A generated clock with -invert is for an inversion the timer cannot trace, such as the output of a clock-generator cell. OpenSTA reference
create_generated_clock -name gclk -source [get_pins mux/Z] -master_clock clk_b -divide_by 2 [get_pins div/Q]

Derives gclk from clk_b, one of several clocks that reach mux/Z.

Hint: Several clocks reach the source pin. Ask what the option resolves.

When more than one clock reaches the source pin, -master_clock says which one the generated clock is derived from. A second generated clock with -add covers the other master. OpenSTA reference
set_clock_groups -physically_exclusive -group [get_clocks clk_func] -group [get_clocks clk_test]

Declares that clk_func and clk_test never exist on the chip at the same time.

Hint: Physically exclusive: ask whether both clocks are ever present at once.

Physically exclusive clocks are defined on the same point for different modes, so only one is ever present. Paths between them are not timed, and crosstalk between them is not considered either, since they never switch together. OpenSTA reference
set_clock_groups -logically_exclusive -group [get_clocks clk_a] -group [get_clocks clk_b]

Declares that clk_a and clk_b both exist on the chip but never exchange data.

Hint: Logically exclusive: both exist on the chip. Ask what they never do.

The typical case is a multiplexer that selects one of two clocks: both clocks run on the chip, but beyond the multiplexer only one reaches the registers. Paths between them are not timed; crosstalk between the two clock networks is still considered, because both switch. OpenSTA reference
set_clock_gating_check -setup 0.1 -hold 0.05

Adds 0.1 ns setup and 0.05 ns hold checks on the enable of every clock gate.

Hint: No objects are named. Ask how widely the margins apply.

An enable that changes while the clock is active would cut the clock pulse short. For an AND gate the enable must be stable while the clock is high; the check enforces that with margins. With no objects the margins apply to every clock-gating circuit in the design. OpenSTA reference
set_sense -type clock -stop_propagation [get_pins u_mux/I1]

Stops clocks from propagating beyond the pin u_mux/I1.

Hint: Only clock propagation is affected. Ask where it stops.

Only clock propagation stops; data timing through the pin is unchanged. It prunes a clock from logic it never really drives, such as the unused input of a clock multiplexer. set_sense replaces the deprecated set_clock_sense. OpenSTA reference
set_sense -type clock -negative [get_pins u_xor/Z]

Tells the timer the clock at u_xor/Z is inverted from its input.

Hint: An XOR (exclusive-OR) gate can pass or invert. Ask what the timer cannot work out alone.

An XOR (exclusive-OR) gate is not unate: its output can follow or invert an input depending on the other input. The timer cannot tell which, so it considers both. Setting the sense resolves it to one. OpenSTA reference
set_ideal_network [get_ports scan_en]

Treats the scan_en network as ideal, with no delay or buffering.

Hint: scan_en is a high-fanout net buffered later. Ask how it is treated until then.

High-fanout nets such as scan enable and reset are buffered in a dedicated step later. Until then, treating them as ideal keeps their huge fanout from distorting timing and from wasting optimization effort. OpenSTA reads this command and ignores it. OpenSTA reference
set_ideal_latency 0.3 [get_ports scan_en]

Gives the ideal network from scan_en an arrival latency of 0.3 ns.

Hint: An ideal network has zero delay. Ask what this estimates.

An ideal network has zero delay, which is optimistic. The latency estimates the delay its future buffer tree will add, as network latency does for an ideal clock. OpenSTA reads this command and ignores it. OpenSTA reference
set_ideal_transition 0.1 [get_ports scan_en]

Sets 0.1 ns as the transition on the ideal network from scan_en.

Hint: An ideal network has no buffers, so it has no slew of its own.

An ideal network has no real buffers to compute a slew from, so this value stands in for one, as set_clock_transition does for an ideal clock. OpenSTA reads this command and ignores it. OpenSTA reference
Two clocks in the design never appear in the same logic. You want every path between them left unchecked, in both directions, with one command that also covers paths added later.

set_clock_groups -asynchronous -group {clk_a} -group {clk_b}

Hint: A one-way exception would leave the other direction still checked.

Grouping cuts every path between the groups, both ways, and keeps doing so for paths created later. A false path as written covers one direction only, so the reverse paths are still timed. Uncertainty adds margin rather than removing the check. OpenSTA reference
create_clock -name clk -period 2.0

No port is given, so this defines a virtual clock instead.

Hint: Ask what this clock is attached to.

A clock with no object list is a virtual clock, which exists for constraining ports but drives nothing in the design. Every register meant to be on it is then unclocked, and the timer reports the endpoints as unconstrained rather than failing. OpenSTA reference
create_clock -period 2.0 -name clk -waveform {0 ____} [get_ports clk]

1.0

Hint: The clock is meant to spend half its period high.

The two numbers are the times of the first rising and the first falling edge, so a symmetric clock of period 2 falls at 1. This is also the default, which is why the option is usually left out and only appears when the duty cycle is not even. OpenSTA reference