Games / Command flash cards / SDC (Synopsys Design Constraints) / All sections

All sections

The cards come in more than one shape: a command to explain, a description whose command you name, a snippet with a fault to find, a command with a gap to fill, and steps to put in order. A missed card returns later in the round and starts the schedule over. A card answered correctly moves up the schedule and next appears after 1, 3, 7, then 21 days. Keys 1 to 4 choose an option, h shows a hint, and Enter moves on. A hint keeps the card where it is on the schedule. An ordering card is answered by clicking its items in order, and one wrong click ends it. Time values are in nanoseconds. Progress is stored in this browser.

SourceThese cards follow SDC (Synopsys Design Constraints) as implemented by OpenSTA, the open-source static timing analyzer used by OpenROAD, and each answer links to that command in the OpenSTA command reference. Commercial timers accept the same commands but can differ in details; where OpenSTA reads a command without acting on it, the card says so. Reference: OpenSTA command reference (OpenSTA on GitHub).
All 96 cards in this deck, with answers
  • create_clock -name clk -period 2.0 [get_ports clk]
    Defines a 2.0 ns clock on port clk, rising at 0 and falling at 1.0.

    Hint: Ask what -period covers, and where the falling edge goes when no waveform is given.

    -period is the full cycle time, and -name gives the clock a name separate from the port. With no -waveform, the clock rises at 0 and falls at half the period, a 50% duty cycle. OpenSTA reference

  • create_clock -name vclk -period 2.0
    Defines a clock on no pin or port, used as a reference for I/O (Input/Output) delays.

    Hint: Nothing follows the period. Ask what the clock is attached to.

    With no object list the clock is virtual. It models the clock of an off-chip device, so set_input_delay -clock vclk and set_output_delay -clock vclk can time the chip's I/O (Input/Output) paths against it. OpenSTA reference

  • create_clock -name clk -period 10 -waveform {0 3} [get_ports clk]
    Defines a 10 ns clock that rises at 0 and falls at 3, a 30% duty cycle.

    Hint: Two numbers in the waveform. Ask which edge each one is.

    The waveform list gives the rise time first and the fall time second, both within one period. {0 3} means high from 0 to 3 and low from 3 to 10. OpenSTA reference

  • create_clock -name clk_test -period 20 -add [get_ports clk]
    Defines a second clock on port clk, keeping the clock already there.

    Hint: A clock already exists on that port. Ask what the flag protects.

    Defining a clock on a pin that already has one replaces it. -add keeps both, which models one port that carries different clocks in different modes (functional and test). Such clocks are usually then separated with set_clock_groups. OpenSTA reference

  • create_generated_clock -name clk_div2 -source [get_ports clk] -divide_by 2 [get_pins div_reg/Q]
    Declares a clock at div_reg/Q, derived from clk, with twice its period.

    Hint: Dividing the frequency does the opposite to the period.

    SDC (Synopsys Design Constraints) describes the circuit; it does not build it. The divider flip-flop already exists, and this command tells the timer what clock appears at its output. Because the clock is derived from clk, its edges stay aligned with clk and paths between the two clocks are timed. OpenSTA reference

  • create_generated_clock -name clk_pll -source [get_pins pll/REF] -multiply_by 4 [get_pins pll/OUT]
    Declares a clock at the PLL (Phase-Locked Loop) output with one quarter of the reference clock's period.

    Hint: Multiplying the frequency does the opposite to the period.

    -multiply_by multiplies the frequency, so the period is divided. A PLL (Phase-Locked Loop) output cannot be traced through the netlist, so a generated clock declares it. OpenSTA reference

  • set_clock_uncertainty -setup 0.15 [get_clocks clk]
    Makes setup checks on clk 0.15 ns stricter, as margin for jitter and skew.

    Hint: Ask which direction uncertainty pushes a setup check, and what the flag narrows it to.

    For a setup check the uncertainty moves the required time earlier, which reduces setup slack by that amount. The -setup flag limits it to setup checks. Before CTS (Clock Tree Synthesis) the value usually includes a skew estimate. After CTS (Clock Tree Synthesis) the real skew is computed, and the value is reduced to jitter plus margin. OpenSTA reference

  • set_clock_uncertainty 0.1 [get_clocks clk]
    Applies 0.1 ns of uncertainty to both setup and hold checks on clk.

    Hint: No -setup and no -hold. Ask which checks are left.

    Without -setup or -hold the value applies to both checks. Setup and hold usually need different margins, so production constraints often set them separately. OpenSTA reference

  • set_clock_latency -source 0.4 [get_clocks clk]
    Models 0.4 ns of delay from the clock's origin to its definition point.

    Hint: Source latency is measured on one side of the clock definition point. Ask which.

    Source latency is the delay before the clock definition point, for example from an off-chip oscillator to the clock port. Network latency (the same command without -source) is the delay from the definition point to the register clock pins. Source latency still applies after the clocks are propagated; ideal network latency is replaced by the computed tree delay. OpenSTA reference

  • set_clock_latency 0.8 [get_clocks clk]
    Estimates 0.8 ns of on-chip clock tree delay while clk is still ideal.

    Hint: Without -source, the latency is on the other side of the definition point.

    Before CTS (Clock Tree Synthesis) no tree exists, so its delay is estimated. The latency is added to both launch and capture edges, so it cancels on paths within clk but shifts I/O (Input/Output) paths and paths to other clocks. After set_propagated_clock the computed tree delay is used instead. OpenSTA reference

  • set_propagated_clock [all_clocks]
    Makes timing use the calculated delay through the built clock tree.

    Hint: Ask what a clock's delay is before this command, and after it.

    The command switches clocks from ideal to propagated. An ideal clock reaches every register at the same time, plus any estimated latency. A propagated clock carries the real buffer and wire delays, so real skew appears in the timing report. It is applied after CTS (Clock Tree Synthesis). OpenSTA reference

  • set_clock_transition 0.05 [get_clocks clk]
    Sets the slew assumed at register clock pins while clk is ideal.

    Hint: An ideal clock has no buffers. Ask where a slew would otherwise come from.

    An ideal clock has no buffers from which to compute a slew, so this value stands in for one. It affects register clock-to-output delay and setup and hold times. After propagation the computed slews replace it. The design-rule limit is a different command, set_max_transition. OpenSTA reference

  • set_clock_groups -asynchronous -group [get_clocks clk_a] -group [get_clocks clk_b]
    Declares clk_a and clk_b asynchronous, so paths between them are not timed.

    Hint: Two groups, no phase relation. Ask what the timer should do with paths between them.

    The effect is a false path in both directions between the groups. Signals that cross between asynchronous clocks cannot be closed by timing analysis; they need CDC (Clock Domain Crossing) synchronizers, which are verified separately. OpenSTA reference

  • create_generated_clock -name clk_e -source [get_ports clk] -edges {1 3 5} [get_pins div/Q]
    Declares a clock at div/Q with twice the period of clk.

    Hint: Edges are numbered from 1: rise, fall, rise. Count 1 to 5.

    The waveform is built from clk edges 1, 3, and 5. The source clock's edges are numbered from 1: rise, fall, rise, and so on. The generated clock rises at edge 1, falls at edge 3, and rises again at edge 5, so its period covers two source periods. -edges describes waveforms that -divide_by cannot, such as a non-50% duty cycle. OpenSTA reference

  • create_generated_clock -name clk_n -source [get_ports clk] -divide_by 1 -invert [get_pins u_gen/CLKN]
    Declares the clock at u_gen/CLKN as clk inverted, with the same period.

    Hint: Divide by one changes nothing; ask what -invert adds.

    The timer already propagates a clock through a plain inverter. A generated clock with -invert is for an inversion the timer cannot trace, such as the output of a clock-generator cell. OpenSTA reference

  • create_generated_clock -name gclk -source [get_pins mux/Z] -master_clock clk_b -divide_by 2 [get_pins div/Q]
    Derives gclk from clk_b, one of several clocks that reach mux/Z.

    Hint: Several clocks reach the source pin. Ask what the option resolves.

    When more than one clock reaches the source pin, -master_clock says which one the generated clock is derived from. A second generated clock with -add covers the other master. OpenSTA reference

  • set_clock_groups -physically_exclusive -group [get_clocks clk_func] -group [get_clocks clk_test]
    Declares that clk_func and clk_test never exist on the chip at the same time.

    Hint: Physically exclusive: ask whether both clocks are ever present at once.

    Physically exclusive clocks are defined on the same point for different modes, so only one is ever present. Paths between them are not timed, and crosstalk between them is not considered either, since they never switch together. OpenSTA reference

  • set_clock_groups -logically_exclusive -group [get_clocks clk_a] -group [get_clocks clk_b]
    Declares that clk_a and clk_b both exist on the chip but never exchange data.

    Hint: Logically exclusive: both exist on the chip. Ask what they never do.

    The typical case is a multiplexer that selects one of two clocks: both clocks run on the chip, but beyond the multiplexer only one reaches the registers. Paths between them are not timed; crosstalk between the two clock networks is still considered, because both switch. OpenSTA reference

  • set_clock_gating_check -setup 0.1 -hold 0.05
    Adds 0.1 ns setup and 0.05 ns hold checks on the enable of every clock gate.

    Hint: No objects are named. Ask how widely the margins apply.

    An enable that changes while the clock is active would cut the clock pulse short. For an AND gate the enable must be stable while the clock is high; the check enforces that with margins. With no objects the margins apply to every clock-gating circuit in the design. OpenSTA reference

  • set_sense -type clock -stop_propagation [get_pins u_mux/I1]
    Stops clocks from propagating beyond the pin u_mux/I1.

    Hint: Only clock propagation is affected. Ask where it stops.

    Only clock propagation stops; data timing through the pin is unchanged. It prunes a clock from logic it never really drives, such as the unused input of a clock multiplexer. set_sense replaces the deprecated set_clock_sense. OpenSTA reference

  • set_sense -type clock -negative [get_pins u_xor/Z]
    Tells the timer the clock at u_xor/Z is inverted from its input.

    Hint: An XOR (exclusive-OR) gate can pass or invert. Ask what the timer cannot work out alone.

    An XOR (exclusive-OR) gate is not unate: its output can follow or invert an input depending on the other input. The timer cannot tell which, so it considers both. Setting the sense resolves it to one. OpenSTA reference

  • set_ideal_network [get_ports scan_en]
    Treats the scan_en network as ideal, with no delay or buffering.

    Hint: scan_en is a high-fanout net buffered later. Ask how it is treated until then.

    High-fanout nets such as scan enable and reset are buffered in a dedicated step later. Until then, treating them as ideal keeps their huge fanout from distorting timing and from wasting optimization effort. OpenSTA reads this command and ignores it. OpenSTA reference

  • set_ideal_latency 0.3 [get_ports scan_en]
    Gives the ideal network from scan_en an arrival latency of 0.3 ns.

    Hint: An ideal network has zero delay. Ask what this estimates.

    An ideal network has zero delay, which is optimistic. The latency estimates the delay its future buffer tree will add, as network latency does for an ideal clock. OpenSTA reads this command and ignores it. OpenSTA reference

  • set_ideal_transition 0.1 [get_ports scan_en]
    Sets 0.1 ns as the transition on the ideal network from scan_en.

    Hint: An ideal network has no buffers, so it has no slew of its own.

    An ideal network has no real buffers to compute a slew from, so this value stands in for one, as set_clock_transition does for an ideal clock. OpenSTA reads this command and ignores it. OpenSTA reference

  • set_input_delay -clock clk 0.6 [get_ports data_in]
    Says data_in arrives 0.6 ns after the rising edge of clk.

    Hint: The delay describes what happens outside the block, before the port.

    The input delay models the part of the path outside the block: from the launching register off-chip, through external logic and the board, to the port. The timer gives the on-chip path what is left of the cycle. Without -max or -min, the value is used for both setup and hold. OpenSTA reference

  • set_output_delay -clock clk 0.8 [get_ports data_out]
    Requires data_out to be valid 0.8 ns before the next capturing edge of clk.

    Hint: The delay describes what happens after the port, outside the block.

    The output delay is the external path after the port plus the setup time of the register that captures it off-chip. The on-chip path from the launching register to the port must finish in the period minus 0.8 ns. OpenSTA reference

  • set_input_delay -clock clk -max 1.2 [get_ports din] set_input_delay -clock clk -min 0.3 [get_ports din]
    Gives din a latest arrival of 1.2 ns for setup and an earliest of 0.3 ns for hold.

    Hint: Two commands, two flags. Ask which check uses each.

    A setup check uses the latest possible arrival and a hold check uses the earliest, so real interfaces constrain both. -max and -min set separate values and do not replace each other. -rise and -fall are the options that split the value by data transition. OpenSTA reference

  • set_input_delay -clock clk_a 1.0 [get_ports din] set_input_delay -clock clk_b 2.0 -add_delay [get_ports din]
    Gives din two arrival times, one relative to clk_a and one to clk_b, both timed.

    Hint: Two clocks, and a flag on the second command. Ask what it prevents.

    Without -add_delay, a second input delay on the same port replaces the first. With it, both are kept, which models a port driven by devices on two different clocks. OpenSTA reference

  • set_input_delay -clock clk -clock_fall 0.5 [get_ports din]
    Says din arrives 0.5 ns after the falling edge of clk.

    Hint: Distinguish -clock_fall from -fall: one is about the clock, the other the data.

    -clock_fall chooses which edge of the clock the delay is measured from. -fall is different: it restricts the value to falling transitions of the data signal. A falling-edge reference models an external device that launches data on the falling edge, as in DDR (Double Data Rate) interfaces. OpenSTA reference

  • set_output_delay -clock clk -min -0.2 [get_ports dout]
    Requires data to reach dout no sooner than 0.2 ns after the clk edge.

    Hint: A negative value on a minimum delay. Ask which check uses min, and which way it moves.

    The value is used for the hold check. There, the minimum output delay is the external minimum path delay minus the external register's hold time. A negative value means that hold time is longer than the external path, so the on-chip path to the port must supply the difference: data launched at the edge must not reach dout sooner than 0.2 ns. OpenSTA reference

  • set_driving_cell -lib_cell BUF_X2 -pin Z [all_inputs]
    Models every input port as driven by a BUF_X2 output pin.

    Hint: SDC (Synopsys Design Constraints) cannot change the netlist. Ask what the cell is used for.

    SDC (Synopsys Design Constraints) does not change the netlist. The port's slew now depends on its load: the timer uses the library tables of BUF_X2 to compute the delay and transition at each port from the load that port actually drives. This is more realistic than a fixed set_input_transition. The clock port is usually excluded and constrained separately. OpenSTA reference

  • set_input_transition 0.08 [get_ports din]
    Sets a fixed 0.08 ns transition at din, whatever load it drives.

    Hint: Compare it with set_driving_cell: ask whether this value depends on the load.

    The slew is fixed and does not depend on the load. A load-dependent slew comes from set_driving_cell, and a transition limit comes from set_max_transition. OpenSTA reference

  • set_load 0.02 [get_ports data_out]
    Adds 0.02 pF (picofarads) of off-chip capacitance on data_out for its driver.

    Hint: The port is an output. Ask what is on the other side of it.

    The load models the board trace and the receiving pin outside the block. The on-chip cell that drives the port must charge it, which increases that cell's delay and output slew. Capacitance is in the library's unit, which varies: picofarads in many libraries, femtofarads in others such as Nangate45. report_units shows which. A limit on load is set_max_capacitance. OpenSTA reference

  • set_drive 0.5 [get_ports din]
    Models the external driver of din as a 0.5 kilohm resistance.

    Hint: The unit is resistance. Ask which end of the input it describes.

    The drive resistance and the port's load set the input slew and delay. It is the older, simpler alternative to set_driving_cell, which uses a real cell's delay and slew tables and is usually preferred. Resistance is in the library's unit, usually kilohms. OpenSTA reference

  • set_driving_cell -lib_cell NAND2_X1 -from_pin A1 [get_ports din]
    Models din as driven by a NAND2_X1 through its arc from A1.

    Hint: A NAND has more than one input. Ask which arc the option picks.

    The delay and slew come from the NAND2_X1 arc that starts at input A1 and ends at its output. A cell with several inputs has a different delay arc from each one. -from_pin picks the arc, and -input_transition_rise and -input_transition_fall set the slew assumed at that input. OpenSTA reference

  • set_load 0.015 [get_nets n_long]
    Sets the wire capacitance of n_long to 0.015 pF, replacing extracted values.

    Hint: The object is a net, not a port. Ask what part of the net's capacitance this sets.

    On a port the value is external load; on a net it is the net's wire capacitance, in picofarads here. It overrides parasitics read from a SPEF (Standard Parasitic Exchange Format) file for that net. OpenSTA reference

  • set_false_path -from [get_clocks clk_a] -to [get_clocks clk_b]
    Stops timing paths launched by clk_a and captured by clk_b, in that direction only.

    Hint: -from and -to are given. Ask whether the reverse direction is covered too.

    A false path is directional. Paths from clk_b back to clk_a are still timed unless a second command covers them; set_clock_groups covers both directions at once. A path should be declared false only when its timing can never matter, for example a crossing handled by a synchronizer. OpenSTA reference

  • set_false_path -from [get_ports rst_n]
    Removes every timing path that starts at the reset port rst_n.

    Hint: Only -from is given. Ask which checks at the far end also disappear.

    With only -from, every path from the port is removed, including the recovery and removal checks at the registers it resets. That is safe only when the release of reset is synchronized inside the block. Holding a pin constant is set_case_analysis; an ideal network is set_ideal_network. OpenSTA reference

  • set_multicycle_path 2 -setup -from [get_cells a_reg] -to [get_cells b_reg]
    Gives the path from a_reg to b_reg two clock cycles for setup instead of one.

    Hint: The setup edge moves a cycle later. Ask what happens to the hold check by default.

    The setup capture edge moves one cycle later. The hold check moves with it by default, to one cycle after the launch edge, which demands a very long minimum delay. That is why a setup multicycle is almost always paired with a hold multicycle of one less. OpenSTA reference

  • set_multicycle_path 2 -setup -from [get_cells a_reg] -to [get_cells b_reg] set_multicycle_path 1 -hold -from [get_cells a_reg] -to [get_cells b_reg]
    Allows two cycles for setup and moves the hold check back to the launch edge.

    Hint: Two commands, N and N-1. Ask where the hold check ends up.

    The hold multiplier counts how many cycles the hold check moves back from its default position. After -setup N, the rule is -hold N-1, which returns the hold check to the launch edge, the same as a normal single-cycle path. OpenSTA reference

  • set_multicycle_path 2 -setup -start -from [get_clocks clk_fast] -to [get_clocks clk_slow]
    Counts the two setup cycles in periods of the launching clock, clk_fast.

    Hint: Launch and capture clocks differ. Ask which one's period the multiplier counts.

    When the launch and capture clocks differ, the multiplier needs a reference clock. -start uses the launching clock and -end the capturing clock. By default setup multipliers count capture periods (-end) and hold multipliers count launch periods (-start). OpenSTA reference

  • set_max_delay 2.0 -from [get_ports in_a] -to [get_ports out_b]
    Requires the path from in_a to out_b to take at most 2.0 ns.

    Hint: A combinational path between two ports has no clock to constrain it.

    A typical use is a combinational feedthrough from an input port to an output port, which has no register to define a clock-based requirement. On a path that already has a clock requirement, the value replaces it. set_min_delay is the matching lower bound. OpenSTA reference

  • set_min_delay 0.3 -from [get_ports in_a] -to [get_ports out_b]
    Requires the path from in_a to out_b to take at least 0.3 ns.

    Hint: The mirror of a maximum delay. Ask which direction it bounds.

    The minimum delay is checked like a hold requirement. The command states the requirement; an optimization tool may then add delay to meet it, but the constraint itself inserts nothing. OpenSTA reference

  • group_path -name io_in -from [all_inputs]
    Puts every path from an input port into a group reported apart from others.

    Hint: Ask what a report shows per group, and what that hides when everything is in one.

    Each path group has its own worst path. A failing input path in its own group cannot hide the register-to-register paths in theirs, and optimization tools work on the worst path of every group. Commercial tools also accept -weight to set a group's optimization priority. OpenSTA reference

  • set_disable_timing -from A -to Z [get_cells u_mux]
    Deletes the timing arc from pin A to pin Z of u_mux, so no path uses it.

    Hint: Compare it with a false path: ask what happens to the arc itself.

    The arc is removed from the timing graph, so no path of any kind passes through it. Other arcs of the cell stay. Typical uses are breaking a combinational loop and removing an arc that the design never exercises. OpenSTA reference

  • set_case_analysis 0 [get_ports test_mode]
    Holds test_mode at 0 and propagates the constant through the logic.

    Hint: The pin is a mode select. Ask what happens to logic downstream of it.

    The constant propagates through downstream logic, so paths used only in test mode drop out. A multiplexer whose select is 0 passes only its 0 input, so paths through its 1 input disappear. This is how one netlist is timed separately in functional and test modes. A false path from the port would remove only paths starting there; the downstream logic would stay unconstrained by the mode. OpenSTA reference

  • set_max_time_borrow 0.3 [get_cells lat_*]
    Limits the latches lat_* to borrowing at most 0.3 ns after they open.

    Hint: Borrowing is a latch's ability to accept late data. Ask what the number caps.

    Time borrowing is data arriving at a transparent latch after it opens; the late arrival is passed on to the next stage. Capping it keeps the next stage's budget predictable. OpenSTA reference

  • set_data_check -from [get_pins u1/STROBE] -to [get_pins u1/D] -setup 0.1
    Requires u1/D to arrive at least 0.1 ns before u1/STROBE does.

    Hint: Neither pin is a clock. Ask what the -from pin acts as.

    This is a setup check between two data pins. A normal setup check compares data with a clock; a data check compares two data signals: the -from pin is the reference and the -to pin is checked against it. It suits a strobe and the data it samples, or the inputs of a custom macro. OpenSTA reference

  • set_min_pulse_width -high 0.4 [get_clocks clk]
    Requires each high pulse of clk to last at least 0.4 ns.

    Hint: The clock tree can shrink a pulse on its way to the registers.

    The check applies at the register clock pins. Unequal rise and fall delays in the clock tree can shrink a pulse on its way there. The check catches a pulse too narrow for a register to respond to. Without -high or -low, it applies to both. OpenSTA reference

  • set_max_delay 1.0 -from [get_ports din] -to [get_cells cap_reg]
    Requires data from din to meet cap_reg's check within 1.0 ns, setup time included.

    Hint: The path ends at a register, not a port. Ask what else is in the path then.

    When the path ends at a timing check, the check's setup time counts as part of the path, so the data must arrive earlier than 1.0 ns by that amount. The same holds for set_min_delay with the hold time. OpenSTA reference

  • group_path -default -from [all_inputs]
    Returns the paths from input ports to their default path group.

    Hint: The flag is -default. Ask what it undoes.

    group_path -default undoes an earlier grouping for the matching paths. By default a path belongs to the group of the clock that captures it. OpenSTA reference

  • set_disable_timing [get_cells u_ro]
    Disables every timing arc through u_ro but keeps its checks.

    Hint: A whole instance, no -from or -to. Ask whether its internal checks go too.

    With an instance and no -from or -to, all arcs through it are disabled; the timing checks inside it, such as a register's setup and hold, stay. A typical use is breaking the loop of a ring oscillator. OpenSTA reference

  • set_case_analysis rising [get_pins u_sel/S]
    Times only rising transitions at u_sel/S and drops its falling ones.

    Hint: The value is a transition, not a constant. Ask what still switches.

    Besides constants 0 and 1, case analysis accepts rising and falling. A transition value keeps the pin switching but limits it to one direction, for a signal that is only ever asserted one way during operation. OpenSTA reference

  • set_max_transition 0.15 [current_design]
    Sets a 0.15 ns slew limit on every pin of the design, as a rule to fix.

    Hint: Ask whether this describes the design or constrains it.

    A slow transition increases delay, short-circuit power, and sensitivity to noise. Violations are fixed by buffering or upsizing, usually before timing optimization. Library pins carry their own limits as well. OpenSTA reference

  • set_max_transition 0.5 [current_design] ;# library pin limits are 0.3
    Leaves the library's 0.3 ns limit in force on those pins.

    Hint: Two limits now exist on those pins. Ask which one wins.

    The stricter limit applies. A design rule can come from the library (per pin) and from the constraints (per design, port, or clock). Where both exist, the tighter one is checked, so an SDC (Synopsys Design Constraints) limit can tighten the library value but never relax it. OpenSTA reference

  • set_max_transition -clock_path 0.08 [get_clocks clk]
    Sets a 0.08 ns slew limit on the clock network of clk only.

    Hint: The object is a clock and the flag narrows it further. Ask to what.

    On a clock object the limit applies to every pin in that clock's domain; -clock_path narrows it to the clock network. Clock slews affect skew, pulse width, and power, so they are usually held tighter than data slews. OpenSTA reference

  • set_max_capacitance 0.1 [current_design]
    Sets 0.1 pF (picofarads) as the most load any driver may drive.

    Hint: The load a driver sees is wire plus pins. Ask what the limit protects.

    The load is the net's wire capacitance plus the input pins it drives. A cell's delay tables cover a limited range of loads; beyond it the delay is extrapolated and unreliable. Violations are fixed by buffering or upsizing the driver. OpenSTA reference

  • set_max_fanout 16 [current_design]
    Limits every driver in the design to a fanout of 16.

    Hint: Fanout counts loads, not length. Ask how a violation is fixed.

    Violations are fixed by splitting the net with buffers. Fanout adds up the fanout load of the pins a driver drives, usually 1 each. It is a coarse stand-in for capacitance and slew, so many flows rely on the transition and capacitance limits instead. OpenSTA reference

  • set_min_capacitance 0.002 [get_ports dout]
    Requires the driver of dout to see at least 0.002 pF (picofarads) of load.

    Hint: A minimum, not a maximum. Ask when too little load is a problem.

    A minimum load is uncommon. It applies when a cell is characterized, or stable, only above some load. The fix is to add load, for example a larger wire or an extra pin. OpenSTA reference

  • set_timing_derate -late 1.05
    Scales late delays up by 5%, to model slow on-chip variation.

    Hint: Late values are the ones that hurt when larger. Ask which paths those are.

    Late values are the ones that hurt when larger: the data path of a setup check and the capture clock path of a hold check. Without -clock or -data, both clock and data paths are derated; without -cell_delay or -net_delay, both kinds of delay are. OpenSTA reference

  • set_timing_derate -early 0.95 -cell_delay
    Scales early cell delays down by 5%, leaving net delays unchanged.

    Hint: Two restrictions: early paths, and one kind of delay.

    An early derate below 1 and a late derate above 1 make the analysis pessimistic in both directions at once. On a clock path shared by launch and capture, the two derates cannot both be true; CRPR (Clock Reconvergence Pessimism Removal) removes that part. OpenSTA reference

  • set_operating_conditions ss_0p72v_125c
    Selects the operating condition ss_0p72v_125c from a loaded library.

    Hint: The name looks like a corner. Ask where such a condition is defined.

    An operating condition (process, voltage, temperature) is defined inside a loaded library; the command picks one by name for delay calculation. Current flows usually load one library per corner instead, and analyze several corners. OpenSTA reference

  • set_operating_conditions -analysis_type on_chip_variation -min ff_cond -max ss_cond
    Times setup with slow data and a fast clock, and hold the reverse.

    Hint: On-chip variation assumes both conditions at once. Ask which side gets which.

    On-chip variation assumes both conditions can occur on the same die at once. A setup check takes the max condition for data and the min for the clock; a hold check takes the reverse. The bc_wc type instead applies one condition to both clock and data. OpenSTA reference

  • get_ports data*
    Returns the top-level ports whose names start with data.

    Hint: A port belongs to the design's boundary, not to an instance.

    A port is a pin of the top-level design itself, where the block meets the outside. Pins of instances inside the design are found with get_pins. OpenSTA reference

  • get_pins u_alu/*
    Returns every pin of the instance u_alu.

    Hint: A pin belongs to an instance. Ask what u_alu/* covers.

    A pin name is the instance name, the hierarchy separator, and the pin name, as in u_alu/A. When u_alu is a hierarchical block, its pins are the block's boundary pins. OpenSTA reference

  • get_clocks clk*
    Returns the defined clocks whose names start with clk, not ports or pins.

    Hint: A clock is a constraint object with its own name, separate from the port.

    A clock is a constraint object with its own name, which need not match the port it is defined on. Commands such as set_clock_uncertainty and set_false_path -from expect clock objects; passing a port applies the constraint at that point instead. OpenSTA reference

  • get_cells -hierarchical *_reg*
    Returns instances matching *_reg* at every level below this one.

    Hint: Ask what the pattern would match without the flag.

    Without -hierarchical, a pattern is matched only at the current level of hierarchy. With it, the search descends into every block below. OpenSTA reference

  • get_nets -of_objects [get_pins u1/Z]
    Returns the net connected to pin u1/Z.

    Hint: It walks connectivity rather than matching a name.

    -of_objects walks the connectivity instead of matching names: the net of a pin, the pins of a net, or the pins of a cell. OpenSTA reference

  • all_inputs
    Returns every input port of the design, including clock inputs.

    Hint: Ask whether the clock port counts as an input.

    The clock port is an input too, so set_input_delay applied to all_inputs also puts an input delay on the clock. Flows remove the clock port from the list first. OpenSTA reference

  • set_output_delay -clock clk 0.5 [all_outputs]
    Applies a 0.5 ns output delay relative to clk to every output port.

    Hint: Ask what set of ports the command returns, and what it leaves out.

    all_outputs returns the top-level output ports. Combined with a single output delay it is the usual first-pass boundary constraint, refined later for ports with different external timing. OpenSTA reference

  • all_registers -clock clk_a
    Returns the registers and latches clocked by clk_a.

    Hint: By default it returns instances. Ask whether latches are among them.

    By default the result is register instances, both flip-flops and latches. -clock_pins, -data_pins, -async_pins, and -output_pins return pins instead; -edge_triggered and -level_sensitive pick one kind. OpenSTA reference

  • all_clocks
    Returns every defined clock, including generated and virtual clocks.

    Hint: Ask whether a clock with no pin still counts.

    The result is clock objects: every clock from create_clock and create_generated_clock, whether it sits on a port, on an internal pin, or on nothing (a virtual clock). OpenSTA reference

  • current_design top
    Makes top the design that the following commands apply to.

    Hint: Several designs can be loaded. Ask what the command picks.

    With several designs loaded, constraints apply to the current one. Constraint files often begin with it so they are read in the right context. OpenSTA reference

  • get_lib_cells */BUF_*
    Returns the library cells named BUF_* in every loaded library.

    Hint: The pattern names a library. Ask whether the result is in the design.

    No instances are returned. Library objects are the cell definitions; design objects are the instances of them in the netlist. A library cell is named with its library, as in lib/BUF_X2. OpenSTA reference

  • get_lib_pins */BUF_X2/Z
    Returns the Z pin of the library cell BUF_X2, not a pin of any instance.

    Hint: The pattern names a library cell's pin. Ask which pin it is.

    A library pin belongs to the cell definition. It carries the pin's library data, such as its capacitance and design-rule limits. OpenSTA reference

  • get_libs *ss*
    Returns the loaded libraries whose names contain ss.

    Hint: Ask whether this searches files on disk or what is already loaded.

    It searches libraries already loaded, for example to pick the slow-corner library by name. Reading a library from disk is a tool command, not part of SDC (Synopsys Design Constraints). OpenSTA reference

  • get_pins -of_objects [get_nets n1] -filter "direction==output"
    Returns the driver of net n1, the pin on it whose direction is output.

    Hint: A net has one output pin among its pins. Ask what that pin is.

    -filter keeps only objects whose properties match the expression. Combined with -of_objects, this is the usual way to find the pin that drives a net. OpenSTA reference

  • get_ports -regexp {data\[[0-3]\]}
    Returns the ports data[0] through data[3], using a regular expression.

    Hint: Ask what the brackets mean once the pattern is a regular expression.

    Without -regexp, patterns are wildcard patterns in which * matches any text and ? one character. -regexp switches to regular expressions, and -nocase then makes matching case-insensitive. OpenSTA reference

  • get_cells -quiet u_spare*
    Returns the matching cells, or an empty list with no error if none match.

    Hint: Ask what normally happens when a pattern matches nothing.

    A pattern that matches nothing normally reports an error. -quiet suits constraints shared between designs where some objects may not exist. OpenSTA reference

  • set_units -time ns -capacitance pF
    Declares the file's times are in ns and capacitances in pF.

    Hint: Numbers in a constraint file carry no units of their own.

    Here ns is nanoseconds and pF is picofarads. Numbers in SDC (Synopsys Design Constraints) carry no units of their own. Without this declaration they are read in the library's units, so a file written for one library can be misread with another. OpenSTA checks the declared units and warns if they differ from the ones it uses. OpenSTA reference

  • current_instance u_core
    Makes later object names resolve relative to the instance u_core.

    Hint: Ask what a relative name means afterwards.

    After it, get_pins alu/A means u_core/alu/A. This lets a block's own constraints be applied inside a larger design. With no argument, it returns to the top level. OpenSTA reference

  • set_hierarchy_separator .
    Makes names use . instead of / between hierarchy levels.

    Hint: The default separator is a slash. Ask what this changes.

    The default separator is /, as in u_core/alu/A. A file written with u_core.alu.A style names needs this command so its names resolve. OpenSTA reference

  • set_voltage 0.72 -object_list VDD
    Sets the supply voltage on the power net VDD to 0.72 V.

    Hint: The object is a power net. Ask what the number describes.

    In a design with several supplies, each power net has its own voltage. -min sets a separate value for minimum-delay analysis. The command describes the supply; it does not create the net. OpenSTA reference

  • create_voltage_area -name VA_LOW -coordinate {100 100 400 300} [get_cells u_lp]
    Reserves a region of the die for the cells of u_lp, on their own supply.

    Hint: Coordinates are given. Ask whether this is a physical or an electrical statement.

    It is a physical constraint for placement: the cells of u_lp go inside the region and all others stay out, so the region can have its own power grid. Timing analysis ignores it. Coordinates are in micrometres. OpenSTA reference

  • Two clocks in the design never appear in the same logic. You want every path between them left unchecked, in both directions, with one command that also covers paths added later.
    set_clock_groups -asynchronous -group {clk_a} -group {clk_b}

    Hint: A one-way exception would leave the other direction still checked.

    Grouping cuts every path between the groups, both ways, and keeps doing so for paths created later. A false path as written covers one direction only, so the reverse paths are still timed. Uncertainty adds margin rather than removing the check. OpenSTA reference

  • You are constraining a block. Outside it, the logic between this output port and the register that captures it takes 0.4 nanoseconds.
    set_output_delay 0.4 -clock clk [get_ports out]

    Hint: The delay being described happens after the port, not before it.

    The number is the external delay the block must leave room for, so it is subtracted from the period when the path to the port is checked. A maximum delay would instead replace the clock-based check entirely, and a load is a capacitance, not a time. OpenSTA reference

  • A path between two registers on the same clock is allowed two clock cycles to settle, rather than one.
    set_multicycle_path 2 -setup -from [get_pins a_reg/CK] -to [get_pins b_reg/D]

    Hint: One of these relaxes the check; the others remove it or replace it.

    The path is still checked, against a capture edge two cycles later. A false path would stop it being checked at all, and a maximum delay of 2 would set an absolute limit in nanoseconds unrelated to the clock. The hold form moves the hold check instead, which is the companion command, not this one. OpenSTA reference

  • No pin in the design may be driven with a transition slower than 0.15 nanoseconds, whatever the library allows.
    set_max_transition 0.15 [current_design]

    Hint: The limit is on how sharp an edge is, not on what it drives.

    This is a design rule, checked at every pin and repaired by sizing and buffering. The capacitance form limits load instead, the clock form sets an assumed transition on an ideal clock, and the input form describes what drives the ports. OpenSTA reference

  • create_clock -name clk -period 2.0
    No port is given, so this defines a virtual clock instead.

    Hint: Ask what this clock is attached to.

    A clock with no object list is a virtual clock, which exists for constraining ports but drives nothing in the design. Every register meant to be on it is then unclocked, and the timer reports the endpoints as unconstrained rather than failing. OpenSTA reference

  • set_multicycle_path 2 -setup -from [get_pins a_reg/CK] -to [get_pins b_reg/D]
    Without a matching hold exception, hold is now checked a cycle late.

    Hint: Ask which check moved when the setup edge moved.

    Moving the capture edge for setup moves the hold check with it, so hold is checked against the edge before the new capture edge, one full cycle after launch. Almost nothing meets that. The usual pair is a setup value of N with a hold value of N minus one. OpenSTA reference

  • set_input_delay 0.5 [get_ports data_in]
    No clock is named, so the delay has no edge to be relative to.

    Hint: An arrival time is always measured from something.

    An input delay says how late the data arrives after an edge of some clock, so the clock has to be named. Without it the command is an error, and in a script that ignores errors the port is left unconstrained and quietly never checked. OpenSTA reference

  • set_false_path -from [get_pins dpath/a_reg[9]/Q]
    The bus index is taken as a command, so the line fails.

    Hint: Count the square brackets and ask what each pair means to the interpreter.

    Square brackets are command substitution, so the interpreter tries to run a command named 9. The name has to be braced or escaped, as in {dpath/a_reg[9]/Q}, or built with a variable that is passed straight through. This is the commonest mistake in a constraints file. OpenSTA reference

  • create_clock -period 2.0 -name clk -waveform {0 ____} [get_ports clk]
    1.0

    Hint: The clock is meant to spend half its period high.

    The two numbers are the times of the first rising and the first falling edge, so a symmetric clock of period 2 falls at 1. This is also the default, which is why the option is usually left out and only appears when the duty cycle is not even. OpenSTA reference

  • set_input_delay 0.4 ____ clk [get_ports data_in]
    -clock

    Hint: The missing word names which clock the arrival is measured against.

    Every port constraint is relative to a clock edge, and this is the option that names it. Its companions are -clock_fall for an arrival relative to the falling edge, and -add_delay to keep an earlier constraint on the same port rather than replacing it. OpenSTA reference

  • set_timing_derate ____ 1.05
    -late

    Hint: The paths being slowed are the late ones, whichever check they serve.

    Derating is expressed as early and late, not as minimum and maximum, because the same path can be the late one in a setup check and the early one in a hold check. A factor above one slows the late paths; the early ones take a factor below one. OpenSTA reference

  • Put these in the order a timing session must run them.
    1. read_liberty NangateOpenCellLibrary_typical.lib
    2. read_verilog gcd.v
    3. link_design gcd
    4. read_sdc gcd.sdc

    Hint: Each line needs something the line before it created.

    The netlist names cells, so the library has to be read first. Linking resolves those names into a design, and only then do objects exist for the constraints to find. A constraints file read before linking matches nothing, and usually says so only as a warning. OpenSTA reference