Games / Command flash cards / OpenROAD-flow-scripts variables / Synthesis

Synthesis

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SourceThese cards cover the make variables that drive OpenROAD-flow-scripts, the reference flow built on OpenROAD. Each card shows a line as it appears in a design's or a platform's config.mk, and each answer links to that variable in the flow's own variable reference. Variables come and go between releases; this deck follows the version in the openroad/orfs image. Reference: flow variable reference (OpenROAD-flow-scripts on GitHub).

All 12 cards in this section, with answers

export SYNTH_HIERARCHICAL = 1

Keeps the module hierarchy through synthesis instead of flattening it.

Hint: The default flattens everything. Ask what is kept instead.

Flat synthesis optimizes across module boundaries and usually gives better results, but it loses the names that make a large design navigable. Hierarchical synthesis keeps modules above the size set by SYNTH_MINIMUM_KEEP_SIZE and flattens the rest. OpenROAD-flow-scripts reference
export SYNTH_MINIMUM_KEEP_SIZE = 1000

Keeps modules bigger than 1000 basic gates and flattens smaller ones.

Hint: The unit is not gates, and not microns. It is relative to one small cell.

The size is measured in units of the platform's basic two-input gate area, so it means the same thing on different technologies. It applies to hierarchical synthesis: small modules are flattened so they can be optimized across their boundaries anyway. OpenROAD-flow-scripts reference
export ABC_AREA = 1

Tells the synthesis optimizer to aim for area rather than speed.

Hint: The two strategies pull in opposite directions.

ABC (And-Inverter-Graph optimizer) is the engine inside Yosys that maps logic to library cells. The default is the speed strategy; setting this switches to the area strategy, which gives a smaller but slower netlist. OpenROAD-flow-scripts reference
export ABC_DRIVER_CELL = BUF_X1

Says what drives the design's inputs while synthesis estimates timing.

Hint: Synthesis has no placement and no real drivers yet, so it needs an assumption.

Without a driver the input slew is unknown, and slew drives every delay after it. This variable and ABC_LOAD_IN_FF, the load on the outputs, are the boundary assumptions synthesis works from. OpenROAD-flow-scripts reference
export ABC_LOAD_IN_FF = 3

Sets the capacitance synthesis assumes on the design's outputs.

Hint: The unit is in the name, and it is the other end of the design from the driver.

Outputs drive something off-block, and the size of that load decides how strongly synthesis builds the last stage. The value is in femtofarads, hence the name. OpenROAD-flow-scripts reference
export ADDER_MAP_FILE = $(PLATFORM_DIR)/cells_adders.v

Maps the design's adders onto the platform's own adder cells.

Hint: Ask what synthesis would otherwise build an adder out of.

Left alone, synthesis builds an adder from ordinary gates. A platform with dedicated full-adder cells maps to them instead, which is smaller and faster. The same mechanism exists for clock gates and latches. OpenROAD-flow-scripts reference
export TIEHI_CELL_AND_PORT = LOGIC1_X1 Z

Names the cell and pin that synthesis uses to drive a constant 1.

Hint: Two values: which cell, and which of its pins.

A gate input must never be tied straight to the supply rail, since that exposes the thin oxide. A tie cell provides a safe constant instead. TIELO_CELL_AND_PORT is the same for logic 0. OpenROAD-flow-scripts reference
export SYNTH_NETLIST_FILES = ./results/nangate45/gcd/base/1_synth.v

Skips synthesis and starts the flow from the netlist given.

Hint: Ask which stage of the flow stops being needed.

This is how a netlist from elsewhere, or from an earlier run, enters the flow. It is also the way to iterate on placement and routing without paying for synthesis each time. OpenROAD-flow-scripts reference
export SWAP_ARITH_OPERATORS = 1

Lets the flow rebuild adders and multipliers in a faster architecture.

Hint: The same arithmetic can be built in several shapes, with different speeds.

An adder can be a ripple-carry, a Kogge-Stone, a Brent-Kung, and more, all with the same function but different delay and area. The flow can swap the module for another architecture when timing needs it. OpenROAD-flow-scripts reference
export CLKGATE_MAP_FILE = $(PLATFORM_DIR)/cells_clkgate.v

Maps inferred clock gating onto the platform's clock-gating cells.

Hint: The same mapping mechanism as the adder file, for a different kind of cell.

A clock gate built from ordinary gates can glitch the clock. The platform's integrated cell latches the enable so it cannot. The file tells synthesis which cell to use; LATCH_MAP_FILE does the same for latches. OpenROAD-flow-scripts reference
export LATCH_MAP_FILE = $(PLATFORM_DIR)/cells_latch.v

Maps inferred latches onto the platform's own latch cells.

Hint: Ask what synthesis does with an inferred latch when no such cell is named.

A latch inferred from incomplete code has to become some real cell. Without a mapping file, synthesis builds one from gates, which is larger and less predictable than the library's own latch. OpenROAD-flow-scripts reference
export SYNTH_HDL_FRONTEND = slang

Reads the sources with the slang front end, not the default one.

Hint: It changes how the sources are read, before any logic is built.

The sources are parsed by slang before any logic is built. The default reader handles a subset of SystemVerilog. The slang front end supports considerably more of the language, which is what designs written in modern SystemVerilog need. Leaving the variable empty keeps the default. OpenROAD-flow-scripts reference