Games / Command flash cards / OpenROAD-flow-scripts variables / All sections

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Each card shows a command to explain. A missed card returns later in the round and starts the schedule over. A card answered correctly moves up the schedule and next appears after 1, 3, 7, then 21 days. Keys 1 to 4 choose an option, h shows a hint, and Enter moves on. A hint keeps the card where it is on the schedule. An ordering card is answered by clicking its items in order, and one wrong click ends it. Time values are in nanoseconds. Progress is stored in this browser.

SourceThese cards cover the make variables that drive OpenROAD-flow-scripts, the reference flow built on OpenROAD. Each card shows a line as it appears in a design's or a platform's config.mk, and each answer links to that variable in the flow's own variable reference. Variables come and go between releases; this deck follows the version in the openroad/orfs image. Reference: flow variable reference (OpenROAD-flow-scripts on GitHub).

All 84 cards in this deck, with answers

export DESIGN_NAME = gcd

Names the top-level module that the flow builds.

Hint: The flow has to know which module is the design, out of everything it reads.

Every stage works on this module, and it must match a module in the Verilog that is read. DESIGN_NICKNAME is the separate variable that renames the output directory. OpenROAD-flow-scripts reference
export DESIGN_NICKNAME = riscv32i

Changes the output directory name without changing the module built.

Hint: Compare it with DESIGN_NAME: only one of the two has to match the Verilog.

Results go to results/<platform>/<nickname>/. It exists for designs whose top module name is unwieldy or collides with another design's. OpenROAD-flow-scripts reference
export PLATFORM = nangate45

Selects the process design kit the design is built with.

Hint: One word pulls in a whole directory of technology files.

The platform directory supplies the technology and cell files, the site, the power grid script, and its own default variables. Changing this one line rebuilds the same design on a different technology. OpenROAD-flow-scripts reference
export VERILOG_FILES = $(sort $(wildcard ./designs/src/gcd/*.v))

Lists the design's source files for synthesis to read.

Hint: Ask what synthesis is given to read.

The list is read by synthesis, in order. sort around a wildcard keeps the order stable so a build is repeatable. Header directories are given separately with VERILOG_INCLUDE_DIRS. OpenROAD-flow-scripts reference
export SDC_FILE = ./designs/nangate45/gcd/constraint.sdc

Gives the timing constraints, starting with the clock definition.

Hint: It is read early and then used by every stage that thinks about timing.

The file holds the SDC (Synopsys Design Constraints) commands: clock definitions, input and output delays, and any exceptions. Synthesis, placement, clock tree synthesis, and routing all read it, and later stages read the version each earlier stage wrote. OpenROAD-flow-scripts reference
export ADDITIONAL_LEFS = ./designs/src/tiny/sram.lef

Adds hard macro geometry: outline, pins, and blockages.

Hint: A hardened macro is not in the standard cell library. Ask what its shape comes from.

A macro needs three things in the flow: its shape from a LEF (Library Exchange Format) file here, its timing from ADDITIONAL_LIBS, and its layout from ADDITIONAL_GDS at the end. The shape is stored in the design database; the timing is not. OpenROAD-flow-scripts reference
export ADDITIONAL_LIBS = ./designs/src/tiny/sram.lib

Adds hard macro timing and power data for analysis.

Hint: The counterpart of the macro's shape.

The library is read in each session that times the design, because it is not stored in the database, unlike the geometry. A macro missing from here times as if it had no delay at all. OpenROAD-flow-scripts reference
export ADDITIONAL_GDS = ./designs/src/tiny/sram.gds

Adds the macro's real layout for the final merged layout file.

Hint: It matters only at the very end, when one file has to contain everything.

Through the flow a macro is only an outline with pins. The finishing stage merges the real layout of each macro into the design's own layout, which is what goes to the foundry. OpenROAD-flow-scripts reference
export BLOCKS = aes_cipher_top

Names sub-blocks that are hardened first and used as macros above.

Hint: It turns part of your own design into something the top level treats as a macro.

In a hierarchical run each named block goes through the flow on its own and produces an abstract and a timing model. The top level then places it as a macro, which is how a design too big for one flat run is built. OpenROAD-flow-scripts reference
export SYNTH_HIERARCHICAL = 1

Keeps the module hierarchy through synthesis instead of flattening it.

Hint: The default flattens everything. Ask what is kept instead.

Flat synthesis optimizes across module boundaries and usually gives better results, but it loses the names that make a large design navigable. Hierarchical synthesis keeps modules above the size set by SYNTH_MINIMUM_KEEP_SIZE and flattens the rest. OpenROAD-flow-scripts reference
export SYNTH_MINIMUM_KEEP_SIZE = 1000

Keeps modules bigger than 1000 basic gates and flattens smaller ones.

Hint: The unit is not gates, and not microns. It is relative to one small cell.

The size is measured in units of the platform's basic two-input gate area, so it means the same thing on different technologies. It applies to hierarchical synthesis: small modules are flattened so they can be optimized across their boundaries anyway. OpenROAD-flow-scripts reference
export ABC_AREA = 1

Tells the synthesis optimizer to aim for area rather than speed.

Hint: The two strategies pull in opposite directions.

ABC (And-Inverter-Graph optimizer) is the engine inside Yosys that maps logic to library cells. The default is the speed strategy; setting this switches to the area strategy, which gives a smaller but slower netlist. OpenROAD-flow-scripts reference
export ABC_DRIVER_CELL = BUF_X1

Says what drives the design's inputs while synthesis estimates timing.

Hint: Synthesis has no placement and no real drivers yet, so it needs an assumption.

Without a driver the input slew is unknown, and slew drives every delay after it. This variable and ABC_LOAD_IN_FF, the load on the outputs, are the boundary assumptions synthesis works from. OpenROAD-flow-scripts reference
export ABC_LOAD_IN_FF = 3

Sets the capacitance synthesis assumes on the design's outputs.

Hint: The unit is in the name, and it is the other end of the design from the driver.

Outputs drive something off-block, and the size of that load decides how strongly synthesis builds the last stage. The value is in femtofarads, hence the name. OpenROAD-flow-scripts reference
export ADDER_MAP_FILE = $(PLATFORM_DIR)/cells_adders.v

Maps the design's adders onto the platform's own adder cells.

Hint: Ask what synthesis would otherwise build an adder out of.

Left alone, synthesis builds an adder from ordinary gates. A platform with dedicated full-adder cells maps to them instead, which is smaller and faster. The same mechanism exists for clock gates and latches. OpenROAD-flow-scripts reference
export TIEHI_CELL_AND_PORT = LOGIC1_X1 Z

Names the cell and pin that synthesis uses to drive a constant 1.

Hint: Two values: which cell, and which of its pins.

A gate input must never be tied straight to the supply rail, since that exposes the thin oxide. A tie cell provides a safe constant instead. TIELO_CELL_AND_PORT is the same for logic 0. OpenROAD-flow-scripts reference
export SYNTH_NETLIST_FILES = ./results/nangate45/gcd/base/1_synth.v

Skips synthesis and starts the flow from the netlist given.

Hint: Ask which stage of the flow stops being needed.

This is how a netlist from elsewhere, or from an earlier run, enters the flow. It is also the way to iterate on placement and routing without paying for synthesis each time. OpenROAD-flow-scripts reference
export SWAP_ARITH_OPERATORS = 1

Lets the flow rebuild adders and multipliers in a faster architecture.

Hint: The same arithmetic can be built in several shapes, with different speeds.

An adder can be a ripple-carry, a Kogge-Stone, a Brent-Kung, and more, all with the same function but different delay and area. The flow can swap the module for another architecture when timing needs it. OpenROAD-flow-scripts reference
export CORE_UTILIZATION = 40

Sizes the core so the cells fill 40% of it, leaving the rest free.

Hint: It is a percentage, and it decides a size rather than reporting one.

The die size follows from the cell area and this number, together with CORE_ASPECT_RATIO and CORE_MARGIN. Low utilization eases routing and wastes area; high utilization does the opposite. Giving DIE_AREA and CORE_AREA instead sets the size directly. OpenROAD-flow-scripts reference
export CORE_ASPECT_RATIO = 2.0

Makes the core twice as tall as it is wide.

Hint: Read the ratio in the documented order: height over width.

It only applies when the size comes from CORE_UTILIZATION. A shape other than square is used to fit a block into a fixed slot at the top level, or to suit a design's pin sides. OpenROAD-flow-scripts reference
export CORE_MARGIN = 2

Leaves 2 microns between the core area and the die edge.

Hint: It is the space between two boundaries, and something has to live there.

The margin is where the power ring and the boundary pins go, so a core pressed against the die edge leaves nowhere to bring power in. One value sets all four sides; four values set them separately. OpenROAD-flow-scripts reference
export DIE_AREA = 0 0 100.13 100.8 export CORE_AREA = 10.07 11.2 90.25 91

Sets the die and the core rectangles directly, in microns.

Hint: Four numbers each: two corners. Ask which rectangle sits inside the other.

Each is a lower-left and an upper-right corner. Giving both replaces the utilization-based sizing, which is how a block gets the exact size a top-level floorplan has reserved for it. OpenROAD-flow-scripts reference
export PLACE_SITE = FreePDK45_38x28_10R_NP_162NW_34O

Names the site whose height and width the placement rows are built from.

Hint: It comes from the technology file, and it decides the shape of a row.

A site is the smallest legal cell footprint in the technology. Rows are one site high, and every cell's width is a whole number of sites, which is what makes legalization possible. OpenROAD-flow-scripts reference
export MACRO_PLACE_HALO = 10 10

Keeps a 10 micron band clear around each macro, in x and y.

Hint: Two numbers, and the space they describe stays empty.

Cells packed against a macro leave no room to reach the macro's pins or to add buffers later. The halo reserves that room. It is used by automatic macro placement. OpenROAD-flow-scripts reference
export MACRO_PLACEMENT_TCL = ./designs/nangate45/bp/macro.tcl

Places named macros by hand, leaving the rest to the automatic placer.

Hint: You can use it for some macros and leave the others alone.

The file holds place_macro commands. Any macro it does not place is left to rtl_macro_placer, which is how a floorplan fixes the macros that matter and lets the tool handle the rest. OpenROAD-flow-scripts reference
export IO_CONSTRAINTS = ./designs/nangate45/gcd/io.tcl

Restricts where the boundary pins may be placed, by edge or by name.

Hint: Ask which stage reads it, and what it would otherwise decide for itself.

The file holds set_io_pin_constraint and related commands, read before place_pins. Without it the pin placer is free to put any pin anywhere on the boundary. The layers are set separately by IO_PLACER_H and IO_PLACER_V. OpenROAD-flow-scripts reference
export PDN_TCL = $(PLATFORM_DIR)/grid_strategy-M1-M4-M7.tcl

Gives the script that describes the power grid to build.

Hint: The file name names three layers. Ask what is built across them.

The script holds the grid definition commands: the rails, the straps per layer, and the layer pairs to connect, which pdngen then builds. It usually comes from the platform, since the grid depends on the metal stack. OpenROAD-flow-scripts reference
export TAPCELL_TCL = $(PLATFORM_DIR)/tapcell.tcl

Gives the script that inserts the well taps and the endcap cells.

Hint: Two kinds of cell, both about the rows rather than the logic.

The script calls tapcell with the platform's masters and spacing. The spacing comes from the foundry's rule on how far a transistor may be from a well tap, so the script belongs to the platform. OpenROAD-flow-scripts reference
export FLOORPLAN_DEF = ./designs/nangate45/bp/floorplan.def

Starts from a ready-made floorplan instead of creating one.

Hint: Ask what it replaces, rather than what it adds.

The file brings the die and core areas, the rows, and often the pin and macro placement. It is mutually exclusive with sizing by utilization or by explicit areas, and it is how an externally agreed floorplan enters the flow. OpenROAD-flow-scripts reference
export PLACE_DENSITY = 0.60

Asks global placement to spread cells to 60% density per bin.

Hint: It is a target for the placer, not a property of the floorplan.

Utilization sizes the die; this decides how tightly the placer packs cells within it. A lower value spreads cells out, which eases routing and lengthens wires; a higher value does the opposite and runs faster. OpenROAD-flow-scripts reference
export PLACE_DENSITY_LB_ADDON = 0.20

Raises the flow's computed lower bound on density by 0.20.

Hint: The flow computes a lower bound for density on its own. Ask what this does to it.

The flow derives a minimum sensible density from the design, and this adds headroom above it, which spreads cells further. It is the usual knob for a design that places easily but routes badly. OpenROAD-flow-scripts reference
export CELL_PAD_IN_SITES_GLOBAL_PLACEMENT = 4

Reserves four sites of empty space beside each cell.

Hint: The unit is sites, and the padding is not real silicon.

The padding applies during global placement. It is a placement fiction that leaves room for routing to reach pins and for repair to add cells. It is set separately for global and detailed placement, usually larger for global. OpenROAD-flow-scripts reference
export IO_PLACER_H = metal3 export IO_PLACER_V = metal2

Puts pins on horizontal tracks on metal3 and on vertical tracks on metal2.

Hint: Horizontal and vertical describe the tracks, not which edge the pin sits on.

The two variables become the -hor_layers and -ver_layers arguments of place_pins. The layer has to match the track direction, since the pin shape sits on a track. OpenROAD-flow-scripts reference
export GPL_TIMING_DRIVEN = 0

Turns off timing-driven placement, which is on by default.

Hint: Check the default before deciding what setting it to 0 means.

Timing-driven placement weights critical nets so they are shortened, at the cost of runtime. It is on by default and turned off for quick exploration runs or when the timing estimate is not yet meaningful. OpenROAD-flow-scripts reference
export CLUSTER_FLOPS = 1

Groups flip-flops into multi-bit cells where the library has them.

Hint: It only works if the library has the cells for it.

One multi-bit register serves several bits from a single clock pin, so the clock tree drives fewer sinks and spends less power. The flow ignores the setting on a platform whose library has no such cells. OpenROAD-flow-scripts reference
export DONT_USE_CELLS = TAPCELL_X1 FILLCELL_X1 AOI211_X1 OAI211_X1

Keeps optimization from choosing those cells anywhere in the flow.

Hint: Ask why a cell that exists would be excluded from use.

Cells are excluded when they are hard to route into, when they belong to another purpose (a tap or a filler), or when they behave badly. The list becomes set_dont_use inside the flow. OpenROAD-flow-scripts reference
export ENABLE_DPO = 0

Turns off the detailed placement optimization pass, which is on by default.

Hint: Another one where the default matters. It names an optimization after legalization.

The pass is improve_placement: local swaps and shifts that shorten wires while keeping the placement legal. It is turned off when it costs more runtime than it is worth, or to keep a placement stable. OpenROAD-flow-scripts reference
export CTS_CLUSTER_SIZE = 30

Allows at most 30 clock sinks in one cluster under a buffer.

Hint: A cluster is a group of sinks that will share one buffer.

Sinks are grouped before the tree is built, and each group gets its own buffer, which becomes a leaf of the tree above. A larger cluster means fewer buffers and more load on each. CTS_CLUSTER_DIAMETER limits the same group by distance instead. OpenROAD-flow-scripts reference
export CTS_CLUSTER_DIAMETER = 100

Keeps a clock sink cluster within 100 microns across.

Hint: The unit is microns, so this limit is geometric.

A cluster that is small in count can still be spread across the block, and then its buffer drives a long wire to each sink. The diameter limit keeps a cluster compact; the two limits are used together. OpenROAD-flow-scripts reference
export CTS_BUF_DISTANCE = 60

Puts a buffer roughly every 60 microns along the clock tree's wires.

Hint: It concerns the wire between buffers, not the sinks.

Wire delay grows with the square of length, so a long clock wire is split by buffers. Setting the distance makes the tree regular; leaving it unset lets the tool choose from its characterization. OpenROAD-flow-scripts reference
export CTS_LIB_NAME = NangateOpenCellLibrary

Names the library that the clock buffers are chosen from.

Hint: Ask where the clock buffers are chosen from when several libraries are loaded.

A run may load several libraries, including macro libraries and different threshold-voltage flavours. Naming one keeps clock buffer selection inside it. OpenROAD-flow-scripts reference
export SKIP_CTS_REPAIR_TIMING = 1

Skips the timing repair that normally follows clock tree synthesis.

Hint: Ask what is being traded away, and when that would be acceptable.

Repair after the clock tree is often the longest step of a run, because real skew appears there for the first time. Skipping it suits early exploration or a fast test run, and it leaves timing unfixed. OpenROAD-flow-scripts reference
export MIN_ROUTING_LAYER = metal2 export MAX_ROUTING_LAYER = metal10

Confines routing to metal2 through metal10, leaving metal1 alone.

Hint: Ask why the lowest layer is not metal1.

metal1 is left out because the standard cells' own pins and supply rails already occupy it. The upper bound keeps routing off layers the power grid or the package needs. Both become set_routing_layers inside the flow. OpenROAD-flow-scripts reference
export MIN_CLK_ROUTING_LAYER = metal4

Keeps clock routing off the lowest layers, starting it at metal4.

Hint: It is usually higher than the signal minimum. Ask what is gained higher up.

Upper layers are thicker and so less resistive, which keeps clock delay and skew down. The variable is the lower bound of set_routing_layers -clock, and it is typically higher than the signal minimum. OpenROAD-flow-scripts reference
export ROUTING_LAYER_ADJUSTMENT = 0.3

Tells the global router each layer has 30% less capacity.

Hint: The number derates something the global router counts. Ask which way the trade runs.

Thirty percent of each layer's tracks are treated as unavailable. Some are already taken by pins, the power grid, and blockages. A larger adjustment spreads routing out and eases detailed routing, at the cost of detours and longer global routing; a smaller one risks congestion the detailed router cannot solve. The default is 0.5. OpenROAD-flow-scripts reference
export FASTROUTE_TCL = $(PLATFORM_DIR)/fastroute.tcl

Runs a script of routing settings before global routing starts.

Hint: It runs before the router, so ask what it can still change.

The script holds the per-platform routing setup: the layer ranges, the clock layers, and the layer adjustments. Platforms ship one because those choices depend on the metal stack. OpenROAD-flow-scripts reference
export ENABLE_RESISTANCE_AWARE = 1

Passes the resistance-aware flag to global routing.

Hint: It is passed straight through to the global router as a flag.

Resistance-aware routing weighs the resistance of the layer a net is assigned to, instead of treating layers as interchangeable capacity. The OpenROAD documentation marks the option as not ready for production. OpenROAD-flow-scripts reference
export DISABLE_VIA_GEN = 1

Stops the detailed router generating its own vias, using only the technology's.

Hint: It is a flag for the detailed router, and vias come in two kinds.

The router can either build via shapes from rules or use the fixed vias the technology defines. Restricting it to the fixed set is used when a technology's generated vias would not be manufacturable. OpenROAD-flow-scripts reference
export TNS_END_PERCENT = 100

Repairs all violating endpoints, not only the worst ones.

Hint: Ask what a lower number would buy, given that the worst path is always repaired.

The worst path is always repaired; this says how much of the failing tail is repaired after it, as a percentage of violating endpoints. The default is 100, and it is reduced (5 is common) to cut runtime, which leaves total negative slack worse. OpenROAD-flow-scripts reference
export SETUP_SLACK_MARGIN = 0.05

Keeps repairing setup until each path has 0.05 ns of slack in hand.

Hint: Repair normally stops at zero slack. Ask what this changes about stopping.

Repairing to a margin (overfixing) leaves headroom for what later stages add, since routing and extraction usually make timing worse. A negative value underfixes, stopping before slack reaches zero, which is used to save runtime. HOLD_SLACK_MARGIN is the same for hold. OpenROAD-flow-scripts reference
export HOLD_SLACK_MARGIN = 0.1

Repairs hold until each path has 0.1 ns of hold slack in hand.

Hint: Hold is fixed by adding delay. Ask what a margin costs here.

Hold margin costs buffers and area, because delay has to be added to the fast paths. It buys safety against the on-chip variation that a single corner does not show. A negative value underfixes. OpenROAD-flow-scripts reference
export CAP_MARGIN = 20 export SLEW_MARGIN = 20

Repairs capacitance and slew to limits 20% tighter than the real ones.

Hint: Both are design-rule limits, and the margins work the same way as the slack ones.

Before routing, parasitics are estimated from placement and are optimistic. Overfixing against tighter limits leaves room for the real wires. The two become the margin arguments of repair_design. OpenROAD-flow-scripts reference
export SKIP_GATE_CLONING = 1

Stops timing repair from duplicating a gate to split its load.

Hint: Cloning is one of the transforms timing repair can apply. Ask what it costs.

Cloning a gate lets each copy drive part of the fanout, which helps a heavily loaded driver, but it adds area and makes the netlist diverge from the synthesized one. Flows disable it when netlist stability or area matters more. Cloning is used by default. OpenROAD-flow-scripts reference
export SKIP_LAST_GASP = 1

Skips the final timing-repair attempt made after the main passes.

Hint: The name says when it runs, not what it does.

The last-gasp pass is a final push on whatever still fails after the normal transforms have run. It costs runtime for a small gain, so runs that care about turnaround skip it. It is used by default. OpenROAD-flow-scripts reference
export SKIP_INCREMENTAL_REPAIR = 1

Skips the repair that runs inside global routing.

Hint: Ask which stage's repair this is, given the parasitics that stage provides.

After global routing, parasitics are much closer to the truth, so the flow repairs timing again with better numbers. Skipping it saves runtime and leaves those violations for later stages, or unfixed. OpenROAD-flow-scripts reference
export RECOVER_POWER = 20

Slows the 20% of paths with the most slack, to save power.

Hint: The percentage refers to paths that are not in trouble.

Slack on a path means it is running faster than it has to, which costs leakage and area. Downsizing those cells trades the unneeded speed back for power. The value becomes repair_timing -recover_power. OpenROAD-flow-scripts reference
export MATCH_CELL_FOOTPRINT = 1

Allows sizing to swap only cells with the same layout boundary.

Hint: The restriction is physical, not electrical.

Same-footprint swaps drop into place without disturbing placement or routing, so they can be made late. It narrows the choice of cells, which limits how much timing can improve. OpenROAD-flow-scripts reference
export OPT_POST_GRT_WNS = 0

Turns off the worst-slack repair that normally runs after global routing.

Hint: Check the default. Ask what kind of repair is gentle enough to run after routing.

The pass is deliberately gentle: it swaps threshold voltage and reroutes wires rather than adding or moving cells, so it disturbs the placement and routing as little as possible. It is on by default. OpenROAD-flow-scripts reference
export FILL_CELLS = FILLCELL_X1 FILLCELL_X2 FILLCELL_X4

Names the cells used to fill the gaps between placed cells.

Hint: Ask what happens if the variable is left empty.

A filler carries the supply rails and the well layers across a gap, so the rows stay legal to manufacture. If the variable is unset or empty, the flow skips filler insertion altogether. Metal fill is the separate USE_FILL. OpenROAD-flow-scripts reference
export USE_FILL = 1

Turns on metal fill, which evens out each layer's density.

Hint: Compare it with FILL_CELLS: one fills rows, the other fills layers.

Dummy metal shapes are added where a layer is too empty. Manufacturing needs each layer's metal density inside a band, or polishing leaves an uneven surface. Metal fill adds unconnected shapes where a layer is too empty, following the rules in FILL_CONFIG. It is off by default because it is slow and enlarges the layout. OpenROAD-flow-scripts reference
export PWR_NETS_VOLTAGES = VDD 1.1 export GND_NETS_VOLTAGES = VSS 0.0

Gives the supply voltages that the drop analysis solves against.

Hint: Ask which analysis needs to know a voltage, rather than just a net name.

The analysis pushes current through the grid's resistance and reports how far the local voltage falls below these values. IR_DROP_LAYER says which layer the result is reported on. OpenROAD-flow-scripts reference
export IR_DROP_LAYER = metal1

Chooses the layer whose voltage drop is reported.

Hint: The drop is worst furthest from the source. Ask where that is in the stack.

The analysis solves the whole grid, but the number that matters is what the cells see, and they connect on the lowest layer. Reporting there shows the worst case. OpenROAD-flow-scripts reference
export GDS_ALLOW_EMPTY = sram.*

Allows macros matching that pattern to have no layout of their own.

Hint: The value is a pattern, and the stage is the one that merges layouts.

Merging normally fails if a macro has no layout, which catches a missing file. The pattern makes that deliberate, for a macro whose layout comes later or is supplied by the foundry. OpenROAD-flow-scripts reference
export SEAL_GDS = sky130_seal_ring.gds

Adds a seal ring layout around the design in the final merge.

Hint: A ring placed around the outside of the die, once the design is done.

A seal ring is a metal barrier around the die edge that protects the circuit from the cracks and moisture that dicing can introduce. It is foundry-supplied and merged in at the end. OpenROAD-flow-scripts reference
export CDL_FILE = $(PLATFORM_DIR)/cdl/sc.cdl

Gives the cells' own subcircuits for the netlist that is written.

Hint: Ask what the flow's own netlist output is missing for this check.

Without them the netlist would name cells it never defines. The flow writes a netlist for layout-versus-schematic checking, and that netlist has to include the standard cells' transistor-level contents. This file supplies them, as the -masters argument of write_cdl. OpenROAD-flow-scripts reference
export KLAYOUT_TECH_FILE = $(PLATFORM_DIR)/KLayout/tech.lyt

Maps the flow's layer names onto the layout format's numbers.

Hint: Two formats describe the same layers with different names and numbers.

LEF (Library Exchange Format) and DEF (Design Exchange Format) name layers; a layout file identifies them by number and datatype. The mapping lets the flow write the final layout and lets KLayout read it back with the right layers. OpenROAD-flow-scripts reference
export RCX_RULES = $(PLATFORM_DIR)/rcx_patterns.rules

Gives the model that extraction turns routed geometry into parasitics with.

Hint: Extraction has to turn geometry into numbers from somewhere.

The rules file is built once per process from field-solver runs over test patterns. Extraction measures each wire's geometry and neighbours and looks the values up in it, which is what sign-off timing uses. OpenROAD-flow-scripts reference
export CORNER = BC

Picks which process, voltage, and temperature library set is used.

Hint: It selects among libraries that the platform already ships.

A platform that ships several characterizations, such as best case, typical, and worst case, selects one this way. It is available on the ASAP7 and GF180 platforms; CORNERS is the separate variable for analyzing several at once. OpenROAD-flow-scripts reference
export OPENROAD_HIERARCHICAL = 1

Runs the physical stages hierarchically rather than on a flat design.

Hint: Compare it with SYNTH_HIERARCHICAL, which concerns one stage only.

The database keeps the module hierarchy through placement, routing, and the rest, instead of a flat netlist. The documentation says it will become the default and the option will then be retired. Hardening blocks separately is BLOCKS. OpenROAD-flow-scripts reference
export SKIP_REPORT_METRICS = 1

Stops the per-stage metric reporting, to make a build faster.

Hint: Ask what is lost, and what is gained, on a long run.

After each stage the flow reports area, timing, and more into JSON (JavaScript Object Notation) metrics files. That costs a timing run each time. Skipping it speeds up exploration and gives up the record of how the run progressed. OpenROAD-flow-scripts reference
export LEC_CHECK = 1

Checks the netlist is logically unchanged by the tool's edits.

Hint: Ask which two versions of the netlist there are to compare.

The two versions compared are the netlist before and after the tool's changes. Resizing, buffering, and clock tree synthesis rewrite it, and a formal equivalence check proves the rewrite changed no function. The documentation says a failure is an OpenROAD bug worth reporting. REMOVE_CELLS_FOR_LEC drops cells the checker cannot handle. OpenROAD-flow-scripts reference
export GPL_RANDOM_SEED = 42

Fixes the placer's random seed, so a run can be repeated or varied.

Hint: Ask what changes between two runs that are otherwise identical.

Setting the seed to different values gives different placements of the same design, which is how the effect of placement noise on a result is measured. The documentation calls this a perturbation study. OpenROAD-flow-scripts reference
export ASAP7_USE_VT = RVT LVT

Allows the flow to use both the regular and low threshold-voltage cells.

Hint: The letters name transistor flavours, and each one trades the same two things.

A lower threshold voltage makes a cell faster and leakier. Offering several flavours lets optimization spend leakage only where speed is needed. It applies to the ASAP7 platform, whose library ships regular, low, and super-low flavours. OpenROAD-flow-scripts reference
export CORNERS = slow fast

Analyses timing at both named corners, not just one.

Hint: Ask how the flow then knows which library belongs to which name.

Libraries are loaded per corner: for each name the flow reads the matching per-corner library variable, such as SLOW_LIB_FILES. Several corners at once is how a design is signed off, since setup is usually worst slow and hold worst fast. OpenROAD-flow-scripts reference
export TECH_LEF = $(PLATFORM_DIR)/lef/NangateOpenCellLibrary.tech.lef export SC_LEF = $(PLATFORM_DIR)/lef/NangateOpenCellLibrary_macro.lef

Gives the technology layers in one file and the cell shapes in the other.

Hint: Two files in the same format, describing two different things.

The technology file carries the metal layers, vias, sites, and spacing rules; the cell file carries each standard cell's outline, pins, and blockages. Both are LEF (Library Exchange Format), and both come from the platform. OpenROAD-flow-scripts reference
export CLKGATE_MAP_FILE = $(PLATFORM_DIR)/cells_clkgate.v

Maps inferred clock gating onto the platform's clock-gating cells.

Hint: The same mapping mechanism as the adder file, for a different kind of cell.

A clock gate built from ordinary gates can glitch the clock. The platform's integrated cell latches the enable so it cannot. The file tells synthesis which cell to use; LATCH_MAP_FILE does the same for latches. OpenROAD-flow-scripts reference
export LATCH_MAP_FILE = $(PLATFORM_DIR)/cells_latch.v

Maps inferred latches onto the platform's own latch cells.

Hint: Ask what synthesis does with an inferred latch when no such cell is named.

A latch inferred from incomplete code has to become some real cell. Without a mapping file, synthesis builds one from gates, which is larger and less predictable than the library's own latch. OpenROAD-flow-scripts reference
export SYNTH_HDL_FRONTEND = slang

Reads the sources with the slang front end, not the default one.

Hint: It changes how the sources are read, before any logic is built.

The sources are parsed by slang before any logic is built. The default reader handles a subset of SystemVerilog. The slang front end supports considerably more of the language, which is what designs written in modern SystemVerilog need. Leaving the variable empty keeps the default. OpenROAD-flow-scripts reference
export MACRO_WRAPPERS = ./designs/src/bp/wrappers.tcl

Swaps each macro for a wrapped version of it before placement.

Hint: Ask why a macro would be replaced by another version of itself.

A wrapper adds what the macro itself does not carry, such as pin access structures or a keepout, so the flow can treat a bare macro as a well-behaved block. OpenROAD-flow-scripts reference
export RTLMP_MAX_MACRO = 12

Allows at most 12 macros in one cluster of the macro placer.

Hint: The macro placer groups things first. Ask what the number limits.

The placer clusters the netlist into a hierarchy of blocks and shapes them before placing macros. The cluster limits, RTLMP_MAX_MACRO, RTLMP_MIN_MACRO, and their instance counterparts, control how coarse that hierarchy is. Unset, the tool derives values from the design. OpenROAD-flow-scripts reference
export CELL_PAD_IN_SITES_DETAIL_PLACEMENT = 2

Keeps two sites free beside each cell during legalization.

Hint: Compare it with the global placement padding: same idea, later stage, usually smaller.

Legalization is the stage that uses it. Global placement is padded more to spread cells early, while legalization is padded less because the space still has to exist in real rows. The padding is removed before filler insertion, so it costs no area in the end. OpenROAD-flow-scripts reference
export PLACE_PINS_ARGS = -min_distance 4 -min_distance_in_tracks

Passes those extra arguments straight to the pin placer.

Hint: The name says where the text goes, not what it means.

A passthrough variable exists so a design can reach an option the flow does not otherwise expose, here the minimum spacing between pins in tracks. GLOBAL_PLACEMENT_ARGS and CTS_ARGS do the same for their own stages. OpenROAD-flow-scripts reference
export GLOBAL_PLACEMENT_ARGS = -routability_driven

Adds arguments to the global placement call the flow already makes.

Hint: Ask what this reaches that the flow's own density variables cannot.

The flow builds its own global_placement call from the density and timing variables; this appends to it. It is how a design turns on an option such as routability-driven placement without editing the flow. OpenROAD-flow-scripts reference
export CTS_ARGS = -sink_clustering_size 20

Overrides the arguments the flow passes to clock tree synthesis.

Hint: Compare it with the CTS (Clock Tree Synthesis) variables that have their own names.

The named variables, such as CTS_CLUSTER_SIZE, build the usual clock tree synthesis call. This variable replaces those arguments outright, which is the way to reach an option that has no variable of its own. OpenROAD-flow-scripts reference