Games / Command flash cards / OpenROAD flow commands / Reading and writing a design

Reading and writing a design

The cards come in more than one shape: a command to explain, and steps to put in order. A missed card returns later in the round and starts the schedule over. A card answered correctly moves up the schedule and next appears after 1, 3, 7, then 21 days. Keys 1 to 4 choose an option, h shows a hint, and Enter moves on. A hint keeps the card where it is on the schedule. An ordering card is answered by clicking its items in order, and one wrong click ends it. Time values are in nanoseconds. Progress is stored in this browser.

SourceThese cards follow OpenROAD's own commands, checked against the signatures printed by the tool (OpenROAD 26Q3) and the documentation of the module that implements each one. Each answer links to that module's documentation. Commands differ between versions, and commercial tools use different names entirely. Reference: OpenROAD module documentation (OpenROAD on GitHub).
All 11 cards in this section, with answers
  • read_lef nangate45.lef
    Reads the technology and the shapes of the cells.

    Hint: LEF (Library Exchange Format) is the physical library. Ask whether it carries geometry or timing.

    LEF (Library Exchange Format) carries the physical data: the layers, vias, sites, and cell outlines. In detail: the metal layers and their rules, the via definitions, the placement site, and each cell's outline, pins, and blockages. A run reads the technology file first, then the cell file. OpenROAD reference

  • read_liberty NangateOpenCellLibrary_typical.lib
    Reads the cells' timing and power data: delays, setup and hold, and leakage.

    Hint: Liberty is the timing library. Ask what a timer needs that geometry cannot give.

    One Liberty file describes one corner: delays and slews as tables against load and input slew, the timing checks, and power data. Loading the design's database does not bring it, so the library is read separately in every session that reports timing. OpenROAD reference

  • read_verilog gcd.v link_design gcd
    Reads the netlist file, then builds the design gcd from it.

    Hint: Reading a netlist file and building a design from it are two different steps.

    Linking binds each instance to a cell from the libraries. read_verilog only parses the file; link_design picks the named module as the top, resolves every instance against the cells read from the library files, and builds the design in the database. -hier keeps the hierarchy instead of flattening it. OpenROAD reference

  • read_def 2_floorplan.def
    Reads a layout: die area, rows, placement, and routing.

    Hint: DEF (Design Exchange Format) is the layout format. Ask what it holds that the library format does not.

    DEF (Design Exchange Format) is design-specific layout, so it carries placement and routing as well as the boundary: where the boundary is, where each instance sits, and how the nets are wired. The library data it refers to comes from LEF (Library Exchange Format). -floorplan_initialize and -incremental control how it merges with what is already loaded. OpenROAD reference

  • write_db 3_place.odb
    Writes the whole design state, the tool's own database, to one file.

    Hint: Ask what one flow stage must hand to the next, beyond a layout file.

    The OpenDB database holds the technology, the netlist, and the layout together, so a stage can save its result exactly and the next stage can carry on. Flow scripts write one database per stage. OpenROAD reference

  • read_db 6_final.odb
    Restores a saved design, with its technology and layout, in one step.

    Hint: It restores the design, but a timing report also needs something the database has never held.

    The database carries the design, not the Liberty libraries. A session that reads a database and then reports timing must still read_liberty, or the timer reports that no libraries were found. OpenROAD reference

  • write_verilog 6_final.v
    Writes the netlist as it now stands, with the tool's changes.

    Hint: Optimization has added, removed, and resized cells since synthesis.

    Every cell the tool added, removed, or resized is in the file. Buffering, sizing, clock tree synthesis, and filler insertion all change the netlist. The written file is what the layout actually contains, which is what equivalence checking and later flows need. OpenROAD reference

  • write_abstract_lef gcd.lef
    Writes the block as an outline with pins, hiding its internals.

    Hint: An abstract is what a larger design needs in order to use this block.

    The internals are left out. The top level needs the block's size, its pin positions, and where it blocks routing. An abstract gives exactly that, so the top level stays small. Its timing counterpart is write_timing_model. OpenROAD reference

  • write_cdl -masters cells.cdl gcd.cdl
    Writes a netlist for LVS (Layout Versus Schematic) comparison.

    Hint: Physical verification compares the layout against a netlist in this format.

    The cell subcircuits are included through -masters. CDL (Circuit Description Language) is the netlist format physical verification compares the extracted layout against. -masters gives the files holding the standard cells' own subcircuits, so the output is complete. OpenROAD reference

  • write_def 5_route.def
    Writes the current layout out for another tool to read.

    Hint: Ask what another tool needs in order to see this layout, without OpenROAD.

    DEF (Design Exchange Format) is the portable form of the layout: the boundary, the rows, where every instance sits, and the routing. The technology it refers to stays in the library files. Between OpenROAD stages the database is used instead, since it carries more. OpenROAD reference

  • Put these reads in the order a session must perform them.
    1. read_lef platform.tech.lef
    2. read_lef platform.macro.lef
    3. read_verilog gcd.v
    4. link_design gcd
    5. read_spef gcd.spef

    Hint: One kind of file describes the layers that another kind of file uses.

    The technology file defines the layers and vias that the cell abstracts refer to, so it is read first. The netlist names cells from those abstracts, linking turns it into a design, and parasitics can only be annotated onto nets that exist. OpenROAD reference