Games / Command flash cards / OpenROAD flow commands / Clock tree synthesis

Clock tree synthesis

Each card shows a command to explain. A missed card returns later in the round and starts the schedule over. A card answered correctly moves up the schedule and next appears after 1, 3, 7, then 21 days. Keys 1 to 4 choose an option, h shows a hint, and Enter moves on. A hint keeps the card where it is on the schedule. An ordering card is answered by clicking its items in order, and one wrong click ends it. Time values are in nanoseconds. Progress is stored in this browser.

SourceThese cards follow OpenROAD's own commands, checked against the signatures printed by the tool (OpenROAD 26Q3) and the documentation of the module that implements each one. Each answer links to that module's documentation. Commands differ between versions, and commercial tools use different names entirely. Reference: OpenROAD module documentation (OpenROAD on GitHub).
All 7 cards in this section, with answers
  • clock_tree_synthesis -buf_list {CLKBUF_X1 CLKBUF_X2 CLKBUF_X4} -root_buf CLKBUF_X4 -sink_clustering_enable
    Builds the clock tree from those buffers, grouping nearby sinks first.

    Hint: The buffer list is the palette. Ask what gets built out of it.

    The root buffer drives the top of the tree and the list gives the cells the tree is built from. -sink_clustering_enable groups nearby sinks into clusters, each driven by one buffer, which become the leaves of the tree above. It runs after placement. OpenROAD reference

  • clock_tree_synthesis -buf_list {CLKBUF_X2} -obstruction_aware
    Keeps the clock buffers off macros and blockages.

    Hint: Ask where a buffer would otherwise land, and what the legalizer would then do with it.

    The buffers are kept clear as the tree is built. Without it, buffers can be placed over a macro and the legalizer then pushes them somewhere else, which changes the latency and skew the tree was built for. Keeping them clear from the start gives a tree that survives legalization. OpenROAD reference

  • clock_tree_synthesis -buf_list {CLKBUF_X2} -apply_ndr half
    Gives double spacing to the clock nets in the tree's top half.

    Hint: A non-default rule changes how the wire is drawn, and half says how much of the tree gets it.

    The levels counted are the top half of the tree. Extra spacing keeps aggressors away from clock wires, where crosstalk turns straight into skew and jitter. The strategies are none, root_only, half, and full, counted from the root; leaf nets are left out. The default is half. OpenROAD reference

  • configure_cts_characterization -max_cap 0.6 -max_slew 0.2
    Bounds the buffered wire segments the tool characterizes.

    Hint: Characterization happens before the tree is built. Ask what it produces.

    The limits bound what the tool then uses. It first builds a table of buffered wire segments and their delays, then assembles the tree from it. These limits bound the table, so they decide how long a segment may get before another buffer is needed. OpenROAD reference

  • report_cts
    Reports the tree that was built: how many sinks, buffers, and levels.

    Hint: It describes the tree that exists, not the timing of it.

    It answers whether the tree looks sensible: the sink count, the buffers inserted, and how deep the tree is. The timing view of the same tree comes from report_clock_skew and report_clock_latency. OpenROAD reference

  • repair_clock_nets -max_wire_length 100
    Splits the long clock nets with buffers before the tree is built.

    Hint: It runs before the tree exists. Ask what a clock net looks like at that point.

    Before clock tree synthesis a clock may be one net stretching across the block, whose delay would distort everything built on it. Buffering it into shorter segments first gives the tree a sane starting point. OpenROAD reference

  • repair_clock_inverters
    Replaces a clock inverter that has several fanouts with one inverter each.

    Hint: One inverter with many fanouts is a fork in the clock network.

    An inverter feeding several branches splits the clock network into pieces that clock tree synthesis then treats separately. Giving each fanout its own inverter keeps the tree whole. It runs before clock_tree_synthesis. OpenROAD reference