All sections

Hint: LEF (Library Exchange Format) is the physical library. Ask whether it carries geometry or timing.

LEF (Library Exchange Format) carries the physical data: the layers, vias, sites, and cell outlines. In detail: the metal layers and their rules, the via definitions, the placement site, and each cell's outline, pins, and blockages. A run reads the technology file first, then the cell file. OpenROAD reference

Hint: Liberty is the timing library. Ask what a timer needs that geometry cannot give.

One Liberty file describes one corner: delays and slews as tables against load and input slew, the timing checks, and power data. Loading the design's database does not bring it, so the library is read separately in every session that reports timing. OpenROAD reference

Hint: Reading a netlist file and building a design from it are two different steps.

Linking binds each instance to a cell from the libraries. read_verilog only parses the file; link_design picks the named module as the top, resolves every instance against the cells read from the library files, and builds the design in the database. -hier keeps the hierarchy instead of flattening it. OpenROAD reference

Hint: DEF (Design Exchange Format) is the layout format. Ask what it holds that the library format does not.

DEF (Design Exchange Format) is design-specific layout, so it carries placement and routing as well as the boundary: where the boundary is, where each instance sits, and how the nets are wired. The library data it refers to comes from LEF (Library Exchange Format). -floorplan_initialize and -incremental control how it merges with what is already loaded. OpenROAD reference

Hint: Ask what one flow stage must hand to the next, beyond a layout file.

The OpenDB database holds the technology, the netlist, and the layout together, so a stage can save its result exactly and the next stage can carry on. Flow scripts write one database per stage. OpenROAD reference

Hint: It restores the design, but a timing report also needs something the database has never held.

The database carries the design, not the Liberty libraries. A session that reads a database and then reports timing must still read_liberty, or the timer reports that no libraries were found. OpenROAD reference

Hint: Optimization has added, removed, and resized cells since synthesis.

Every cell the tool added, removed, or resized is in the file. Buffering, sizing, clock tree synthesis, and filler insertion all change the netlist. The written file is what the layout actually contains, which is what equivalence checking and later flows need. OpenROAD reference

Hint: An abstract is what a larger design needs in order to use this block.

The internals are left out. The top level needs the block's size, its pin positions, and where it blocks routing. An abstract gives exactly that, so the top level stays small. Its timing counterpart is write_timing_model. OpenROAD reference

Hint: Physical verification compares the layout against a netlist in this format.

The cell subcircuits are included through -masters. CDL (Circuit Description Language) is the netlist format physical verification compares the extracted layout against. -masters gives the files holding the standard cells' own subcircuits, so the output is complete. OpenROAD reference

Hint: Utilization relates cell area to core area. Ask what the command can derive from it.

Rows are made as well. The core area is the design's cell area divided by the utilization; the aspect ratio turns that into width and height, and -core_space adds the margin between core and die. The site sets the row height. Rows for the site are created, and any existing tracks are removed. OpenROAD reference

Hint: Two rectangles are given. Ask which one the cells go in and what the difference is for.

The core is filled with rows. Giving the two areas explicitly is the alternative to giving a utilization; setting both leads to unexpected results. The margin between die and core holds the power ring and the boundary pins. Rows are built inside the core from the given site. OpenROAD reference

Hint: initialize_floorplan removes tracks. Ask what has to put them back.

Tracks are the legal wire centre lines that the router and the pin placer use. initialize_floorplan removes existing tracks, so they are made again per layer, usually from the technology's own values. OpenROAD reference

Hint: Horizontal and vertical describe the direction of the tracks a pin shape sits on.

Each pin's shape goes on a track of the given layers: pins on horizontal tracks use -hor_layers, pins on vertical tracks on -ver_layers. The placer chooses positions that shorten the nets to the cells inside, and it creates a metal shape that meets the minimum-area rule. OpenROAD reference

Hint: Compare it with place_pins, which does every pin at once.

The location and size are fixed, not a suggestion. It is used for pins that must sit at an agreed place, for example to meet a package or a neighbouring block. write_pin_placement writes a file of these commands so a placement can be reproduced exactly. OpenROAD reference

Hint: It says nothing about when pins move. Ask what it changes for a later command.

The constraint applies to the following place_pins call. A region is an edge and an interval, so left:15-60 would use only part of that edge. -group keeps a list of pins together and -mirrored_pins places pairs symmetrically. OpenROAD reference

Hint: The name says RTL (Register Transfer Level): the placer reads the netlist hierarchy.

-halo_width keeps a 5 micron band clear around each macro. The Hier-RTLMP algorithm clusters the netlist into a hierarchy of soft blocks, shapes them, and then places the macros. The halo is the keepout kept around each macro so standard cells and routing are not pinched against it. OpenROAD reference

Hint: This is the manual counterpart to the automatic macro placer.

The location is the macro's lower-left corner in microns and the orientation is a LEF (Library Exchange Format) orientation such as R0 or MX. -exact and -allow_overlap relax the checks the command otherwise applies. OpenROAD reference

Hint: A halo is empty space, not a physical object.

Cells packed against a macro edge leave no room for the macro's pins to be reached, and for the repair steps that follow. The halo reserves that room. set_macro_extension does the same job for the macro placer's own spacing between macros. OpenROAD reference

Hint: Well taps tie the wells to the supplies; ask what pattern they must follow.

-distance is the tap pitch and -endcap_master the cell that ends a row. Foundry rules limit how far any transistor may be from a well tap, so taps are placed on a checkerboard at that pitch. Endcaps terminate the rows so the wells and implants end legally. Both go in before placement. OpenROAD reference

Hint: A row that runs under a macro is not usable. Ask what to do about it.

Rows must not run through a macro, so they are cut around it, plus the halo given here, plus a halo so cells do not crowd the macro edge. -row_min_width and -row_min_height drop the fragments left behind that are too small to use. OpenROAD reference

Hint: The -soft flag is the interesting part: ask what a soft rule allows.

-soft is the difference: a hard blockage keeps every instance out, while a soft blockage steers the global placer away while allowing cells if the placement needs them, and -max_density instead caps how full the region may get. -inst attaches the blockage to one instance. OpenROAD reference

Hint: Standard cells have supply pins but no supply nets in the netlist. The patterns are regular expressions.

-power marks the net as a supply. Synthesis leaves supply pins unconnected, so they are connected by pattern instead of one by one. -power and -ground say which kind of supply the net is, which the grid generator and the analysis need. OpenROAD reference

Hint: Compare it with add_global_connection, which comes first.

The rules come from add_global_connection. They are declared first and applied afterwards, so a script can add several and connect once. Commands that build the grid also apply the rules, and -verbose reports how many pins each rule connected. OpenROAD reference

Hint: Nothing is built yet. Ask what the command starts.

It applies to the voltage domain named, here CORE. A grid is described in pieces: the definition, then straps, rings, and connections, and finally pdngen builds it. -pins names the layers where block pins for the supplies are made. With -macro the definition applies to macros instead of the core. OpenROAD reference

Hint: The -followpins flag ties these stripes to something already in the floorplan.

These are the standard cells' own power and ground rails. With -followpins the pitch and the spacing come from the rows, since one rail runs along each row's supply pins. Without it, straps are regular and need -pitch, -offset, and -width. OpenROAD reference

Hint: Two numbers describe the pattern: how often, and from where.

Each strap is a power and ground pair. The pitch is the distance between one pair and the next, and the offset is measured from the core's lower-left corner. A wider pitch leaves more room for signal routing and carries less current. -spacing sets the gap inside a pair, half the pitch by default. OpenROAD reference

Hint: Straps on different layers cross but do not touch. Ask what is missing.

Each overlapping pair of same-net straps becomes a via stack when pdngen runs. Via rules from the technology are used unless -fixed_vias names ready-made vias. Without a connect rule the two layers simply cross. OpenROAD reference

Hint: Everything so far was description. Ask what turns it into metal.

-report_only prints the specification, -check_only checks it, and -reset clears it. -ripup removes a grid built earlier so it can be rebuilt, and the final trim step removes metal stubs unless -skip_trim is given. OpenROAD reference

Hint: It runs after detailed routing. Ask what routing can do to a via that was already built.

It runs after detailed routing, because signal routing around a via stack can leave it violating spacing rules. Removing the offending vias keeps the design rule clean at the cost of a little grid connectivity. OpenROAD reference

Hint: The grid has resistance and the cells draw current. Ask what that costs.

-voltage_file writes the voltage at each instance. Current drawn through the grid's resistance lowers the voltage the cells actually see, which slows them. -enable_em adds the current per segment for electromigration, and -error_file records nodes that could not be solved. OpenROAD reference

Hint: It comes before the analysis. Ask what would make the analysis meaningless.

A disconnected piece of grid has no path to a supply source, so the analysis cannot solve for its voltage. The check finds that before the analysis runs. OpenROAD reference

Hint: Global placement is analytical: cells get positions, not legal ones.

Cells may still overlap; legalization comes later. The placer balances wirelength against a density penalty on a grid of bins, so cells end up near where they belong but not on legal sites. A lower target density spreads cells further apart, which eases routing and costs wirelength. OpenROAD reference

Hint: Both flags make the placer care about something beyond wirelength, and both cost runtime.

Timing-driven mode runs a virtual repair_design to find slacks and weights low-slack nets so they are shortened; it needs set_wire_rc for the estimates. Routability-driven mode estimates congestion and inflates the cells in congested tiles to spread them. OpenROAD reference

Hint: Global placement leaves cells overlapping and off-site. Ask what fixes that, and what the limit restricts.

The displacement limit is in sites and rows. Legalization removes overlaps and snaps cells to legal sites while keeping them near where global placement put them. The displacement limit caps how far a cell may be moved to find a legal spot. OpenROAD reference

Hint: It only looks. Ask what would make a placement illegal.

Overlapping, off-site, and out-of-row cells are all reported. It is the gate between placement and the stages that assume legality. A script runs it after legalization and stops if anything is reported; -report_file_name writes the list to a file. OpenROAD reference

Hint: The padding is measured in sites, and it exists for the steps that come after placement.

The padding is in sites, applied on both sides of each cell. The reserved sites give the router room to reach pins and leave space for buffers added later by repair. Padding applies to legalization, so it is set before detailed_placement. -masters and -instances narrow it to certain cells. OpenROAD reference

Hint: The rails run along the rows, and placement leaves gaps in them.

The rails then run unbroken along each row. A filler cell carries the power and ground rails and the well and implant layers across a gap, which keeps the rows legal for manufacturing. The argument is a pattern of filler master names, widest first. remove_fillers clears them again so a later stage can edit the rows. OpenROAD reference

Hint: It runs after legalization, and it keeps the placement legal.

The pass makes local improvements: swapping neighbouring cells and moving a cell within the given distance, keeping the result legal. It is cheap compared with placing again. OpenROAD reference

Hint: A cell can be flipped without changing where it sits.

Mirroring changes which side a cell's pins face without moving the cell or breaking legality, so it shortens wires at no cost in area. It is run after legalization. OpenROAD reference

Hint: The gain is in the clock network, not in the data paths.

One multi-bit register has a single clock input for several bits, so the clock tree drives fewer sinks and burns less power. The weights trade the clock saving against the extra wirelength pulling the bits together. OpenROAD reference

Hint: Rows are the resource; ask what happens when some are full and others are empty.

Some rows end up packed while their neighbours are empty, and a full row leaves the legalizer and the repair steps nowhere to put anything, and it concentrates routing demand. Evening out row usage keeps later steps possible. OpenROAD reference

Hint: The buffer list is the palette. Ask what gets built out of it.

The root buffer drives the top of the tree and the list gives the cells the tree is built from. -sink_clustering_enable groups nearby sinks into clusters, each driven by one buffer, which become the leaves of the tree above. It runs after placement. OpenROAD reference

Hint: Ask where a buffer would otherwise land, and what the legalizer would then do with it.

The buffers are kept clear as the tree is built. Without it, buffers can be placed over a macro and the legalizer then pushes them somewhere else, which changes the latency and skew the tree was built for. Keeping them clear from the start gives a tree that survives legalization. OpenROAD reference

Hint: A non-default rule changes how the wire is drawn, and half says how much of the tree gets it.

The levels counted are the top half of the tree. Extra spacing keeps aggressors away from clock wires, where crosstalk turns straight into skew and jitter. The strategies are none, root_only, half, and full, counted from the root; leaf nets are left out. The default is half. OpenROAD reference

Hint: Characterization happens before the tree is built. Ask what it produces.

The limits bound what the tool then uses. It first builds a table of buffered wire segments and their delays, then assembles the tree from it. These limits bound the table, so they decide how long a segment may get before another buffer is needed. OpenROAD reference

Hint: It describes the tree that exists, not the timing of it.

It answers whether the tree looks sensible: the sink count, the buffers inserted, and how deep the tree is. The timing view of the same tree comes from report_clock_skew and report_clock_latency. OpenROAD reference

Hint: It runs before the tree exists. Ask what a clock net looks like at that point.

Before clock tree synthesis a clock may be one net stretching across the block, whose delay would distort everything built on it. Buffering it into shorter segments first gives the tree a sane starting point. OpenROAD reference

Hint: One inverter with many fanouts is a fork in the clock network.

An inverter feeding several branches splits the clock network into pieces that clock tree synthesis then treats separately. Giving each fanout its own inverter keeps the tree whole. It runs before clock_tree_synthesis. OpenROAD reference

Hint: It is about design rules, not about slack.

The violations are slew, capacitance, fanout, and long wires: too slow a transition, too much load, too many loads, or too long a wire. Run estimate_parasitics -placement first, so the repair sees wire load. Timing repair is a separate command. OpenROAD reference

Hint: Ask why you would repair to a stricter limit than the real one.

Before routing, parasitics are estimated from placement and are optimistic; the real wires are worse. Repairing against a tighter limit buys margin so the design still passes once it is routed. OpenROAD reference

Hint: A long wire has resistance as well as capacitance. Ask what buffers do to its delay.

A wire's delay grows with the square of its length, so splitting it with buffers turns one long quadratic segment into several short ones. The default limit is the length that minimizes wire delay for the values given to set_wire_rc. OpenROAD reference

Hint: Ask what the margin is for, given that zero slack already passes.

Repair works by sizing gates, inserting buffers, cloning gates, and swapping pins. The margin leaves headroom for what later steps add, since routing and extraction usually make timing a little worse. OpenROAD reference

Hint: A hold violation means data arrives too early. Ask what fixes that.

Delay is added with buffers on the fast paths. Setup is repaired before hold, so hold repair does not undo it, and hold repair refuses to insert a buffer that would break setup unless -allow_setup_violations is given. Run it after clock tree synthesis, with propagated clocks. OpenROAD reference

Hint: A path with plenty of slack is paying for speed it does not need.

Slack is money left on the table: a smaller cell is slower but leaks less and presents less load. Recovering power gives it back on the paths that can afford it, without touching the critical ones. OpenROAD reference

Hint: It names library cells, not instances of them.

Sizing and buffering will not pick them. Clock buffers are excluded from data-path use, and cells known to behave badly are excluded outright. report_dont_use lists the excluded cells and reset_dont_use clears the list. Protecting a specific instance is set_dont_touch instead. OpenROAD reference

Hint: Compare it with set_dont_use: one names a library cell, the other an object in the design.

It applies to instances and nets in the design, for logic that must survive exactly as it is, such as a synchronizer or a cell a later step depends on. It concerns optimization, not placement or routing. OpenROAD reference

Hint: Ask what the block knows about what lies outside it.

A buffer at the boundary isolates the inside of the block from whatever drives it, so one weak external driver cannot slow a whole cone of logic. -outputs does the same for outputs, where the buffer takes the external load. OpenROAD reference

Hint: It is usually the first thing a placement-aware repair flow does.

Repair and clock tree synthesis insert their own. Synthesis buffers a netlist without knowing where anything will be placed, so its buffers are guesses. Removing them lets repair rebuild with real distances. Instances marked set_dont_touch are kept. OpenROAD reference

Hint: A tie cell holds a net at a constant. Ask why its loads should not be shared.

A shared tie cell would drive a long, high-fanout net held at a constant, which is fragile and wastes area. A copy beside each load keeps the net tiny. The separation keeps the copy off its load's own pin. OpenROAD reference

Hint: Ask which logic can be removed without changing what the block does.

Logic that drives nothing costs area, leakage, and routing while affecting nothing. It appears after other transformations, so the pass is run late rather than trusted to synthesis alone. OpenROAD reference

Hint: Two ranges are given. Ask why the clock would get a different one.

Upper layers are thicker, so they are less resistive; putting clocks there keeps their delay and skew low. The signal range usually excludes the top layers, which the power grid uses. OpenROAD reference

Hint: The router counts tracks. Ask what else is already using them.

Half the metal4 tracks are treated as unavailable. The power grid, pins, and macro blockages already consume tracks the router would otherwise count. Derating spreads routing out and keeps the detailed router from meeting congestion it cannot resolve. * sets every layer, a range sets several, and a negative value adds capacity. OpenROAD reference

Hint: Global routing works on regions, and it negotiates when too many nets want the same one.

Each net gets a path through a grid of regions with limited capacity, and the congestion report is written to the named file. Where demand exceeds capacity, the router reroutes nets over the given number of iterations. The report can be opened in the graphical viewer. Unresolved congestion stops the flow unless -allow_congestion is set. OpenROAD reference

Hint: Ask what the detailed router is given to work from.

The guides are written to the named file. A guide is the corridor the detailed router keeps a net inside, which is what makes detailed routing tractable. write_guides writes the same thing afterwards, and read_guides reads one back. OpenROAD reference

Hint: One extreme is the shortest total wire; the other is the shortest path to each sink.

The value applies when each net's route tree is built. At 0 the tree is a minimum-wirelength Steiner tree, which can take a long detour to a far sink. At 1 every sink gets its most direct path, at the cost of wire. Clock and other timing-critical nets get a higher value, with -clock_nets or per net. OpenROAD reference

Hint: Before a net can be routed, the router needs to know how a pin can be entered.

A pin is a shape on a low layer that may be reachable only from certain directions and through certain vias. Detailed routing does this itself; the command exists to run and debug the step alone. OpenROAD reference

Hint: It is iterative: each pass tries to remove what the last one could not.

The violations go to the named file. The detailed router turns each guide into metal and vias that obey the technology's rules, then repeats over the remaining violations. The report lists what is left, which is the number a tapeout must drive to zero. OpenROAD reference

Hint: Default rules give minimum width and spacing. Ask what a non-default rule changes.

A wider wire has less resistance and a wider space has less coupling, at the cost of routing room. Clocks and other sensitive nets get such a rule. Defining it changes nothing until assign_ndr applies it. OpenROAD reference

Hint: The rule already exists. Ask what is still missing.

Rules are defined once and then applied to nets, either -all_clocks or a named net. The router obeys the rule from then on. OpenROAD reference

Hint: The damage happens during manufacturing, not in the finished chip.

-report_violating_nets lists the nets. While a layer is being etched, a long piece of metal connected to a gate accumulates charge and can break the thin oxide. The ratio of metal area to gate area must stay under the foundry's limit. The check needs routing, so it runs after detailed_route. OpenROAD reference

Hint: A diode gives the collected charge somewhere to go.

A diode placed on the net bleeds the charge to the substrate, so the gate survives the etch. Repair reroutes and rechecks, hence the iterations. -jumper_only instead breaks the long metal by hopping to another layer. OpenROAD reference

Hint: Before anything is routed, the tool still needs a number for a wire.

The values are taken per unit length from metal3. Every estimate before routing needs a resistance and capacitance per micron; taking them from a middle layer is the usual choice. The values feed timing-driven placement and repair_design. -clock and -signal set them separately, and -resistance and -capacitance give values directly. OpenROAD reference

Hint: Compare it with set_wire_rc: this one names the layer itself, not an estimate.

Technology files sometimes lack per-layer values, or carry values that do not match the corner in use. Setting them per layer fixes what estimates and extraction start from. report_layer_rc prints what is in force. OpenROAD reference

Hint: There is no routing yet, so the wire has to be guessed from somewhere.

The tool builds a tree over the pin locations and applies the per-length values from set_wire_rc. It is rough but available early, which is what repair_design and timing-driven placement need. OpenROAD reference

Hint: Something better than pin positions now exists, but the real wires do not.

That is closer to the real wires than a placement estimate. The guides say which regions and layers a net will use, so the length and layer mix are much closer to the truth than a Steiner tree over pins. This is what timing between global and detailed routing is based on. OpenROAD reference

Hint: The wires exist now. Ask what the rules file is for.

The model file holds the values for the process. OpenRCX measures each wire's geometry and neighbours and looks the values up in a model built for the process. That is what sign-off timing uses. write_spef then writes the result out. OpenROAD reference

Hint: Ask what another tool would need in order to time this design exactly as it is.

SPEF (Standard Parasitic Exchange Format) lists the resistance and capacitance of every net, which is how extracted parasitics move between tools. read_spef loads such a file back. OpenROAD reference

Hint: Extraction needs to know which set of values in the model to use.

A rules file holds several sets of values, one per process corner. The corner defined here selects one, so several corners can be extracted in the same session and written to separate files. OpenROAD reference

Hint: It prints what is in force, which is not always what you think it is.

Via values are printed too. The values come from the technology file or from set_layer_rc. Checking them is worth doing when delays look wrong, since an empty or wrong value silently changes every estimate. OpenROAD reference

Hint: Two numbers, and the second is a ratio.

Utilization is that instance area divided by the core area. It is the number a flow watches across stages, because repair and clock tree synthesis both add cells. OpenROAD reference

Hint: It counts, it does not measure.

The counts show what the flow has been doing: how many buffers were added, how many fillers, how many taps. -stage labels a report so counts from different stages can be compared. OpenROAD reference

Hint: Wirelength can be counted from an estimate or from the real wires.

Wirelength is the usual quality measure for placement and routing. -detailed_route counts the finished wires instead, -net limits the report to given nets, and without -summary each net is listed. OpenROAD reference

Hint: A net needs something at both ends. Ask which end is missing here.

An undriven net is usually a netlist mistake: a missing connection or logic that was removed. It is checked before placement, because such a net has no meaningful timing. report_overdriven_nets reports the opposite case. OpenROAD reference

Hint: The number is a count, not a length.

The longest nets are where wire delay and slew problems start, so the list is a quick way to find candidates for buffering or for a placement fix. OpenROAD reference

Hint: It concerns the library, not the netlist.

Usable buffers are the standard-cell buffers left after clock buffers, always-on buffers, level shifters, and cells marked set_dont_use are excluded. Their threshold voltage, site, footprint, and leakage are listed too. -filtered shows the smaller set actually used for rebuffering. OpenROAD reference

Hint: The square brackets and the if say what kind of command this is.

Flow scripts use such checks as gates between stages, so a later stage does not run on a design that is not ready. -verbose lists what is missing. OpenROAD reference

Hint: Another gate in a script. Ask what it is guarding against.

Pins may come from the floorplan file or from place_pins. The check lets a script place them only when they are missing, rather than overwriting positions that were given on purpose. OpenROAD reference

Hint: Two limits on the chains that will be built later: how long, and what may share one.

Chains are shift registers built from scan flops. no_mix keeps flops of one clock and edge together, which can leave chains of unequal length; clock_mix allows mixing and stitches falling-edge flops before rising-edge ones. -max_chains takes priority over the length limit. OpenROAD reference

Hint: It changes cells, not connections, and the cells are bigger afterwards.

A scan flop has a second data input and a select, so it can shift instead of capture. The swap changes cell areas, so it is done before placement. OpenROAD reference

Hint: Ask which of preview and commit this one is.

It is the iteration point: change the configuration, look at the chains, and repeat until the plan is right. It is run after scan_replace and global placement, because the plan depends on where the flops are. OpenROAD reference

Hint: This is the step the preview was previewing.

Each chain's scan output feeds the next flop's scan input, and the ends are connected to the scan-in and scan-out drivers named in the configuration. The netlist changes, so timing must be rechecked. OpenROAD reference

Hint: It prints inputs, not results.

The settings are sticky, so a long script can lose track of them. Printing them before planning keeps the plan explainable. OpenROAD reference

Hint: It runs after placement, so it knows where the flops are.

A chain stitched in netlist order can wander across the block. Reordering it into a spatial order keeps the same flops and the same test while cutting the wire the chain costs. OpenROAD reference

Hint: Intent is the word: it says what the power structure should be, not what exists.

UPF (Unified Power Format) describes the power architecture separately from the netlist: which logic shares a supply, what switches it, and what guards the boundaries between domains. The tool then implements it. OpenROAD reference

Hint: A domain is a set of logic before it is a piece of the die.

The domain is a grouping of modules that share a supply. Giving it a region on the die and a voltage are separate steps, and . names the top-level domain. OpenROAD reference

Hint: The domain now gets a place, because a separate supply needs its own grid.

A domain with its own supply needs its own power grid, which means a contiguous region to build it over. Cells of the domain go inside and others stay out, with level shifters at the boundary. OpenROAD reference

Hint: Ask what the tool needs in order to know whether a crossing signal must be shifted.

Domains at different voltages need level shifters between them, so the voltage is part of the intent, not only an analysis setting. It also picks the libraries a domain's cells come from. OpenROAD reference

Hint: Everything here is a declaration. Ask what is not yet decided.

The switch gates a domain's supply so it can be shut off. This says where its supply comes from, what it produces, and what controls it; map_power_switch then names the library cell that implements it. OpenROAD reference

Hint: The switch already exists in the intent. Ask what is still missing to build it.

A header cell passes the supply when enabled and blocks it when not. The mapping ties the abstract switch to that cell and its ports, so the tool can insert real instances. OpenROAD reference

Hint: Ask what a shut-off domain's outputs look like to the logic still running.

An unpowered output floats, and a floating input into always-on logic draws current and can behave unpredictably. An isolation cell, enabled by the isolation signal, holds a defined value instead. OpenROAD reference

Hint: It concerns signals that cross a boundary between two voltages.

The threshold is the voltage difference that triggers one. A signal driven at one voltage may not register correctly at another, so it is passed through a shifter. The threshold is the difference above which one is required. -source and -sink restrict which crossings the strategy applies to. OpenROAD reference

Hint: A strategy says what is needed; this says what to build it from.

The strategy may be an isolation or a level-shifter one. It declares the rule (what to isolate and when); the interface cell declares the implementation. Keeping them apart lets one intent file be used with different libraries. OpenROAD reference

Hint: It reads back what was declared, not what was measured.

Each domain's area and voltage are listed with it. Power intent is easy to get subtly wrong, so reading the domains back is the quick check that the intent file was understood as intended. write_upf writes the whole intent out again. OpenROAD reference

Hint: Pads need somewhere legal to sit, as standard cells need rows.

The east and west rows use the horizontal site, the north and south rows the vertical site, and the four corners their own site. The rotations turn each row's site the right way up; -ring_index handles more than one ring. OpenROAD reference

Hint: The pads are named in order. Ask what decides their exact positions.

The order is left to right for the north and south rows and bottom to top for east and west. Positions are chosen to line up with the bumps when bumps exist, and spread evenly otherwise; -mode chooses explicitly. OpenROAD reference

Hint: Two pad rows meet at each corner of the ring.

There is one at each of the four corners. A corner cell carries the ring's supplies and signals around the turn, so the pad ring stays continuous. Without them the rings on adjacent sides are not connected. OpenROAD reference

Hint: The same idea as filler cells in the core, for a different row.

The fillers are listed widest first, so the row is filled greedily. A continuous row matters because the ring's supplies are carried from pad to pad by abutment. OpenROAD reference

Hint: Neighbouring pads touch. Ask what that contact is for.

Pad and filler cells carry the ring's supplies and control signals across their edges, so placing them against each other wires the ring. The command makes those abutting connections explicit in the netlist. OpenROAD reference

Hint: This is for the older packaging style, where a wire is attached.

In wire bonding a wire runs from a pad on the die to the package, so each I/O (Input/Output) cell needs a bond pad on top of it. Flip-chip parts use a bump array instead. OpenROAD reference

Hint: Read the numbers: a grid, and the distance between its points.

A flip-chip part is turned over and its bumps meet the package directly, so the connections are spread over the whole die rather than around its edge. The pitch is much coarser than anything inside the die. OpenROAD reference

Hint: A bump is just metal until something says what it carries.

Each bump is given a net, and a signal bump is also given the I/O (Input/Output) cell it serves with -terminal. Routing happens unless -dont_route is given, which is used when the redistribution routing is done separately. OpenROAD reference

Hint: The bumps sit above the die, and the pads sit at its edge.

The redistribution layer is a thick metal layer above the die that moves a connection from where the circuit provides it to where the bump needs it. Its wires are wide and widely spaced, hence the values here. OpenROAD reference

Hint: It runs at the end. Ask what the rows would otherwise be mistaken for.

Later tools then ignore them. Pad rows are a placement aid for building the ring, and left behind they can be taken for standard-cell rows by tools that look at rows, so they are removed when the ring is complete. OpenROAD reference

Hint: One file describes several dies and how they sit together.

The file names the chiplets, their instances, and how they bond. 3Dblox, standardized as IEEE 3537, is a language for describing chiplets and their interconnection in 2.5D and 3D packaging: size, orientation, interfaces, thickness, and interconnect regions. Reading one gives OpenROAD the stack to work on. OpenROAD reference

Hint: A structural summary: counts and names, not measurements.

The counts are of chiplets, top-level chip nets, bond regions, and bump pads, and each chip instance is listed with the chiplet it refers to. It is the sanity check after reading a stack, before anything that depends on it, such as timing across chiplets. OpenROAD reference

Hint: Two dies are bonded face to face; something has to line up.

Bonded dies carry marker cells that must land on top of each other. The rule pairs the two masters and sets the largest centre-to-centre misalignment allowed; -relative_orientations also constrains how one may be turned relative to the other. The checker enforces it. OpenROAD reference

Hint: It takes no arguments, so ask what it must already have to work on.

The checks cover the loaded description, including the alignment marker rules registered for bonded chiplets. This part of OpenROAD is new and its documentation is thin, so the tool's own messages are the best guide. OpenROAD reference

[INFO GRT-0096] Final congestion report:
Layer         Resource        Demand        Usage (%)    Max H / Max V / Total Congestion
---------------------------------------------------------------------------------------
metal1               0             0            0.00%             0 /  0 /  0
metal2             957           522           54.55%             0 /  0 /  0
metal3            1394           616           44.19%             0 /  0 /  0
metal4             957           112           11.70%             0 /  0 /  0
metal5             997            41            4.11%             0 /  0 /  0
metal6            1013             0            0.00%             0 /  0 /  0
metal7             302             0            0.00%             0 /  0 /  0
metal8             352             0            0.00%             0 /  0 /  0
metal9             143             0            0.00%             0 /  0 /  0
metal10            143             0            0.00%             0 /  0 /  0
---------------------------------------------------------------------------------------
Total             6258          1291           20.63%             0 /  0 /  0

[INFO GRT-0018] Total wirelength: 6218 um
[INFO GRT-0014] Routed nets: 628

Hint: Compare Demand with Resource on each layer, and read the last column.

Resource is the tracks available and Demand the tracks the router wants; the last columns count the tiles where demand exceeds capacity, and they are all zero. metal2 and metal3 carry the routing because the upper layers are reserved for the power grid and longer nets. OpenROAD reference

Iteration | Overflow |     HPWL (um) |  HPWL(%) |   Penalty | Group
---------------------------------------------------------------
        0 |   0.8751 |  1.457625e+03 |   +0.00% |  3.54e-14 |      
       10 |   0.7488 |  1.788887e+03 |  +22.73% |  5.76e-14 |      
       20 |   0.7303 |  1.810900e+03 |   +1.23% |  9.38e-14 |      
       30 |   0.7305 |  1.810921e+03 |   +0.00% |  1.53e-13 |      
       40 |   0.7342 |  1.806647e+03 |   -0.24% |  2.49e-13 |      
       50 |   0.7323 |  1.812428e+03 |   +0.32% |  4.05e-13 |      
       60 |   0.7316 |  1.813855e+03 |   +0.08% |  6.60e-13 |      
       70 |   0.7324 |  1.810754e+03 |   -0.17% |  1.08e-12 |      
       80 |   0.7318 |  1.809896e+03 |   -0.05% |  1.75e-12 |      
       90 |   0.7310 |  1.810464e+03 |   +0.03% |  2.85e-12 |      

Hint: Overflow measures how much density exceeds the target. Watch it, and watch wirelength.

Overflow is the density excess over the target; placement ends when it reaches the target, not when wirelength stops moving. Wirelength rose from 1457 to about 1810 because the cells started piled together and are being pushed apart. The penalty grows each iteration to force that spreading. OpenROAD reference

    Completing 80% with 9 violations.
    elapsed time = 00:00:00, memory = 1037.00 (MB).
    Completing 90% with 9 violations.
    elapsed time = 00:00:01, memory = 1037.01 (MB).
    Completing 100% with 0 violations.
    elapsed time = 00:00:01, memory = 1037.01 (MB).
[INFO DRT-0199]   Number of violations = 0.

Hint: Each line is one pass over the design. Read the last two.

Detailed routing repeats over the design, ripping up and rerouting what violates the rules. A run is only finished when the violation count reaches zero, which is what the last line confirms. OpenROAD reference

Total wire length = 3605 um.
Total wire length on LAYER metal1 = 0 um.
Total wire length on LAYER metal2 = 1561 um.
Total wire length on LAYER metal3 = 1748 um.
Total wire length on LAYER metal4 = 236 um.
Total wire length on LAYER metal5 = 41 um.
Total wire length on LAYER metal6 = 17 um.
Total wire length on LAYER metal7 = 0 um.
Total wire length on LAYER metal8 = 0 um.
Total wire length on LAYER metal9 = 0 um.
Total wire length on LAYER metal10 = 0 um.

Hint: One layer has no wire at all. Ask what else that layer is needed for.

The platform sets the routing layers, and metal1 is left out because the standard cells' own pins and power rails already occupy it. The wire length concentrates on metal2 and metal3, the lowest layers the router may use. OpenROAD reference

[WARNING GRT-0246] No diode with LEF class CORE ANTENNACELL found.
[INFO ANT-0002] Found 0 net violations.
[INFO ANT-0001] Found 0 pin violations.
[INFO ANT-0002] Found 0 net violations.
[INFO ANT-0001] Found 0 pin violations.

Hint: Three different messages here: read the warning together with the counts.

The warning says the library has no cell of the antenna-diode class, so repair would have nothing to insert. Here it does not matter: the checks report zero net and zero pin violations. The check runs twice because the flow checks before and after attempting repair. OpenROAD reference

[INFO TAP-0004] Inserted 48 endcaps.
[INFO TAP-0005] Inserted 0 tapcells.
Design area 676 um^2 58% utilization.

Hint: Compare the tap spacing the flow asked for with the size of this core.

A core of 1162 square microns is about 34 microns square, and taps are placed on a checkerboard every 120 microns, so none land inside. The 48 endcaps are a separate insertion that terminates the rows. On a larger die the same command would insert many taps. OpenROAD reference

Design area 676 um^2 58% utilization.

Design area 716 um^2 62% utilization.

Hint: The first line is after tap insertion, the second after routing. Ask what ran in between.

Design area counts the instances, not the wires, and the stages in between all add or enlarge cells. Between the two lines came placement, repair, clock tree synthesis, and timing repair, all of which add or enlarge cells. Fillers are added after routing, later than the second line. OpenROAD reference

[INFO CTS-0007] Net "clk" found for clock "core_clock".
[INFO CTS-0010]  Clock net "clk" has 35 sinks.
[INFO CTS-0008] TritonCTS found 1 clock nets.
   ...
[INFO CTS-0027] Generating H-Tree topology for net clk.
[INFO CTS-0028]  Total number of sinks: 35.
   ...
 Level 1
    Direction: Vertical
    Sinks per sub-region: 18
    Sub-region size: 4.1257 X 2.2000
[INFO CTS-0034]     Segment length (rounded): 1.
 Level 2
    Direction: Horizontal
    Sinks per sub-region: 9
    Sub-region size: 2.0629 X 2.2000
[INFO CTS-0034]     Segment length (rounded): 1.
[INFO CTS-0032]  Stop criterion found. Max number of sinks is 15.
[INFO CTS-0035]  Number of sinks covered: 35.

Hint: Read the levels: each one splits the sinks and says which way it cuts.

An H-tree splits the sink region in half at each level, alternating vertical and horizontal, so the path to every leaf is about the same length. Here two levels take 35 sinks down to sub-regions small enough for the stopping rule, which allows at most 15 sinks. OpenROAD reference

Hint: Ask what another tool needs in order to see this layout, without OpenROAD.

DEF (Design Exchange Format) is the portable form of the layout: the boundary, the rows, where every instance sits, and the routing. The technology it refers to stays in the library files. Between OpenROAD stages the database is used instead, since it carries more. OpenROAD reference

Hint: Ask how you would get exactly these macro positions back in a later run.

Automatic macro placement is not repeatable across tool versions, and a reviewed floorplan should not change under you. Writing the result as place_macro commands freezes it, and later runs source the file. write_pin_placement does the same for pins. OpenROAD reference

Hint: Compare it with tapcell, which takes many more options.

tapcell does taps, endcaps, and corner cells together from one long list of masters. This narrower command does the tap checkerboard alone, which suits a flow that places its boundary cells with place_endcaps. OpenROAD reference

Hint: Two layers are given because a ring has to go in both directions.

The horizontal layer carries the pairs above and below, the vertical layer the pairs left and right, so the four together form the ring. The straps inside are extended to meet it, which is how current gets from the ring into the grid. OpenROAD reference

Hint: Ask what would block a later step that needs an empty site.

Fillers occupy every free site, so anything that wants to insert or move a cell must clear them first. A flow removes them, makes its change, and fills again, which is why filler insertion is late in the flow. OpenROAD reference

Hint: Every other repair command decides for itself where buffers go.

It is the manual escape hatch, for a net that repair keeps getting wrong or an experiment. -load_pins chooses which loads move behind the new buffer, so the net can be split deliberately. OpenROAD reference

Hint: It changes nothing by itself. Ask what obeys it afterwards.

The repair commands would otherwise trade as much area, leakage, or site change as they need. The configuration bounds them, with limits on sizing area and leakage and flags to keep the site or the threshold voltage. report_opt_config prints it and reset_opt_config clears it. OpenROAD reference

Hint: Compare it with place_pads, which takes a list and spreads them out.

The offset is measured along the row, so the pad lands where the package needs it. Manual placement is used for pads whose position is fixed by the package, with place_pads filling in the rest. OpenROAD reference

Hint: A pad cell is an instance; ask what the outside world connects to.

The terminal is the point where the design's port exists physically, on the pad's own pin rather than at the core boundary. Bumps and bond pads then attach to those terminals. OpenROAD reference

Hint: Compare it with the power domain, which names logic rather than area.

A power domain is a set of modules; a voltage domain is the area they occupy. The grid generator needs the area, since the region must exist before set_voltage_domain names its power and ground nets and define_pdn_grid builds a grid over it. OpenROAD reference

1. initialize_floorplan
2. pdngen
3. global_placement
4. clock_tree_synthesis
5. detailed_route

Hint: Each one needs something the one before it created.

Rows and a core area come first, then the grid, which must exist before cells are placed over it. The clock tree needs the registers placed, and routing needs the tree. Running these out of order does not usually fail cleanly; it produces a worse result. OpenROAD reference

1. read_lef platform.tech.lef
2. read_lef platform.macro.lef
3. read_verilog gcd.v
4. link_design gcd
5. read_spef gcd.spef

Hint: One kind of file describes the layers that another kind of file uses.

The technology file defines the layers and vias that the cell abstracts refer to, so it is read first. The netlist names cells from those abstracts, linking turns it into a design, and parasitics can only be annotated onto nets that exist. OpenROAD reference

1. repair_design
2. repair_timing -setup
3. repair_timing -hold
4. detailed_placement

Hint: One of them adds delay, so it cannot go first; one of them cleans up after the rest.

Design rules are fixed first, since a pin over its transition limit makes every timing number unreliable. Setup comes before hold, because hold fixes add delay and would otherwise be undone. Everything here inserts and resizes cells, so the row has to be legalized afterwards. OpenROAD reference

Hint: Three of these need the thing the fourth one creates.

The command creates the core, the rows, and the routing tracks, either from a target utilization as here or from an explicit die area, plus the site the rows are built from. Pins, taps, and placement all need those rows. A design read from a layout file already has them. OpenROAD reference

Hint: One of these builds the grid; one only measures it afterwards.

The generator builds the grid from a definition written beforehand. Global connections tell the tool which pins belong to which supply, which is a prerequisite rather than the builder, and the analysis command measures the voltage drop on a grid that already exists. OpenROAD reference

Hint: Two of these move parasitics in or out; only one computes them.

Extraction reads the routed shapes and the layer rules and produces the network. Estimation is the pre-route stand-in based on distance, reading brings in someone else's numbers, and writing exports what the tool already holds. OpenROAD reference