Timing arcs
Each card shows a command to explain. A missed card returns later in the round and starts the schedule over. A card answered correctly moves up the schedule and next appears after 1, 3, 7, then 21 days. Keys 1 to 4 choose an option, h shows a hint, and Enter moves on. A hint keeps the card where it is on the schedule. An ordering card is answered by clicking its items in order, and one wrong click ends it. Time values are in nanoseconds. Progress is stored in this browser.
All 7 cards in this section, with answers
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timing () { related_pin : "CK"; timing_type : hold_rising;An arc from CK to this pin, holding a hold check on the rising edge.
Hint: Two attributes: one names the other end of the arc, one names its kind.
A
timinggroup lives inside the pin it ends at, andrelated_pinsays where it starts.timing_typesays what kind of arc it is: a combinational delay, an edge-triggered delay, or a check such assetup_risingorhold_rising. Liberty reference -
'timing_sense : negative_unate;'A rising input makes the output fall, as in an inverter.
Hint: Ask what happens to the output when the input rises.
Unateness tells the timer which output edge to propagate for a given input edge.
positive_unatepreserves direction,negative_unateinverts it, andnon_unate, as in an exclusive-OR gate, means both must be considered. It is also why a clock through such a gate needsset_sense. Liberty reference -
timing () { related_pin : "A1"; when : "!A2"; timing_sense : negative_unate;This arc applies only while A2 is low, as a NAND's other input must be.
Hint: The condition names another pin. Ask when this arc is the one that applies.
A gate's delay from one input depends on what the others are doing, so a library can hold several arcs for the same pin pair with different conditions. The timer picks the one whose condition can hold, and case analysis can make that choice definite. Liberty reference
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sdf_cond : "A2 == 1'b0";The same condition written for an SDF (Standard Delay Format) file.
Hint: Compare it with `when`: same idea, different consumer.
whenis the condition the timer uses;sdf_condis the same condition in the syntax an SDF (Standard Delay Format) writer needs, so that annotated delays land on the right arc. They should agree, and a mismatch shows up as unannotated arcs. Liberty reference -
pin (Q) { timing () { related_pin : "CK"; } }An arc from CK to Q, since the arc belongs to the pin holding it.
Hint: The group sits inside one pin and names another.
Every arc is read this way: the enclosing pin is the endpoint, and
related_pinis the start. The same shape carries both delays and checks, so atiminggroup inside a data pin naming a clock is a setup or hold check, while one inside an output is a delay. Liberty reference -
timing_type : combinational; timing_type : rising_edge; timing_type : preset; timing_type : three_state_enable;Four kinds of arc, from plain logic to a clocked or enabling one.
Hint: Ask what each one tells the timer about when the arc is active.
combinationalis a plain propagation,rising_edgefires only on a rising clock,presetis an asynchronous path to the output, and the tristate types turn a driver on or off. The type decides which edges the timer pairs and which checks it looks for. Liberty reference -
timing () { related_pin : "CK"; timing_type : min_pulse_width; fall_constraint(Pulse_width_3) { index_1 ("0.00117378,0.0449324,0.198535"); values ("0.075346,0.087068,0.198733"); } }The shortest the clock may stay low, given how sharp its edges are.
Hint: The values are times, and the axis is a transition. Ask what has to last that long.
A pulse shorter than this may not be captured at all. The constraint grows with a slower clock transition, from 0.075 nanoseconds at a sharp edge to 0.199 at the slowest, which is one reason the clock network is held to a tight transition limit.
set_min_pulse_widthcan tighten it. Liberty reference