Games / Command flash cards / Liberty timing libraries / Special cells

Special cells

Each card shows a command to explain. A missed card returns later in the round and starts the schedule over. A card answered correctly moves up the schedule and next appears after 1, 3, 7, then 21 days. Keys 1 to 4 choose an option, h shows a hint, and Enter moves on. A hint keeps the card where it is on the schedule. An ordering card is answered by clicking its items in order, and one wrong click ends it. Time values are in nanoseconds. Progress is stored in this browser.

SourceLiberty is the format that carries a cell library's timing and power. These cards are checked against the Nangate45 library that OpenROAD-flow-scripts ships, and the excerpts are quoted from it. Liberty is a Synopsys format whose specification is licensed; the behaviour described here is what the open timer OpenSTA implements, and answers link to its command reference. Reference: the OpenSTA command reference (Liberty on GitHub).
All 5 cards in this section, with answers
  • latch ("IQ" , "IQN") { data_in : "D"; enable : "G"; }
    A level-sensitive latch, open while its enable is active.

    Hint: Compare the keywords with the ones a flip-flop uses.

    A flip-flop declares next_state and clocked_on; a latch declares data_in and enable, and that difference is how the timer knows to allow time borrowing rather than to check a single edge. The two names in parentheses are the internal state and its complement. Liberty reference

  • ff ("IQ" , "IQN") { next_state : "D"; clocked_on : "CK"; preset : "!SN"; }
    An asynchronous set, active when the SN pin is low.

    Hint: One of these lines does not mention the clock.

    A preset or clear expression acts without the clock, which is why the arcs on such a pin are recovery and removal rather than setup and hold. A cell with both needs clear_preset_var1 to say what the outputs do when both are asserted at once. Liberty reference

  • pin (Z) { function : "A"; three_state : "EN"; }
    The output goes high impedance unless the enable is asserted.

    Hint: Ask what this output does when EN is low.

    The cell has a third state besides high and low, so the timer needs arcs for turning the driver on and off. Those appear as three_state_enable and three_state_disable arcs, and the design has to guarantee that two drivers on the same net are never enabled together. Liberty reference

  • statetable ("CK E SE","IQ") { table : "L L L : - : L , \ L L H : - : H , \ L H L : - : H , \ H - - : - : N " ; } clock_gating_integrated_cell : latch_posedge_precontrol;
    A clock gate whose enable is latched while the clock is low.

    Hint: Look at the last row: what does the cell do while the clock is high?

    Latching the enable while the clock is low stops a late enable from chopping the clock pulse. The attribute tells the tools this is a clock gate rather than ordinary logic, so set_clock_gating_check applies and the clock tree can be built through it. The SE input keeps the gate transparent during scan shift. Liberty reference

  • cell (SDFF_X1) { ff ("IQ" , "IQN") { next_state : "(D & !SE) | (SI & SE)"; clocked_on : "CK"; } }
    A flip-flop with the scan multiplexer built into the cell.

    Hint: Read the next-state expression: it has a choice in it.

    Scan insertion swaps ordinary flops for these, which is why the netlist grows and every register gets two more pins. The multiplexer sits on the data path, so it costs setup time on every functional path, not only during test. Liberty reference