Reading a library
Each card shows real tool output to read. A missed card returns later in the round and starts the schedule over. A card answered correctly moves up the schedule and next appears after 1, 3, 7, then 21 days. Keys 1 to 4 choose an option, h shows a hint, and Enter moves on. A hint keeps the card where it is on the schedule. An ordering card is answered by clicking its items in order, and one wrong click ends it. Time values are in nanoseconds. Progress is stored in this browser.
All 7 cards in this section, with answers
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What does this tell you about the cell, before any timing is read?
report excerpt
cell (DFF_X1) { drive_strength : 1; ff ("IQ" , "IQN") { next_state : "D"; clocked_on : "CK"; } area : 4.522000;It is sequential: the ff group gives its state and its clock.Hint: One group here only appears on a certain kind of cell.
The
ffgroup marks the cell as a flip-flop, names the internal state IQ and its complement, says the next state comes from D, and says CK clocks it.areais in library units and feeds utilization;drive_strengthis the relative label that appears in the cell's name. Liberty reference -
Which check is this, and between which two pins?
report excerpt
pin (D) { direction : input; related_power_pin : "VDD"; related_ground_pin : "VSS"; capacitance : 1.140290; fall_capacitance : 1.062342; rise_capacitance : 1.140290; timing () { related_pin : "CK"; timing_type : hold_rising; fall_constraint(Hold_3_3) { index_1 ("0.00117378,0.0449324,0.198535");A hold check on D against the rising edge of CK.Hint: Look at related_pin and timing_type together, and note which pin group they sit in.
The group sits inside
pin (D), so the check is on D;related_pinnames CK as the reference andtiming_typesays it is a hold check on the rising edge. The values come as a constraint table indexed by the two pins' transitions, not by load. Liberty reference -
Why does this cell have more than one leakage value?
report excerpt
cell_leakage_power : 79.112308; leakage_power () { when : "!CK & !D & !Q & QN"; value : 73.812310; } leakage_power () { when : "!CK & !D & Q & !QN"; value : 77.650980; } leakage_power () { when : "!CK & D & !Q & QN";Leakage depends on the state the cell is holding.Hint: Read the when conditions: they describe the cell's state, not an event.
Which transistors are off depends on the stored state and the inputs, so each state leaks differently.
cell_leakage_poweris the average used when the state probabilities are unknown;report_poweruses the state-dependent values when it has activity data. Liberty reference -
A delay table in this library holds the value 0.0189. What is that?
report excerpt
delay_model : table_lookup; in_place_swap_mode : match_footprint; library_features (report_delay_calculation,report_power_calculation); /* Units Attributes */ time_unit : "1ns"; leakage_power_unit : "1nW"; voltage_unit : "1V"; current_unit : "1mA"; pulling_resistance_unit : "1kohm"; capacitive_load_unit (1,ff);
0.0189 nanoseconds, since the library's time unit is 1 ns.Hint: The file declares its units once, at the top.
Values in Liberty are bare numbers, and the header says what they mean: time in nanoseconds, capacitance in femtofarads, power in nanowatts here. A tool reporting in different units converts on the way out, which
report_unitsshows. Liberty reference -
What kind of cell is this, and what does the timer allow it to do?
report excerpt
cell (DLH_X1) { latch ("IQ" , "IQN") { data_in : "D"; enable : "G"; } area : 2.660000; }A transparent latch, so late data can borrow time through it.Hint: Compare the group's keywords against a flip-flop's.
The
latchgroup withdata_inandenableis the signature. While G is active the cell is transparent, so the timer checks the data against the closing edge and permits borrowing up to the limit set byset_max_time_borrow. The two names are the state and its complement. Liberty reference -
This cell's state table ends with the row "H - - : - : N". What does that row say?
report excerpt
statetable ("CK E SE","IQ") { table : "L L L : - : L ,\ L L H : - : H ,\ L H L : - : H ,\ L H H : - : H ,\ H - - : - : N " ; } clock_gating_integrated_cell : latch_posedge_precontrol;While the clock is high the cell holds its state, whatever the enables do.Hint: The three inputs are CK, E, and SE, and N is not a logic level.
Nmeans no change. The enable is captured only while the clock is low, so a late enable cannot cut a pulse that has already started. That is the whole point of an integrated clock gating cell, and the reasonset_clock_gating_checktimes the enable against the opposite edge. Liberty reference -
The clock reaching this pin has a transition of about 0.045 nanoseconds. What does this table then require?
report excerpt
timing () { related_pin : "CK"; timing_type : min_pulse_width; fall_constraint(Pulse_width_3) { index_1 ("0.00117378,0.0449324,0.198535"); values ("0.075346,0.087068,0.198733"); } }The clock must stay low for at least 0.087 nanoseconds.Hint: Find 0.045 on the axis and read the value beneath it.
It is a fall constraint, so it governs the low phase, and 0.0449 is the second point on the axis, giving 0.087068. A sharper edge would need only 0.075. This is why a clock with a degraded transition can fail a pulse width check that a clean one passes at the same frequency. Liberty reference