Games / Command flash cards / Liberty timing libraries / Constraints and limits

Constraints and limits

Each card shows a command to explain. A missed card returns later in the round and starts the schedule over. A card answered correctly moves up the schedule and next appears after 1, 3, 7, then 21 days. Keys 1 to 4 choose an option, h shows a hint, and Enter moves on. A hint keeps the card where it is on the schedule. An ordering card is answered by clicking its items in order, and one wrong click ends it. Time values are in nanoseconds. Progress is stored in this browser.

SourceLiberty is the format that carries a cell library's timing and power. These cards are checked against the Nangate45 library that OpenROAD-flow-scripts ships, and the excerpts are quoted from it. Liberty is a Synopsys format whose specification is licensed; the behaviour described here is what the open timer OpenSTA implements, and answers link to its command reference. Reference: the OpenSTA command reference (Liberty on GitHub).
All 6 cards in this section, with answers
  • timing_type : setup_rising; timing_type : hold_rising;
    Checks against the rising clock edge: one a setup, one a hold.

    Hint: Both mention the rising edge. Ask whose edge it is.

    The edge in the name is the active clock edge at the related pin. A falling-edge flop uses setup_falling and hold_falling. The values themselves are constraint tables, indexed by the data and clock transitions rather than by load. Liberty reference

  • timing_type : recovery_rising; timing_type : removal_rising;
    The checks on an asynchronous pin's release relative to the clock.

    Hint: Ask which pin these checks belong to; it is not the data pin.

    Asserting a reset needs no timing: the flop resets whenever it arrives. Releasing it does, because a release too close to the clock edge leaves the flop metastable. Recovery is the setup-like check on the release and removal the hold-like one. Liberty reference

  • fall_constraint (Hold_3_3) { index_1 ("..."); /* related pin transition */ index_2 ("..."); /* constrained pin transition */
    A setup or hold value indexed by the clock and data transitions.

    Hint: Compare the axes with a delay table's. Ask what replaced the load.

    A check depends on how sharp both edges are, not on what the pin drives, so load does not appear. A slow clock edge makes setup worse, which is one reason clock slew is held tight. Liberty reference

  • pin (ZN) { direction : output; max_capacitance : 0.150479; max_transition : 0.198535;
    The limits this output declares, which design-rule repair must meet.

    Hint: These sit on an output pin. Ask who has to respect them.

    Beyond these values the tables no longer cover the cell's behaviour. repair_design buffers or upsizes to meet them, and report_check_types -max_slew -max_capacitance reports what remains. SDC (Synopsys Design Constraints) can tighten them but not relax them. Liberty reference

  • rise_constraint (Hold_3_3) { values ("-0.012, -0.009, -0.004"); }
    The data may change slightly before the edge and still be captured.

    Hint: A hold requirement is a time the data must stay stable after the edge.

    Negative values are normal and come from the delays inside the cell: the clock reaches the internal latch after the data does. They make hold easier to meet. Negative setup values also occur, and both are why hold repair must read the library rather than assume zero. Liberty reference

  • default_max_transition : 0.198535; /* library */ pin (ZN) { max_transition : 0.30; } /* cell pin */ set_max_transition 0.15 [current_design]
    The tightest of the three applies at that pin.

    Hint: Three sources set the same limit. Ask which one a tool obeys.

    A cell that can genuinely take a slower edge says so on its pin. A project that wants a sharper edge than any cell requires sets it in the constraints. Design-rule repair works to whichever is smallest at that pin, so a stray global constraint can create work nobody asked for. Liberty reference