Games / Command flash cards / Liberty timing libraries / Cell and pin groups

Cell and pin groups

Each card shows a command to explain. A missed card returns later in the round and starts the schedule over. A card answered correctly moves up the schedule and next appears after 1, 3, 7, then 21 days. Keys 1 to 4 choose an option, h shows a hint, and Enter moves on. A hint keeps the card where it is on the schedule. An ordering card is answered by clicking its items in order, and one wrong click ends it. Time values are in nanoseconds. Progress is stored in this browser.

SourceLiberty is the format that carries a cell library's timing and power. These cards are checked against the Nangate45 library that OpenROAD-flow-scripts ships, and the excerpts are quoted from it. Liberty is a Synopsys format whose specification is licensed; the behaviour described here is what the open timer OpenSTA implements, and answers link to its command reference. Reference: the OpenSTA command reference (Liberty on GitHub).
All 7 cards in this section, with answers
  • cell (DFF_X1) { drive_strength : 1; area : 4.522000;
    The cell's area in library units, and its relative drive strength.

    Hint: Ask which of the two numbers a floorplanner can use directly.

    Area is what report_design_area adds up, and it is the number utilization is computed from. Drive strength is the relative label that appears in the cell's name as _X1; the real drive capability is in the delay tables. Liberty reference

  • ff ("IQ" , "IQN") { next_state : "D"; clocked_on : "CK"; }
    Declares the cell as sequential, naming its state and what clocks it.

    Hint: Ask what this tells a timer that a list of pins and arcs could not.

    The group names the internal state (IQ and its complement), what the next state is (D), and which pin clocks it (CK). That is how a timer knows the cell breaks timing paths rather than passing them through, and where its checks belong. Latches use a latch group instead. Liberty reference

  • pg_pin(VDD) { voltage_name : VDD; pg_type : primary_power; }
    Declares the cell's supply pins and which is power and which ground.

    Hint: Ask which tools need to know about a cell's supply pins.

    Power intent needs this: a cell with two supplies, such as a level shifter or a retention flop, declares each one and what it is for. Signal pins then refer to them through related_power_pin, which ties a pin's characterization to the supply it was measured against. Liberty reference

  • pin (D) { direction : input; capacitance : 1.140290; rise_capacitance : 1.140290; fall_capacitance : 1.062342;
    The load this input presents to its driver, in library units.

    Hint: Ask who pays for this number: the cell itself, or whatever drives it.

    Every load pin adds its capacitance to the net, which is what makes the driver slower. It is why upsizing a cell can hurt: the bigger cell presents a bigger load to the stage before it. Separate rise and fall values exist because the input's capacitance depends on which way it is switching. Liberty reference

  • pin (ZN) { direction : output; function : "!((A1 A2) + B)"; }
    The logic the output performs on the inputs, as a boolean expression.

    Hint: Read the operators: a space, a plus, and an exclamation mark.

    A space means and, a plus means or, an exclamation mark means not, and a circumflex means exclusive or. This is what lets a tool swap one cell for an equivalent one, and what a formal equivalence check compares the netlist against. Liberty reference

  • default_fanout_load : 1.000000; pin (A) { fanout_load : 1.000000; }
    The unit a fanout limit counts, which need not be one per pin.

    Hint: A fanout limit counts something. Ask what unit it counts in.

    A max_fanout of 10 means the sum of the fanout loads on the net must not exceed 10, and a heavy input can declare more than 1. It is a technology-independent stand-in for capacitance, used during synthesis before real loads are known. Liberty reference

  • dont_use
    A mark that keeps a cell in the library but out of the design.

    Hint: The library ships a cell, but this project must not have it placed.

    Teams exclude cells for many reasons: poor yield, high leakage, a hold buffer reserved for repair, or a cell the foundry has withdrawn. The library may carry the attribute, and the flow can add its own with set_dont_use. A cell already placed is not removed, which is why the list is set before synthesis. Liberty reference