Games / Command flash cards / PD fundamentals / Variation and corners

Variation and corners

Each card shows a command to explain. A missed card returns later in the round and starts the schedule over. A card answered correctly moves up the schedule and next appears after 1, 3, 7, then 21 days. Keys 1 to 4 choose an option, h shows a hint, and Enter moves on. A hint keeps the card where it is on the schedule. An ordering card is answered by clicking its items in order, and one wrong click ends it. Time values are in nanoseconds. Progress is stored in this browser.

SourceThese cards cover the reasoning behind physical design rather than any tool's interface: how a timing check is formed, what skew and variation do to it, and what the physical effects cost. Where an idea can be observed in the open flow, the explanation names the command that shows it, and the answer links to its documentation. Reference: the OpenSTA command reference (the open flow on GitHub).
All 9 cards in this section, with answers
  • why several corners are analysed
    Different checks fail at different conditions, so no single corner covers both.

    Hint: Ask which check is worst when everything is slow.

    Setup is worst when cells are slow, hot, and at low voltage; hold is worst when they are fast. A part sold across a voltage and temperature range must pass at every corner it is guaranteed at, which is why sign-off runs them all. the open flow reference

  • on-chip variation
    Cells on one die differ from each other, not just die from die.

    Hint: Ask why one corner for the whole die is still optimistic.

    One corner for the whole die is therefore still optimistic. Doping, lithography, and local temperature all vary across a die, so two cells at the same corner are not identical. Analysis therefore derates the launch and capture paths in opposite directions, which set_timing_derate controls. the open flow reference

  • clock reconvergence pessimism removal
    It credits back derating applied twice on the shared clock path.

    Hint: Part of the clock path is shared. Ask whether it can be fast and slow at once.

    The shared path cannot be both fast and slow. Derating makes the launch clock late and the capture clock early, but the part of the tree they share cannot be both. CRPR (Clock Reconvergence Pessimism Removal) gives that difference back, and the line appears in every report_checks path. the open flow reference

  • set_timing_derate -early 0.95 -late 1.05
    Data is derated late and the capture clock early, for setup.

    Hint: Ask which path of a setup check is made slow, and which fast.

    Each check then sees its own worst case. For setup the data path takes the late factor and the capture clock the early one; for hold the assignment reverses. The pair is what makes the analysis pessimistic in both directions at once, and CRPR (Clock Reconvergence Pessimism Removal) then removes the part that cannot physically happen. the open flow reference

  • multi-corner multi-mode
    Several operating conditions crossed with several modes.

    Hint: Two independent axes. Ask what each one varies.

    Modes bring their own constraints: a chip has functional, test, and low-power modes, each with its own constraints, and each must hold at every corner. The combinations are what sign-off covers, and what makes it expensive. OpenSTA calls one combination a scene. the open flow reference

  • why a margin is kept for aging
    Transistors slow as they age, so a part must start with margin to last.

    Hint: Ask what happens to a transistor after years of use.

    Mechanisms such as bias temperature instability and hot-carrier injection shift a transistor's threshold over its lifetime, and electromigration thins conductors. Designs therefore sign off with margin, or at a corner characterized for end of life. the open flow reference

  • slow-slow and worst-capacitance
    One names the transistors' corner, the other the wires' parasitics.

    Hint: Two names from two different files. Ask what each one varies.

    Library corners such as slow-slow, typical-typical, and fast-fast come from the transistors' process, voltage, and temperature. Parasitic corners come from the metal's own variation and are chosen separately, which is why sign-off pairs them: a slow library with worst capacitance for setup, a fast one with best for hold. the open flow reference

  • temperature inversion
    At low supply voltage, cold silicon can be slower than hot.

    Hint: The old rule is hot equals slow. Ask when that stops being true.

    Two effects compete: carrier mobility falls with heat, which slows a cell, and the threshold voltage falls with heat, which speeds it. At low supply the threshold effect wins, so the worst case moves to cold. This is why a modern flow signs off at both temperature extremes rather than assuming hot is worst. the open flow reference

  • advanced and parametric on-chip variation
    They vary the derate with path depth and location instead of using one factor.

    Hint: Ask what a single derate factor ignores about a path.

    A long path averages out random variation, so a flat derate over-margins it, while a short path needs more. Advanced on-chip variation uses depth-dependent factors, parametric methods carry a distribution per cell, and Liberty variation data supplies the per-cell numbers. the open flow reference