Games / Command flash cards / PD fundamentals / Test concepts

Test concepts

Each card shows a command to explain. A missed card returns later in the round and starts the schedule over. A card answered correctly moves up the schedule and next appears after 1, 3, 7, then 21 days. Keys 1 to 4 choose an option, h shows a hint, and Enter moves on. A hint keeps the card where it is on the schedule. An ordering card is answered by clicking its items in order, and one wrong click ends it. Time values are in nanoseconds. Progress is stored in this browser.

SourceThese cards cover the reasoning behind physical design rather than any tool's interface: how a timing check is formed, what skew and variation do to it, and what the physical effects cost. Where an idea can be observed in the open flow, the explanation names the command that shows it, and the answer links to its documentation. Reference: the OpenSTA command reference (the open flow on GitHub).
All 5 cards in this section, with answers
  • why a chip needs scan
    It makes every register directly settable and readable from the pins.

    Hint: Ask how you would set a register deep inside a chip from outside it.

    Controllability and observability are the problem: a fault deep in the logic cannot be excited or seen from the pins in normal operation. Chaining the registers into a shift register solves both, at the cost of a larger flop, the chain's wiring, and the test pins. the open flow reference

  • stuck-at coverage of 98%
    98% of the modelled faults are excited and observed.

    Hint: Ask what model that number counts against.

    A fault model is a simplification: stuck-at assumes a node is welded to a value. Coverage counts modelled faults, not real defects, so a high number with a weak model still lets parts escape. Untestable logic, such as redundant gates, is why 100% is rare. the open flow reference

  • at-speed test against a stuck-at test
    At-speed test catches defects that slow a path rather than break it.

    Hint: One kind of defect only shows up when the chip runs fast.

    A resistive via or a weak transistor still passes a slow test but fails at frequency. Transition-fault patterns launch and capture in consecutive fast cycles, which is why the scan chains and the clocking must work at speed and why the test mode has its own timing constraints. the open flow reference

  • what scan costs the physical design
    Larger flops, and a long chain competing for routing.

    Hint: Ask what a chain of hundreds of registers does to the layout.

    A chain stitched in netlist order wanders across the block, which is why scan_opt reorders it after placement to follow physical proximity. The scan enable is also a high-fanout net, usually treated as an ideal network until it is buffered. the open flow reference

  • why test mode has its own constraints
    Shifting uses a slower clock and different paths.

    Hint: Ask what the clock and the enables are doing during a shift.

    During shift the data path is register to register through the scan inputs, usually at a slower clock, while functional paths are irrelevant. Capture cycles are at speed. Each mode is a separate set of constraints, which is what multi-mode analysis exists for. the open flow reference