Games / Command flash cards / PD fundamentals / Signal integrity

Signal integrity

Each card shows a command to explain. A missed card returns later in the round and starts the schedule over. A card answered correctly moves up the schedule and next appears after 1, 3, 7, then 21 days. Keys 1 to 4 choose an option, h shows a hint, and Enter moves on. A hint keeps the card where it is on the schedule. An ordering card is answered by clicking its items in order, and one wrong click ends it. Time values are in nanoseconds. Progress is stored in this browser.

SourceThese cards cover the reasoning behind physical design rather than any tool's interface: how a timing check is formed, what skew and variation do to it, and what the physical effects cost. Where an idea can be observed in the open flow, the explanation names the command that shows it, and the answer links to its documentation. Reference: the OpenSTA command reference (the open flow on GitHub).
All 7 cards in this section, with answers
  • crosstalk delta delay
    A neighbour switching the other way slows the victim down.

    Hint: Two nets switch together. Ask when it helps and when it hurts.

    Switching the same way speeds it up instead. The coupling capacitance sees a doubled voltage swing when the two nets move oppositely, which is the Miller effect, so it charges more slowly. Setup analysis takes the slowing case and hold the speeding one, from aggressors whose switching windows overlap the victim's. the open flow reference

  • crosstalk noise, as opposed to delta delay
    A quiet net is pulled by its neighbour, and may glitch its receiver.

    Hint: Ask what happens to a net that is not switching at all.

    Delta delay is about a switching victim; noise is about a static one. A large enough glitch can be latched or can propagate through combinational logic. The defences are the same: spacing, shielding, and shorter parallel runs. the open flow reference

  • how a sensitive net is protected
    More spacing, a shield net alongside, or a shorter parallel run.

    Hint: Three ways, all geometric rather than electrical.

    Coupling grows with the length two wires run alongside and falls with their separation, so the fixes are geometric. A non-default rule that widens and spaces a net is the usual mechanism, and a grounded shield wire is the strongest form. the open flow reference

  • why a slow transition is a problem
    It adds delay, burns current, and invites noise at the input.

    Hint: Name three separate costs, not just the delay.

    Three costs, not one. While an input sits between the rails, both transistor stacks conduct, so current flows straight from supply to ground. A slow edge also lengthens the window where noise can flip the receiver, and it makes the next stage's delay worse. This is why maximum transition is a rule. the open flow reference

  • the noise margin of a gate
    The gap between the level a driver guarantees and the level a receiver accepts.

    Hint: Ask against what a glitch's size is judged.

    A gate accepts anything below its low threshold as a zero and above its high threshold as a one; the unclaimed middle is the margin a glitch has to cross to matter. Margins shrink with the supply voltage, which is why noise became a first-class concern as voltages fell. the open flow reference

  • why an aggressor's switching window matters
    Coupling only affects the victim if the aggressor switches while it does.

    Hint: Ask what has to be true at the same time for coupling to hurt.

    Each net has a range of times in which it can switch. If the windows cannot overlap, the aggressor cannot change the victim's delay, and a tool that ignored this would report impossible worst cases. Windows depend on timing, so the analysis iterates: timing changes windows, which changes delays. the open flow reference

  • a glitch that reaches a register against one that does not
    A glitch matters when it is captured or propagated onward.

    Hint: Ask what makes a glitch harmful rather than merely present.

    Combinational logic can pass a glitch along, and a register can latch one if it lands in the sampling window. On a clock or asynchronous pin it is worse, since those need no window at all. Glitches that harm nothing still cost power, which is a separate concern. the open flow reference