Games / Command flash cards / PD fundamentals / Physical effects

Physical effects

The cards come in more than one shape: a command to explain, and steps to put in order. A missed card returns later in the round and starts the schedule over. A card answered correctly moves up the schedule and next appears after 1, 3, 7, then 21 days. Keys 1 to 4 choose an option, h shows a hint, and Enter moves on. A hint keeps the card where it is on the schedule. An ordering card is answered by clicking its items in order, and one wrong click ends it. Time values are in nanoseconds. Progress is stored in this browser.

SourceThese cards cover the reasoning behind physical design rather than any tool's interface: how a timing check is formed, what skew and variation do to it, and what the physical effects cost. Where an idea can be observed in the open flow, the explanation names the command that shows it, and the answer links to its documentation. Reference: the OpenSTA command reference (the open flow on GitHub).
All 12 cards in this section, with answers
  • why wire delay grows faster than length
    Resistance and capacitance both grow with length, so delay grows with its square.

    Hint: Both resistance and capacitance grow with length. Ask what their product does.

    A wire is a distributed network whose delay goes with resistance times capacitance, and each is proportional to length. Splitting a long wire with buffers turns one quadratic term into several small ones, which is why repair_design -max_wire_length exists. the open flow reference

  • why high fanout is a problem
    Each load adds capacitance, and reaching them all adds wire.

    Hint: Two separate costs: one at the driver, one in the layout.

    A high-fanout net is slow both because of the pin capacitance and because the wire has to travel to every load. The fix is a buffer tree, which trades cell delay for shorter wires, and it is what repair builds when a net exceeds the fanout limit. the open flow reference

  • why utilization is not pushed to the limit
    Later steps add cells, and routing needs space between them.

    Hint: Ask what else needs the space besides the cells that are already there.

    Buffering, clock tree synthesis, and timing repair all add cells after placement, and routing needs tracks that cells do not block. A design packed at 90% may place and then fail to route or to close timing, which is why the target is set by what the flow still has to do. the open flow reference

  • routing congestion
    More nets want to cross a region than it has tracks for.

    Hint: Ask what is being compared with what, in a small region.

    Capacity comes from the tracks in a region; demand from the nets routed through it. Congestion is fixed by spreading the cells that cause it, which is why the placer has a routability mode and why padding and density are the usual controls. global_route reports it per layer. the open flow reference

  • what inserting a buffer costs
    Its own delay, area, and power, in exchange for breaking the wire up.

    Hint: It shortens the wire, but the buffer is not free.

    Buffering wins when the quadratic wire delay saved exceeds the buffer's own delay, which is why there is an optimal spacing rather than "more is better". Each buffer also needs a site, power, and a place in the clock or data path that repair must keep legal. the open flow reference

  • why the floorplan decides the outcome
    Later stages can move cells and wires, but not the shape the floorplan imposed.

    Hint: Ask which later stage can undo a bad macro placement.

    Macros in the wrong place force long wires and pinch routing channels, and no amount of placement or routing effort recovers that. This is why a floorplan is reviewed before the flow is allowed to continue, and why macro placement is treated as a decision rather than an optimization. the open flow reference

  • a placement that is legal but will not route
    The pins cannot be entered: their access points are blocked.

    Hint: Ask what the router needs at each pin that legalization never checks.

    A pin is reachable only from certain directions and through certain vias, and two cells side by side can block each other's access. This is why placement padding exists, why some cells are excluded from use, and why pin_access runs before detailed routing. the open flow reference

  • why the upper metal layers are thicker
    Thick upper layers carry power and long wires with less resistance.

    Hint: Ask what each part of the stack is for, given the same process.

    Resistance falls with thickness, so long nets and the power grid go up the stack, while dense local routing stays on the thin, fine-pitch lower layers. This is the reason clocks are routed high, why the grid takes the top layers, and why layer assignment matters for delay. the open flow reference

  • why a via count matters on a long net
    Each via adds resistance, so many layer changes slow a net.

    Hint: Ask what a layer change costs, besides the wire on each side.

    A via is a small plug of high-resistance metal, and a route that zigzags up and down the stack accumulates them. This is why routers prefer to stay on a layer, why via arrays are used on wide nets, and why via resistance appears in the extraction rules. the open flow reference

  • turning a macro so its pins face the logic
    Wires shorten when the pin edge faces what it connects to.

    Hint: The macro's pins are usually on one edge. Ask what that implies for placement.

    A pin edge facing away means every net wraps around the block, spending wire and congesting the channel behind it. The related choice is whether macros abut or leave a channel: abutted saves area, a channel leaves room for routing and buffers. the open flow reference

  • fin quantization and multiple patterning
    Drive strength comes in steps, and shapes are colored onto masks.

    Hint: Two constraints from the same source: what the process can actually print.

    The width of a FinFET (Fin Field-Effect Transistor) is a whole number of fins, so sizing moves in steps rather than smoothly. Below the wavelength limit a layer is printed with several masks, and shapes too close together must go on different ones, which the rules enforce as a coloring problem the router must respect. the open flow reference

  • Put these estimates of a net's delay in order, from earliest to most trustworthy.
    1. a wire load model, from fanout alone
    2. a placement-based estimate, from the distance between cells
    3. a global route estimate, from the layers and the congestion
    4. extracted parasitics from the detailed route

    Hint: Each one knows something the one before it could only guess.

    Each rung knows more about where the wire actually goes. This is why timing moves at every stage, why early numbers are optimistic, and why a design that closes only just at placement rarely closes after routing. the open flow reference