Games / Command flash cards / PD fundamentals / Flow reasoning

Flow reasoning

The cards come in more than one shape: a command to explain, and steps to put in order. A missed card returns later in the round and starts the schedule over. A card answered correctly moves up the schedule and next appears after 1, 3, 7, then 21 days. Keys 1 to 4 choose an option, h shows a hint, and Enter moves on. A hint keeps the card where it is on the schedule. An ordering card is answered by clicking its items in order, and one wrong click ends it. Time values are in nanoseconds. Progress is stored in this browser.

SourceThese cards cover the reasoning behind physical design rather than any tool's interface: how a timing check is formed, what skew and variation do to it, and what the physical effects cost. Where an idea can be observed in the open flow, the explanation names the command that shows it, and the answer links to its documentation. Reference: the OpenSTA command reference (the open flow on GitHub).
All 12 cards in this section, with answers
  • flat against hierarchical implementation
    Flat gives better results; hierarchical makes a large design tractable.

    Hint: Ask what each one buys, given the same design and the same tools.

    Optimizing across block boundaries is strictly better, but runtime and memory grow faster than linearly, and a team cannot work on one flat database at once. Hierarchy buys parallel work and repeatability at the cost of the boundaries it freezes. the open flow reference

  • why a block is abstracted
    The top level needs its outline, pins, and timing, not its contents.

    Hint: Ask what the top level needs to know about a finished block, and what it does not.

    A block's insides are millions of objects the top level would only slow down on. An abstract LEF (Library Exchange Format) gives the shape and pins and write_timing_model the timing, so the top level treats it as a macro. the open flow reference

  • why a late fix is made as an ECO
    A small local edit keeps everything else exactly as it was verified.

    Hint: Ask what re-running the flow would cost, besides time.

    Re-running from synthesis produces a different netlist and a different layout, so every check and every verification result starts again. An ECO (Engineering Change Order) touches a few cells and keeps the rest of the sign-off evidence valid, which is why closure ends in small edits. the open flow reference

  • why timing closure is iterative
    Each fix moves cells and wires, which changes the timing of other paths.

    Hint: Ask what a fix in one place does elsewhere.

    Adding a buffer displaces neighbours, changes parasitics, and can create a new critical path. The flow therefore alternates repair and analysis rather than fixing everything at once, and a stage's result is only trusted after its own analysis has run. the open flow reference

  • why early timing is optimistic
    Each stage's estimate of the wires is closer to the truth than the last.

    Hint: Ask what each stage knows that the one before it did not.

    Before placement there are no distances, after placement only straight lines, after global routing the regions, and only after detailed routing the real wires. Each step reveals cost the last one could not see, which is why margins are kept early and released late. the open flow reference

  • the PPA (Power, Performance, Area) trade
    Pushing any one of the three costs the other two, so a target is a choice.

    Hint: Ask what happens to the other two when one is pushed.

    A faster design uses bigger cells at lower threshold voltage, spending area and leakage; a smaller one is slower. The quality of a run is reported as worst and total negative slack, area, power, and the violation counts, and a team weighs them against the product's needs. the open flow reference

  • a metal-only ECO against an all-layer ECO
    A metal-only change reuses the base masks by rewiring spare cells.

    Hint: Ask which masks each one changes, and what that costs.

    The transistor masks are the expensive ones, so designs scatter spare cells through the layout in advance; a late fix connects them with metal changes alone. An all-layer change can add real cells but needs the full mask set again. This is why spare cells are placed before anyone knows what will break. the open flow reference

  • why the implementation timer and the sign-off timer disagree
    They use different delay calculation and parasitics, so their slacks differ.

    Hint: Ask what each tool is optimized for, given the same design.

    An implementation tool times millions of paths thousands of times, so it trades accuracy for speed; a sign-off timer does the opposite. Teams measure the gap and carry margin for it, which is exactly what SETUP_SLACK_MARGIN and its equivalents are for. the open flow reference

  • budgeting a block's interface timing
    A share of the period at each port, as input and output delays.

    Hint: The block is designed alone but must fit a whole. Ask what it is given.

    Someone has to decide how much of a cycle belongs inside the block and how much to the logic around it. That split becomes the block's constraints, and the top level assumes the block meets them. Budgets that do not add up are discovered late, at integration. the open flow reference

  • why setup is fixed before hold
    Hold fixes add delay, which can break setup, so setup is settled first.

    Hint: Ask what each fix does to the other check.

    Adding buffers for hold slows the path, and if setup were already tight it fails again. Repair therefore runs setup first, and hold repair refuses to insert a buffer that would break setup unless told otherwise. Hold is also fixed late, when the clock tree and routing are real. the open flow reference

  • Put these stages in the order a flow runs them.
    1. floorplan and power grid
    2. placement
    3. clock tree synthesis
    4. routing
    5. parasitic extraction and sign-off timing

    Hint: Each stage needs something the stage before it produced.

    Nothing can be placed before there are rows and a grid, the clock tree needs the registers placed, routing needs the tree, and only a routed design has parasitics worth extracting. Each stage also re-times, which is why an early mistake is expensive. the open flow reference

  • Put these in the order a sign-off run needs them.
    1. detailed routing
    2. metal fill
    3. parasitic extraction
    4. static timing analysis

    Hint: One of these changes the capacitance the others measure.

    Fill is added after routing, and it adds capacitance to the nets beside it. Extracting before the fill exists gives numbers that are too optimistic, so the order matters: route, fill, extract, then time. the open flow reference