Games / Command flash cards / PD fundamentals / Clocking

Clocking

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SourceThese cards cover the reasoning behind physical design rather than any tool's interface: how a timing check is formed, what skew and variation do to it, and what the physical effects cost. Where an idea can be observed in the open flow, the explanation names the command that shows it, and the answer links to its documentation. Reference: the OpenSTA command reference (the open flow on GitHub).

All 11 cards in this section, with answers

latency against skew

Latency is the delay to a register; skew is the difference between two.

Hint: One is an absolute delay, the other a difference. Ask which hurts a check.

Equal latency at both ends cancels in a same-clock check, so a deep clock tree is not itself a timing problem. The difference between the two ends does not cancel, which is why the tree is balanced rather than merely made short. report_clock_skew shows the difference. the open flow reference
skew that delays the capture clock

It helps setup, by giving the data more time, and hurts hold.

Hint: Work through both checks: the late capture edge helps one and hurts the other.

A late capture edge extends the setup window and shortens the hold window by the same amount. This is why fixing hold by adding buffers can be cheaper than rebalancing a tree, and why useful skew is deliberately unbalanced rather than skew being minimized everywhere. the open flow reference
jitter against skew

Skew is a difference between registers; jitter is a variation over time.

Hint: One varies between places, the other between cycles.

Jitter comes from the clock generator and from supply noise, so it cannot be designed out of the tree. It enters analysis as part of set_clock_uncertainty, along with a margin for skew before the tree exists. the open flow reference
useful skew

Deliberate skew that moves slack from a path with margin to one without.

Hint: Ask what deliberately unbalancing the tree can buy.

Delaying a register's clock gives the path into it more time and the path out of it less. Where the outgoing path has margin, that is free speed. It costs hold margin and makes the design more sensitive to variation, so it is used deliberately and sparingly. the open flow reference
a clock domain crossing

The two clocks have no fixed phase, so no margin guarantees it.

Hint: Ask why timing analysis cannot close such a path, however much margin it has.

No margin closes it. With no fixed relationship, an edge can land arbitrarily close to the data change, and the receiving register can go metastable. The fix is a synchronizer, and timing declares the crossing false with set_clock_groups -asynchronous. Verifying the synchronizers is a separate check. the open flow reference
why a clock gate needs its own check

A late enable can cut a clock pulse short, producing a runt edge.

Hint: Ask what a late enable would do to the shape of the gated clock.

The check constrains the enable against the clock so the gate only ever produces whole pulses. The integrated cell latches the enable to make that possible, and set_clock_gating_check sets the margins. the open flow reference
an H-tree, a mesh, and a spine

Increasingly expensive ways to buy lower skew, from tree to grid.

Hint: Order them by how much metal and power they spend on skew.

An H-tree balances by construction and is cheap, but its skew depends on the loads matching. A mesh shorts the leaves together, so skew is very low and the power very high. A spine is the middle: a strong backbone with trees hanging off it. The choice follows the skew budget. the open flow reference
why a shallower clock tree is not automatically better

A shallow tree needs bigger buffers and matches loads less easily.

Hint: Ask what a deep tree costs, and what shallowness costs in return.

Latency itself cancels within a clock, so depth is not the enemy; what matters is skew, power, and how sensitive the tree is to variation. Deep trees accumulate variation, and shallow ones need strong drivers and long wires. Insertion delay also matters at a block's boundary, where it does not cancel. the open flow reference
what clock gating actually saves

The switching power of the clock branch below the gate.

Hint: Ask how far down the tree the saving reaches.

Everything below a disabled gate stops toggling, including the register clock pins, which is where most clock power sits. The costs are the gate's own area, a timing check on its enable, and a tree that is harder to balance because branches switch independently. the open flow reference
duty cycle distortion along a clock path

Each unbalanced stage shifts one edge relative to the other, shrinking a pulse.

Hint: Ask what happens if a buffer's rise delay differs from its fall delay.

A pulse that starts at half the period can arrive much narrower, and a register needs a minimum high and low time to work. This is why clock cells are drawn with matched edges and why set_min_pulse_width is checked at the leaves. the open flow reference
a reset domain crossing

A register reset by one reset feeds one reset by another.

Hint: The clock domains can be the same. Ask what differs instead.

If one register is released from reset while its neighbour is still held, the released one can capture a value that the other is about to change, which is the same hazard as a clock crossing. Reset domain crossing checks are a separate verification step, distinct from clock domain crossing. the open flow reference