All sections

Hint: Write the inequality: data arrival against the next capture edge.

Uncertainty comes off as well. Arrival is the launch edge plus the launch clock's latency, the register's clock-to-output delay, and the logic delay. Required is the capture edge plus the capture clock's latency, minus the setup time and the uncertainty. Setup slack is required minus arrival, which is what report_checks prints at the bottom. the open flow reference

Hint: The two edges involved are usually the same one, not a cycle apart.

Hold compares the fastest path against the same capture edge, so the period cancels out. That is why hold failures do not improve when the clock is slowed, and why they are fixed by adding delay to the data path rather than by relaxing the clock. the open flow reference

Hint: One number, formed from two. Ask which is subtracted from which.

The same definition covers both checks because required time means different things in each: the latest allowed arrival for setup and the earliest for hold, where the subtraction reverses. Slack is the universal currency of timing closure. the open flow reference

Hint: Ask whether it is about delay alone, or about delay against a requirement.

A long path with a relaxed requirement, such as a multicycle path, can have more slack than a short path on a fast clock. Optimization works on slack, so the critical path is defined by slack, and it moves as the design is fixed. the open flow reference

Hint: Two registers, two clock edges. Ask which edge belongs to which register.

Both edges come from the clock, but they arrive at different registers after different clock-tree paths, which is where skew enters. Writing a check as launch-side against capture-side is what makes the effect of skew, latency, and uncertainty easy to see. the open flow reference

Hint: Ask what the designer knows that the timer does not.

An exception is a promise about behaviour: an enable holds the capture register, or the protocol waits. If the promise is wrong the chip fails in a way no timing report will show, which is why exceptions are reviewed as carefully as they are written. the open flow reference

Hint: One is an absolute delay, the other a difference. Ask which hurts a check.

Equal latency at both ends cancels in a same-clock check, so a deep clock tree is not itself a timing problem. The difference between the two ends does not cancel, which is why the tree is balanced rather than merely made short. report_clock_skew shows the difference. the open flow reference

Hint: Work through both checks: the late capture edge helps one and hurts the other.

A late capture edge extends the setup window and shortens the hold window by the same amount. This is why fixing hold by adding buffers can be cheaper than rebalancing a tree, and why useful skew is deliberately unbalanced rather than skew being minimized everywhere. the open flow reference

Hint: One varies between places, the other between cycles.

Jitter comes from the clock generator and from supply noise, so it cannot be designed out of the tree. It enters analysis as part of set_clock_uncertainty, along with a margin for skew before the tree exists. the open flow reference

Hint: Ask what deliberately unbalancing the tree can buy.

Delaying a register's clock gives the path into it more time and the path out of it less. Where the outgoing path has margin, that is free speed. It costs hold margin and makes the design more sensitive to variation, so it is used deliberately and sparingly. the open flow reference

Hint: Ask why timing analysis cannot close such a path, however much margin it has.

No margin closes it. With no fixed relationship, an edge can land arbitrarily close to the data change, and the receiving register can go metastable. The fix is a synchronizer, and timing declares the crossing false with set_clock_groups -asynchronous. Verifying the synchronizers is a separate check. the open flow reference

Hint: Ask what a late enable would do to the shape of the gated clock.

The check constrains the enable against the clock so the gate only ever produces whole pulses. The integrated cell latches the enable to make that possible, and set_clock_gating_check sets the margins. the open flow reference

Hint: Ask which check is worst when everything is slow.

Setup is worst when cells are slow, hot, and at low voltage; hold is worst when they are fast. A part sold across a voltage and temperature range must pass at every corner it is guaranteed at, which is why sign-off runs them all. the open flow reference

Hint: Ask why one corner for the whole die is still optimistic.

One corner for the whole die is therefore still optimistic. Doping, lithography, and local temperature all vary across a die, so two cells at the same corner are not identical. Analysis therefore derates the launch and capture paths in opposite directions, which set_timing_derate controls. the open flow reference

Hint: Part of the clock path is shared. Ask whether it can be fast and slow at once.

The shared path cannot be both fast and slow. Derating makes the launch clock late and the capture clock early, but the part of the tree they share cannot be both. CRPR (Clock Reconvergence Pessimism Removal) gives that difference back, and the line appears in every report_checks path. the open flow reference

Hint: Ask which path of a setup check is made slow, and which fast.

Each check then sees its own worst case. For setup the data path takes the late factor and the capture clock the early one; for hold the assignment reverses. The pair is what makes the analysis pessimistic in both directions at once, and CRPR (Clock Reconvergence Pessimism Removal) then removes the part that cannot physically happen. the open flow reference

Hint: Two independent axes. Ask what each one varies.

Modes bring their own constraints: a chip has functional, test, and low-power modes, each with its own constraints, and each must hold at every corner. The combinations are what sign-off covers, and what makes it expensive. OpenSTA calls one combination a scene. the open flow reference

Hint: Ask what happens to a transistor after years of use.

Mechanisms such as bias temperature instability and hot-carrier injection shift a transistor's threshold over its lifetime, and electromigration thins conductors. Designs therefore sign off with margin, or at a corner characterized for end of life. the open flow reference

Hint: Two nets switch together. Ask when it helps and when it hurts.

Switching the same way speeds it up instead. The coupling capacitance sees a doubled voltage swing when the two nets move oppositely, which is the Miller effect, so it charges more slowly. Setup analysis takes the slowing case and hold the speeding one, from aggressors whose switching windows overlap the victim's. the open flow reference

Hint: Ask what happens to a net that is not switching at all.

Delta delay is about a switching victim; noise is about a static one. A large enough glitch can be latched or can propagate through combinational logic. The defences are the same: spacing, shielding, and shorter parallel runs. the open flow reference

Hint: Three ways, all geometric rather than electrical.

Coupling grows with the length two wires run alongside and falls with their separation, so the fixes are geometric. A non-default rule that widens and spaces a net is the usual mechanism, and a grounded shield wire is the strongest form. the open flow reference

Hint: Name three separate costs, not just the delay.

Three costs, not one. While an input sits between the rails, both transistor stacks conduct, so current flows straight from supply to ground. A slow edge also lengthens the window where noise can flip the receiver, and it makes the next stage's delay worse. This is why maximum transition is a rule. the open flow reference

Hint: Three components. Ask which one exists even when nothing switches.

Switching power is the load capacitance times the supply squared times the activity; internal power is the cell's own cost per transition, from its library; leakage flows whether or not anything switches. Clock networks dominate the first two because they switch every cycle. the open flow reference

Hint: Ask how often a clock switches compared with a data net.

A data net switches on a fraction of cycles; the clock switches twice per cycle everywhere. This is why clock gating, multi-bit flops, and fewer clock buffers all matter so much, and why clock power is reported as its own group. the open flow reference

Hint: Ask at what voltage the library was characterized, and what the cell actually gets.

Timing is computed at the library's voltage, so a local droop makes real silicon slower than the report. Designs either keep drop under a budget (a few percent of the supply) or analyse timing at the reduced voltage. analyze_power_grid finds the drop. the open flow reference

Hint: Ask what physically moves, and over what timescale.

Momentum from the electron flow moves atoms along the wire, opening it eventually. The limit is a current density, not a current, which is why widening a strap fixes it. It is a wear-out mechanism: the part works when new and fails in the field. the open flow reference

Hint: Ask what the grid cannot deliver quickly enough on its own.

The charge is held beside the cells that need it. The grid has inductance and resistance, so a sudden demand outruns it. A capacitor beside the switching cells supplies that moment and recharges between. It costs leakage and area, so decaps are placed where switching is heaviest. the open flow reference

Hint: Both resistance and capacitance grow with length. Ask what their product does.

A wire is a distributed network whose delay goes with resistance times capacitance, and each is proportional to length. Splitting a long wire with buffers turns one quadratic term into several small ones, which is why repair_design -max_wire_length exists. the open flow reference

Hint: Two separate costs: one at the driver, one in the layout.

A high-fanout net is slow both because of the pin capacitance and because the wire has to travel to every load. The fix is a buffer tree, which trades cell delay for shorter wires, and it is what repair builds when a net exceeds the fanout limit. the open flow reference

Hint: Ask what else needs the space besides the cells that are already there.

Buffering, clock tree synthesis, and timing repair all add cells after placement, and routing needs tracks that cells do not block. A design packed at 90% may place and then fail to route or to close timing, which is why the target is set by what the flow still has to do. the open flow reference

Hint: Ask what is being compared with what, in a small region.

Capacity comes from the tracks in a region; demand from the nets routed through it. Congestion is fixed by spreading the cells that cause it, which is why the placer has a routability mode and why padding and density are the usual controls. global_route reports it per layer. the open flow reference

Hint: It shortens the wire, but the buffer is not free.

Buffering wins when the quadratic wire delay saved exceeds the buffer's own delay, which is why there is an optimal spacing rather than "more is better". Each buffer also needs a site, power, and a place in the clock or data path that repair must keep legal. the open flow reference

Hint: Ask which later stage can undo a bad macro placement.

Macros in the wrong place force long wires and pinch routing channels, and no amount of placement or routing effort recovers that. This is why a floorplan is reviewed before the flow is allowed to continue, and why macro placement is treated as a decision rather than an optimization. the open flow reference

Hint: Ask what each one buys, given the same design and the same tools.

Optimizing across block boundaries is strictly better, but runtime and memory grow faster than linearly, and a team cannot work on one flat database at once. Hierarchy buys parallel work and repeatability at the cost of the boundaries it freezes. the open flow reference

Hint: Ask what the top level needs to know about a finished block, and what it does not.

A block's insides are millions of objects the top level would only slow down on. An abstract LEF (Library Exchange Format) gives the shape and pins and write_timing_model the timing, so the top level treats it as a macro. the open flow reference

Hint: Ask what re-running the flow would cost, besides time.

Re-running from synthesis produces a different netlist and a different layout, so every check and every verification result starts again. An ECO (Engineering Change Order) touches a few cells and keeps the rest of the sign-off evidence valid, which is why closure ends in small edits. the open flow reference

Hint: Ask what a fix in one place does elsewhere.

Adding a buffer displaces neighbours, changes parasitics, and can create a new critical path. The flow therefore alternates repair and analysis rather than fixing everything at once, and a stage's result is only trusted after its own analysis has run. the open flow reference

Hint: Ask what each stage knows that the one before it did not.

Before placement there are no distances, after placement only straight lines, after global routing the regions, and only after detailed routing the real wires. Each step reveals cost the last one could not see, which is why margins are kept early and released late. the open flow reference

Hint: Ask which of the three is a delay and which two are requirements.

Clock-to-output is how long after the edge the register drives its new value, so it is part of the path delay. Setup and hold say how long the data must be stable before and after the edge, so they are subtracted from the budget. All three come from the library and vary with slew. the open flow reference

Hint: Ask whether adding flops makes failure impossible or merely unlikely.

A register that samples a changing input can sit between states, and it resolves after an unpredictable time. A second register gives it a full cycle to settle, which cuts the failure rate by orders of magnitude. The result is a mean time between failures, quoted in years, not a guarantee. the open flow reference

Hint: Slack is the margin at the current period. Ask how the two combine.

Slack already accounts for the setup time, the clock skew, and the uncertainty, so shrinking the period by the slack is what the design can take. Note that skew and uncertainty do not shrink with the period, so the estimate is optimistic if the clock is scaled a long way. report_clock_min_period computes it. the open flow reference

Hint: Draw the two edges. Ask how far apart they are.

The timer pairs each launch edge with the nearest following capture edge, so mixing edges halves the budget. Between clocks of different periods it does the same over their common multiple, which can produce a much tighter requirement than either period alone. the open flow reference

Hint: Both relax a check. Ask which one is still checked at all.

A false path claims the timing never matters, so nothing is reported and nothing is optimized. A multicycle path claims it matters later, so it is still checked, against a different edge. Using a false path where a multicycle would do hides real failures. the open flow reference

Hint: A latch is open for a while. Ask what late data can do in that window.

Because a latch is transparent rather than edge-triggered, data arriving after it opens flows on immediately, so the overrun is passed to the following stage rather than failing. It is paid back there, which is why the total across stages still has to fit and why set_max_time_borrow caps it. the open flow reference

Hint: Order them by how much metal and power they spend on skew.

An H-tree balances by construction and is cheap, but its skew depends on the loads matching. A mesh shorts the leaves together, so skew is very low and the power very high. A spine is the middle: a strong backbone with trees hanging off it. The choice follows the skew budget. the open flow reference

Hint: Ask what a deep tree costs, and what shallowness costs in return.

Latency itself cancels within a clock, so depth is not the enemy; what matters is skew, power, and how sensitive the tree is to variation. Deep trees accumulate variation, and shallow ones need strong drivers and long wires. Insertion delay also matters at a block's boundary, where it does not cancel. the open flow reference

Hint: Ask how far down the tree the saving reaches.

Everything below a disabled gate stops toggling, including the register clock pins, which is where most clock power sits. The costs are the gate's own area, a timing check on its enable, and a tree that is harder to balance because branches switch independently. the open flow reference

Hint: Ask what happens if a buffer's rise delay differs from its fall delay.

A pulse that starts at half the period can arrive much narrower, and a register needs a minimum high and low time to work. This is why clock cells are drawn with matched edges and why set_min_pulse_width is checked at the leaves. the open flow reference

Hint: The clock domains can be the same. Ask what differs instead.

If one register is released from reset while its neighbour is still held, the released one can capture a value that the other is about to change, which is the same hazard as a clock crossing. Reset domain crossing checks are a separate verification step, distinct from clock domain crossing. the open flow reference

Hint: Two names from two different files. Ask what each one varies.

Library corners such as slow-slow, typical-typical, and fast-fast come from the transistors' process, voltage, and temperature. Parasitic corners come from the metal's own variation and are chosen separately, which is why sign-off pairs them: a slow library with worst capacitance for setup, a fast one with best for hold. the open flow reference

Hint: The old rule is hot equals slow. Ask when that stops being true.

Two effects compete: carrier mobility falls with heat, which slows a cell, and the threshold voltage falls with heat, which speeds it. At low supply the threshold effect wins, so the worst case moves to cold. This is why a modern flow signs off at both temperature extremes rather than assuming hot is worst. the open flow reference

Hint: Ask what a single derate factor ignores about a path.

A long path averages out random variation, so a flat derate over-margins it, while a short path needs more. Advanced on-chip variation uses depth-dependent factors, parametric methods carry a distribution per cell, and Liberty variation data supplies the per-cell numbers. the open flow reference

Hint: Ask against what a glitch's size is judged.

A gate accepts anything below its low threshold as a zero and above its high threshold as a one; the unclaimed middle is the margin a glitch has to cross to matter. Margins shrink with the supply voltage, which is why noise became a first-class concern as voltages fell. the open flow reference

Hint: Ask what has to be true at the same time for coupling to hurt.

Each net has a range of times in which it can switch. If the windows cannot overlap, the aggressor cannot change the victim's delay, and a tool that ignored this would report impossible worst cases. Windows depend on timing, so the analysis iterates: timing changes windows, which changes delays. the open flow reference

Hint: Ask what makes a glitch harmful rather than merely present.

Combinational logic can pass a glitch along, and a register can latch one if it lands in the sampling window. On a clock or asynchronous pin it is worse, since those need no window at all. Glitches that harm nothing still cost power, which is a separate concern. the open flow reference

Hint: Ask what has to happen to the block's outputs and its state.

Gating the clock stops switching power; gating the supply also stops leakage, which dominates when a block is idle for long. The price is isolation cells on the outputs, retention flops for the state worth keeping, and a wake-up sequence that costs time and a current surge. the open flow reference

Hint: Ask where a tool gets it when no simulation has been run.

Switching power is proportional to it, so the number matters as much as the capacitance. Simulation gives real activity through a value-change dump or a switching-activity file; without one, a default is assumed at the inputs and propagated, which is an estimate only. the open flow reference

Hint: Ask what a net does when its inputs arrive at different times.

An unbalanced logic cone makes a gate switch several times before settling, and each transition costs a full charge and discharge. It can be a noticeable fraction of dynamic power in arithmetic logic, and it does not appear in a report that uses a single activity factor per net. the open flow reference

Hint: Leakage rises with temperature. Ask what dissipating it does next.

The feedback is real and, if the package cannot remove the heat, it runs away. It is one reason sign-off includes a hot corner and why leakage is controlled with threshold-voltage choice and power gating rather than treated as a fixed cost. the open flow reference

Hint: Ask what the router needs at each pin that legalization never checks.

A pin is reachable only from certain directions and through certain vias, and two cells side by side can block each other's access. This is why placement padding exists, why some cells are excluded from use, and why pin_access runs before detailed routing. the open flow reference

Hint: Ask what each part of the stack is for, given the same process.

Resistance falls with thickness, so long nets and the power grid go up the stack, while dense local routing stays on the thin, fine-pitch lower layers. This is the reason clocks are routed high, why the grid takes the top layers, and why layer assignment matters for delay. the open flow reference

Hint: Ask what a layer change costs, besides the wire on each side.

A via is a small plug of high-resistance metal, and a route that zigzags up and down the stack accumulates them. This is why routers prefer to stay on a layer, why via arrays are used on wide nets, and why via resistance appears in the extraction rules. the open flow reference

Hint: The macro's pins are usually on one edge. Ask what that implies for placement.

A pin edge facing away means every net wraps around the block, spending wire and congesting the channel behind it. The related choice is whether macros abut or leave a channel: abutted saves area, a channel leaves room for routing and buffers. the open flow reference

Hint: Two constraints from the same source: what the process can actually print.

The width of a FinFET (Fin Field-Effect Transistor) is a whole number of fins, so sizing moves in steps rather than smoothly. Below the wavelength limit a layer is printed with several masks, and shapes too close together must go on different ones, which the rules enforce as a coloring problem the router must respect. the open flow reference

Hint: Ask what happens to the other two when one is pushed.

A faster design uses bigger cells at lower threshold voltage, spending area and leakage; a smaller one is slower. The quality of a run is reported as worst and total negative slack, area, power, and the violation counts, and a team weighs them against the product's needs. the open flow reference

Hint: Ask which masks each one changes, and what that costs.

The transistor masks are the expensive ones, so designs scatter spare cells through the layout in advance; a late fix connects them with metal changes alone. An all-layer change can add real cells but needs the full mask set again. This is why spare cells are placed before anyone knows what will break. the open flow reference

Hint: Ask what each tool is optimized for, given the same design.

An implementation tool times millions of paths thousands of times, so it trades accuracy for speed; a sign-off timer does the opposite. Teams measure the gap and carry margin for it, which is exactly what SETUP_SLACK_MARGIN and its equivalents are for. the open flow reference

Hint: The block is designed alone but must fit a whole. Ask what it is given.

Someone has to decide how much of a cycle belongs inside the block and how much to the logic around it. That split becomes the block's constraints, and the top level assumes the block meets them. Budgets that do not add up are discovered late, at integration. the open flow reference

Hint: Ask what each fix does to the other check.

Adding buffers for hold slows the path, and if setup were already tight it fails again. Repair therefore runs setup first, and hold repair refuses to insert a buffer that would break setup unless told otherwise. Hold is also fixed late, when the clock tree and routing are real. the open flow reference

Hint: Ask how you would set a register deep inside a chip from outside it.

Controllability and observability are the problem: a fault deep in the logic cannot be excited or seen from the pins in normal operation. Chaining the registers into a shift register solves both, at the cost of a larger flop, the chain's wiring, and the test pins. the open flow reference

Hint: Ask what model that number counts against.

A fault model is a simplification: stuck-at assumes a node is welded to a value. Coverage counts modelled faults, not real defects, so a high number with a weak model still lets parts escape. Untestable logic, such as redundant gates, is why 100% is rare. the open flow reference

Hint: One kind of defect only shows up when the chip runs fast.

A resistive via or a weak transistor still passes a slow test but fails at frequency. Transition-fault patterns launch and capture in consecutive fast cycles, which is why the scan chains and the clocking must work at speed and why the test mode has its own timing constraints. the open flow reference

Hint: Ask what a chain of hundreds of registers does to the layout.

A chain stitched in netlist order wanders across the block, which is why scan_opt reorders it after placement to follow physical proximity. The scan enable is also a high-fanout net, usually treated as an ideal network until it is buffered. the open flow reference

Hint: Ask what the clock and the enables are doing during a shift.

During shift the data path is register to register through the scan inputs, usually at a slower clock, while functional paths are irrelevant. Capture cycles are at speed. Each mode is a separate set of constraints, which is what multi-mode analysis exists for. the open flow reference

Hint: Two blocks share one cycle. Ask what stops them each assuming the whole of it.

A path from a register in one block to a register in another crosses the boundary, and each side sees only its half. The budgets are the promise each side makes to the other, expressed as set_output_delay on one and set_input_delay on the other. the open flow reference

Hint: Ask where the clock that captures the data comes from.

Sending a clock alongside the data means the two travel the same path and see the same delay, so the interface survives a flight time far longer than a cycle. It is how fast off-chip interfaces work, and it is constrained against a virtual clock rather than the core's. the open flow reference

Hint: Ask what the top level can no longer see once a block is a model.

A model states the block's arrival and required times at its pins. If it was extracted with the wrong constraints or a different corner, the top level times against a fiction and closes on it. This is why models are regenerated whenever the block changes and are checked against the block's own analysis. the open flow reference

Hint: Ask what a top-level net does when a block sits in its way.

If a block occupies the space between two others, a connection either routes around it, which costs wire, or through it, which costs pins and a committed channel inside the block. Feedthroughs have to be planned when the block is built, since adding one later means rebuilding it. the open flow reference

1. floorplan and power grid
2. placement
3. clock tree synthesis
4. routing
5. parasitic extraction and sign-off timing

Hint: Each stage needs something the stage before it produced.

Nothing can be placed before there are rows and a grid, the clock tree needs the registers placed, routing needs the tree, and only a routed design has parasitics worth extracting. Each stage also re-times, which is why an early mistake is expensive. the open flow reference

1. detailed routing
2. metal fill
3. parasitic extraction
4. static timing analysis

Hint: One of these changes the capacitance the others measure.

Fill is added after routing, and it adds capacitance to the nets beside it. Extracting before the fill exists gives numbers that are too optimistic, so the order matters: route, fill, extract, then time. the open flow reference

1. a wire load model, from fanout alone
2. a placement-based estimate, from the distance between cells
3. a global route estimate, from the layers and the congestion
4. extracted parasitics from the detailed route

Hint: Each one knows something the one before it could only guess.

Each rung knows more about where the wire actually goes. This is why timing moves at every stage, why early numbers are optimistic, and why a design that closes only just at placement rarely closes after routing. the open flow reference