Games / Command flash cards / Standard-cell library / Sequential cells

Sequential cells

Each card shows a command to explain. A missed card returns later in the round and starts the schedule over. A card answered correctly moves up the schedule and next appears after 1, 3, 7, then 21 days. Keys 1 to 4 choose an option, h shows a hint, and Enter moves on. A hint keeps the card where it is on the schedule. An ordering card is answered by clicking its items in order, and one wrong click ends it. Time values are in nanoseconds. Progress is stored in this browser.

SourceThese cards describe standard-cell libraries in general, checked against the open libraries that OpenROAD-flow-scripts ships: Nangate45, sky130 high density, and ASAP7. Cell names and conventions differ between libraries, so each card says which library its example comes from. The answers link to the OpenROAD module that handles the cell in question. Reference: OpenROAD module documentation (the open libraries on GitHub).
All 8 cards in this section, with answers
  • DFF_X1 DFFR_X1 DFFS_X1 DFFRS_X1
    A plain flip-flop, then ones with asynchronous reset, set, and both.

    Hint: Read the letters after the flip-flop name as the extra pins.

    The letters are R for reset, S for set, and RS for both, all asynchronous. Such a pin acts without waiting for a clock edge, which is why it needs its own timing checks, recovery and removal, rather than setup and hold. Synchronous resets need no extra pin; they are logic in front of D. the open libraries reference

  • SDFF_X1 versus DFF_X1
    A scan flop: the same flip-flop plus a test input and a select.

    Hint: The extra pins exist for manufacturing test, not for the design's function.

    In test mode the select switches the flop to its scan input, and the flops form a shift register through which patterns are loaded and results read out. scan_replace swaps plain flops for these before placement, since they are larger. the open libraries reference

  • sky130_fd_sc_hd__dlxtp_1
    A latch: transparent while the clock is at its active level.

    Hint: Compare it with a flip-flop: one samples at an instant, the other over a window.

    It is level-sensitive, not edge-triggered: it passes data through while open, so a late signal can borrow time from the next stage instead of failing. That flexibility costs a harder timing analysis, so latches are used deliberately rather than inferred. the open libraries reference

  • CLKGATE_X1
    An integrated clock gate, which latches the enable first.

    Hint: Ask what would happen if the enable changed while the clock was high.

    Latching the enable is what stops the gated clock glitching. Gating with a plain AND lets a late enable chop a pulse in half, which can clock a register on a runt edge. The integrated cell latches the enable while the clock is low, so the gated output only ever has whole pulses. CLKGATETST_X1 adds a test enable that forces the clock on during scan. the open libraries reference

  • export CLUSTER_FLOPS = 1
    Uses multi-bit flops, where several bits share one clock pin.

    Hint: One cell, several bits. Ask which network benefits.

    Each clock pin is a sink the clock tree must drive, so folding four flops into one cell removes three sinks and the wire to them. The saving is in clock power and tree size; the cost is that the four bits must sit together. The library has to provide such cells. the open libraries reference

  • set_isolation and a retention flop in a switchable domain
    A flop that keeps its state while its domain's supply is off.

    Hint: Ask what has to survive when a domain's supply is switched off.

    An always-on supply feeds the small latch that holds it. Restoring state is faster and cheaper than recomputing it, so the flops worth keeping are given a small always-on latch inside. The isolation cells at the domain boundary are a different cell: they hold the domain's outputs at a defined value while it is off. the open libraries reference

  • DFF_X1 area 4.52 versus DLH_X1 area 2.66
    A flip-flop is two latches, so it costs about twice the area and power.

    Hint: One of the two contains the other, twice over.

    A master latch takes the data while the clock is low and a slave passes it on when the clock rises, which is what makes the cell edge-triggered. Latch-based designs trade that area and power saving for timing that is much harder to reason about. the open libraries reference

  • a flop with a feedback multiplexer, against a clock gate driving plain flops
    The multiplexer still clocks the flop; the gate stops the clock entirely.

    Hint: Both keep a value. Ask what the clock is doing in each case.

    Recirculating the output through a multiplexer holds the value but the register still toggles internally and still draws clock power. A clock gate shared across a bank of registers removes that power, which is why tools convert the one into the other during synthesis. the open libraries reference