Games / Command flash cards / Standard-cell library / Physical-only cells

Physical-only cells

The cards come in more than one shape: a command to explain, a description whose command you name, and steps to put in order. A missed card returns later in the round and starts the schedule over. A card answered correctly moves up the schedule and next appears after 1, 3, 7, then 21 days. Keys 1 to 4 choose an option, h shows a hint, and Enter moves on. A hint keeps the card where it is on the schedule. An ordering card is answered by clicking its items in order, and one wrong click ends it. Time values are in nanoseconds. Progress is stored in this browser.

SourceThese cards describe standard-cell libraries in general, checked against the open libraries that OpenROAD-flow-scripts ships: Nangate45, sky130 high density, and ASAP7. Cell names and conventions differ between libraries, so each card says which library its example comes from. The answers link to the OpenROAD module that handles the cell in question. Reference: OpenROAD module documentation (the open libraries on GitHub).
All 14 cards in this section, with answers
  • TAPCELL_X1
    A well tap: it ties the wells and substrate to the supplies.

    Hint: It has no logic pins. Ask what part of the transistor it is connecting.

    An untied well floats, which can let the parasitic structures in CMOS (Complementary Metal-Oxide-Semiconductor) latch up. Foundry rules therefore limit how far any transistor may be from a tap, and taps are inserted on a checkerboard at that pitch before placement. the open libraries reference

  • place_endcaps -endcap TAPCELL_X1
    Endcaps terminate each row so its wells and implants end legally.

    Hint: Ask what is special about the first and last cell of a row.

    A row that simply stops leaves its well and implant layers ending in mid-air, which breaks the rules about how those layers may end. The endcap provides a legal ending. It is inserted with the taps, before placement. the open libraries reference

  • FILLCELL_X1 FILLCELL_X2 FILLCELL_X4 FILLCELL_X8 FILLCELL_X16
    Fillers close the gaps so the rails and wells run unbroken.

    Hint: Several widths of the same thing. Ask what has to be continuous along a row.

    Several widths exist so any gap is filled exactly, widest first. A filler carries the power and ground rails and the well and implant layers across the gap, without which the row is not manufacturable. They go in after routing-affecting steps, and remove_fillers clears them if something must change. the open libraries reference

  • sky130_fd_sc_hd__decap_8
    A decoupling capacitor, which stores charge across the supplies.

    Hint: It also fills a gap, but it does something electrical as well.

    It fills a gap like a filler, and adds capacitance. When many cells switch at once, the grid cannot deliver current fast enough and the local supply dips. A decap sits beside them holding charge to supply that moment. It costs leakage, so flows place them where switching is heaviest rather than everywhere. the open libraries reference

  • ANTENNA_X1
    A diode that bleeds off charge collected by long metal during etching.

    Hint: The damage it prevents happens during manufacturing, not in use.

    While a layer is etched, metal connected to a gate accumulates charge that can break the thin oxide. A diode gives that charge a path to the substrate. repair_antennas inserts them after routing, where the check finds violations. Protection at the pins is a different cell, in the pad library. the open libraries reference

  • LOGIC0_X1 and LOGIC1_X1
    Tie cells, which drive a constant 0 or 1 through a transistor.

    Hint: Ask why an input that needs a constant is not simply wired to a rail.

    Wiring a gate input straight to a rail exposes its thin oxide to the full supply and to any damage the rail collects. A tie cell drives the constant through a transistor instead. repair_tie_fanout gives each load its own copy so the constant nets stay short. sky130 combines both polarities in one cell, conb_1. the open libraries reference

  • set_level_shifter -domain PD_CORE
    A cell that passes a signal between domains at different supply voltages.

    Hint: It sits between two domains, and what differs between them is not the clock.

    A signal driven at a low supply may not register fully at a higher one, and can leave the receiving gate partly on, burning current. A shifter re-drives it at the receiving domain's supply. It needs both supplies, so it is placed at the boundary. the open libraries reference

  • place_tapcells -distance 20
    How far any transistor may be from a tie to its well, to prevent latch-up.

    Hint: The rule behind this number is about the wells, not about timing.

    Wells and substrate must be held at a fixed voltage. If they float, the parasitic structures between them can turn on and short the supply, which destroys the chip. The foundry gives a maximum distance, and tap cells are placed in rows at that spacing before anything else. the open libraries reference

  • a scattering of unused gates and flops, placed before tapeout
    Cells left in the layout so a late fix can be made in metal alone.

    Hint: Ask what a late fix can do if the transistor masks are already made.

    Rewiring existing gates changes only the metal masks, which is far cheaper than a new mask set. Teams therefore scatter a mix of gates and registers across the die in advance, accepting the wasted area and leakage as insurance. What is left unused is tied off. the open libraries reference

  • FILLCELL_X4 versus a decoupling capacitor cell
    Both continue the rows, but one also adds capacitance across the supply.

    Hint: Both fill a gap in a row. Ask what one of them adds.

    A gap in a row breaks the continuity of the wells and implant layers, so something must fill it. A decoupling cell fills the same gap with a transistor wired as a capacitor, which supplies charge locally when nearby cells switch. It leaks, so it is used where the supply needs it. the open libraries reference

  • Placement has left gaps between cells in a row. The wells and implant layers must run unbroken from one end of the row to the other.
    FILLCELL_X4

    Hint: The gap needs occupying, not connecting.

    Filler cells carry no logic and no pins beyond the rails; they exist to keep the row continuous. A well tap ties the wells to a voltage and is placed on a spacing rule instead, and a diode and a tie cell both connect to something. the open libraries reference

  • An unused input must sit permanently at logic one, and the rules forbid wiring a gate input straight to the supply rail.
    LOGIC1_X1

    Hint: Something has to stand between the rail and the gate.

    A tie cell drives a constant through a transistor, which protects the gate from the rail during manufacturing and gives the net a real driver for the checks. A buffer would work electrically but costs more and needs an input of its own. the open libraries reference

  • A long metal wire collected charge during etch, and the gate at the end of it needs somewhere for that charge to go.
    ANTENNA_X1

    Hint: The fix is a device that conducts to the substrate.

    A diode bleeds the accumulated charge away before it can damage the thin gate oxide. The alternative fix is to break the long wire with a jump to another layer. A decoupling cell is also a capacitor to the rails, but it protects the supply, not a gate. the open libraries reference

  • Put these steps in the order a flow performs them.
    1. place well taps and endcaps
    2. place the standard cells
    3. insert antenna diodes
    4. insert filler

    Hint: One of them can only be judged once the wires exist.

    Taps and endcaps are placed on the empty floorplan, since everything else has to fit around them. Diodes come after routing, because only then is it known which wires are too long. Filler is last, once nothing else will move. the open libraries reference