Games / Command flash cards / Standard-cell library / Combinational cells

Combinational cells

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SourceThese cards describe standard-cell libraries in general, checked against the open libraries that OpenROAD-flow-scripts ships: Nangate45, sky130 high density, and ASAP7. Cell names and conventions differ between libraries, so each card says which library its example comes from. The answers link to the OpenROAD module that handles the cell in question. Reference: OpenROAD module documentation (the open libraries on GitHub).
All 9 cards in this section, with answers
  • NAND2_X1 versus AND2_X1
    The AND is a NAND with an inverter after it, so it is larger and slower.

    Hint: Ask what a CMOS (Complementary Metal-Oxide-Semiconductor) gate does naturally.

    Static CMOS (Complementary Metal-Oxide-Semiconductor) logic naturally builds inverting gates: a pull-up network of p-type transistors and a pull-down of n-type. Every non-inverting gate is an inverting one plus an inverter. This is why synthesis prefers NAND, NOR, and the compound inverting gates. the open libraries reference

  • AOI21_X1
    And-Or-Invert: it computes not of (A1 and A2) or B.

    Hint: Read the name as the operations in order, and the digits as input counts.

    The digits give the input counts of each group, here a two-input AND feeding an OR with one more input, all inverted. Such a compound gate is one CMOS (Complementary Metal-Oxide-Semiconductor) stage, so it is smaller and faster than the gates it replaces. OAI21 is the same shape with the operations swapped. the open libraries reference

  • BUF_X4 versus two INV_X4 in series
    One characterized cell, usually smaller and faster than the pair.

    Hint: Both are non-inverting. Ask what the library can do that the netlist cannot.

    Two inverters in series do the same job. A buffer is drawn as two stages, but its internal stage is sized for the output stage rather than being a general-purpose cell, and the pair is characterized as one. Repair and clock tree synthesis use buffers where polarity must be preserved and inverter pairs where it must not. the open libraries reference

  • MUX2_X1
    A two-input multiplexer as one cell rather than three gates.

    Hint: Ask why a library would provide it when AND, OR, and NOT already exist.

    It is smaller than the gates that would build it. Selection is so common (enables, bypasses, scan) that libraries provide it as a transmission-gate or compound cell, which is smaller and faster than the three gates it replaces. Clock multiplexing uses a dedicated glitch-free cell, not this one. the open libraries reference

  • HA_X1 and FA_X1
    A half adder, with no carry in, and a full adder, which takes one.

    Hint: Two adder cells. Ask what the second has that the first does not.

    Adders are built from these cells in a chain or a tree, so libraries provide them drawn compactly rather than leaving synthesis to assemble them from gates. The architecture of the chain is what SWAP_ARITH_OPERATORS changes in the flow. the open libraries reference

  • sky130_fd_sc_hd__ebufn_2
    A tristate buffer, whose output can be released to high impedance.

    Hint: Its output has a third state besides 0 and 1.

    Releasing the output lets several drivers share one net, one at a time. Timing tools treat such a net carefully, since it has no driver at all in some states, and physical verification checks that two drivers can never be enabled together. the open libraries reference

  • NAND2_X1 versus NOR2_X1
    The first is preferred, since stacking the slower transistors hurts more.

    Hint: Think about which transistors end up in series in each one.

    In a not-and gate the parallel transistors are the pull-up ones, which are the weaker type and benefit most from being in parallel. In a not-or gate they are stacked, so the gate must be made wide to match. Libraries therefore offer stronger and cheaper not-and cells, and synthesis maps toward them. the open libraries reference

  • NAND2_X1 NAND3_X1 NAND4_X1 ... and no NAND8
    A deeper stack is slower, so wide gates are built from smaller ones.

    Hint: Ask what happens to the transistors in series as the input count grows.

    Each transistor added in series adds resistance and adds its own capacitance to the internal nodes, so delay grows faster than linearly. Beyond about four the tool is better off building a tree of smaller gates, which is why libraries stop there. the open libraries reference

  • AOI21_X1 instead of AND2_X1 + NOR2_X1
    One inverting cell does the job of two, with less delay and area.

    Hint: Count the gates the signal passes through in each version.

    Inverting logic is what the transistors naturally build, so an and-or-invert cell is a single stage rather than two. Synthesis leans on these heavily, and the inversions it introduces are absorbed by the cells around them or by swapping a cell for its complement. the open libraries reference