Games / Command flash cards / Standard-cell library / Clock cells

Clock cells

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SourceThese cards describe standard-cell libraries in general, checked against the open libraries that OpenROAD-flow-scripts ships: Nangate45, sky130 high density, and ASAP7. Cell names and conventions differ between libraries, so each card says which library its example comes from. The answers link to the OpenROAD module that handles the cell in question. Reference: OpenROAD module documentation (the open libraries on GitHub).
All 5 cards in this section, with answers
  • CLKBUF_X1 versus BUF_X1
    A clock buffer, drawn so its rise and fall delays match closely.

    Hint: The clock cares about something the data path mostly does not.

    A chain of unbalanced buffers slowly distorts the duty cycle, which eats the high or low pulse width the registers need. Clock cells are drawn to keep the two edges symmetric, and clock tree synthesis is given only those cells to build with. the open libraries reference

  • sky130_fd_sc_hd__clkinvlp_2
    A low-power clock inverter, traded against speed.

    Hint: The letters before the drive strength say what it is optimized for.

    The clock switches every cycle and reaches every register, so it is often the largest single consumer of dynamic power. A library that offers lower-power clock cells lets the tree use them where the extra delay is affordable. the open libraries reference

  • sky130_fd_sc_hd__dlygate4sd1_1
    A delay cell: it passes the signal through and adds a controlled delay.

    Hint: Its function is the identity. Ask what it is bought for.

    Hold repair needs delay without drive, and a buffer adds too little for its area. Delay cells give a predictable amount per cell. The dlymetal family in the same library gets its delay from long internal wires instead of gates. the open libraries reference

  • CLKBUF_X1 characterized with matched rise and fall delays
    Matched edges keep the duty cycle from drifting along the tree.

    Hint: Ask what happens to a pulse after twenty unmatched stages.

    If a cell's rising delay differs from its falling one, every stage shifts one edge relative to the other and the high phase shrinks. After a deep tree the pulse can be too narrow for the registers at the leaves, which is what the minimum pulse width check catches. the open libraries reference

  • a tree of clock inverters, against a tree of clock buffers
    Inverters give the same tree with half the stages, so sharper edges.

    Hint: A buffer is two inverters. Ask what that costs at every level.

    Since a buffer is a pair of inverters, building with inverters halves the number of stages for the same drive, which means less accumulated variation and a cleaner edge. The tree must then have an even number of levels to every leaf, or the registers see opposite phases. the open libraries reference