All sections

Hint: Same function four times. Ask what differs, and what it costs.

The suffix scales the transistor widths, so a higher number drives more load in less time while using more area, more input capacitance, and more leakage. Sizing during repair mostly means moving along this series. These names are Nangate45; sky130 writes the same idea as inv_1, inv_2, inv_4. the open libraries reference

Hint: Read the parts around the function: who made it, for what, and how tall.

A long name usually encodes the foundry, the library family, and the row height as well as the function. In sky130_fd_sc_hd, sc is standard cell and hd high density. In ASAP7, 75t is the row height in tracks and the trailing letter is the threshold-voltage flavour. the open libraries reference

Hint: Two flavours of the same transistor. Ask what is traded between them.

Leakage is traded for speed. A lower threshold voltage switches faster and leaks more, at the same supply and area. A flow offers several flavours so optimization can spend leakage only on the paths that need the speed. ASAP7 ships regular, low, and super-low. the open libraries reference

Hint: Two libraries, one process. Ask what differs physically between them.

The tall variant is the fast one: a taller row gives wider transistors, so a high-speed library is faster and larger than a high-density one at the same drive strength. A design picks one as its main library. Mixing them is possible only if the row heights are compatible. the open libraries reference

Hint: Ask what a CMOS (Complementary Metal-Oxide-Semiconductor) gate does naturally.

Static CMOS (Complementary Metal-Oxide-Semiconductor) logic naturally builds inverting gates: a pull-up network of p-type transistors and a pull-down of n-type. Every non-inverting gate is an inverting one plus an inverter. This is why synthesis prefers NAND, NOR, and the compound inverting gates. the open libraries reference

Hint: Read the name as the operations in order, and the digits as input counts.

The digits give the input counts of each group, here a two-input AND feeding an OR with one more input, all inverted. Such a compound gate is one CMOS (Complementary Metal-Oxide-Semiconductor) stage, so it is smaller and faster than the gates it replaces. OAI21 is the same shape with the operations swapped. the open libraries reference

Hint: Both are non-inverting. Ask what the library can do that the netlist cannot.

Two inverters in series do the same job. A buffer is drawn as two stages, but its internal stage is sized for the output stage rather than being a general-purpose cell, and the pair is characterized as one. Repair and clock tree synthesis use buffers where polarity must be preserved and inverter pairs where it must not. the open libraries reference

Hint: Ask why a library would provide it when AND, OR, and NOT already exist.

It is smaller than the gates that would build it. Selection is so common (enables, bypasses, scan) that libraries provide it as a transmission-gate or compound cell, which is smaller and faster than the three gates it replaces. Clock multiplexing uses a dedicated glitch-free cell, not this one. the open libraries reference

Hint: Two adder cells. Ask what the second has that the first does not.

Adders are built from these cells in a chain or a tree, so libraries provide them drawn compactly rather than leaving synthesis to assemble them from gates. The architecture of the chain is what SWAP_ARITH_OPERATORS changes in the flow. the open libraries reference

Hint: Read the letters after the flip-flop name as the extra pins.

The letters are R for reset, S for set, and RS for both, all asynchronous. Such a pin acts without waiting for a clock edge, which is why it needs its own timing checks, recovery and removal, rather than setup and hold. Synchronous resets need no extra pin; they are logic in front of D. the open libraries reference

Hint: The extra pins exist for manufacturing test, not for the design's function.

In test mode the select switches the flop to its scan input, and the flops form a shift register through which patterns are loaded and results read out. scan_replace swaps plain flops for these before placement, since they are larger. the open libraries reference

Hint: Compare it with a flip-flop: one samples at an instant, the other over a window.

It is level-sensitive, not edge-triggered: it passes data through while open, so a late signal can borrow time from the next stage instead of failing. That flexibility costs a harder timing analysis, so latches are used deliberately rather than inferred. the open libraries reference

Hint: Ask what would happen if the enable changed while the clock was high.

Latching the enable is what stops the gated clock glitching. Gating with a plain AND lets a late enable chop a pulse in half, which can clock a register on a runt edge. The integrated cell latches the enable while the clock is low, so the gated output only ever has whole pulses. CLKGATETST_X1 adds a test enable that forces the clock on during scan. the open libraries reference

Hint: The clock cares about something the data path mostly does not.

A chain of unbalanced buffers slowly distorts the duty cycle, which eats the high or low pulse width the registers need. Clock cells are drawn to keep the two edges symmetric, and clock tree synthesis is given only those cells to build with. the open libraries reference

Hint: The letters before the drive strength say what it is optimized for.

The clock switches every cycle and reaches every register, so it is often the largest single consumer of dynamic power. A library that offers lower-power clock cells lets the tree use them where the extra delay is affordable. the open libraries reference

Hint: Its function is the identity. Ask what it is bought for.

Hold repair needs delay without drive, and a buffer adds too little for its area. Delay cells give a predictable amount per cell. The dlymetal family in the same library gets its delay from long internal wires instead of gates. the open libraries reference

Hint: It has no logic pins. Ask what part of the transistor it is connecting.

An untied well floats, which can let the parasitic structures in CMOS (Complementary Metal-Oxide-Semiconductor) latch up. Foundry rules therefore limit how far any transistor may be from a tap, and taps are inserted on a checkerboard at that pitch before placement. the open libraries reference

Hint: Ask what is special about the first and last cell of a row.

A row that simply stops leaves its well and implant layers ending in mid-air, which breaks the rules about how those layers may end. The endcap provides a legal ending. It is inserted with the taps, before placement. the open libraries reference

Hint: Several widths of the same thing. Ask what has to be continuous along a row.

Several widths exist so any gap is filled exactly, widest first. A filler carries the power and ground rails and the well and implant layers across the gap, without which the row is not manufacturable. They go in after routing-affecting steps, and remove_fillers clears them if something must change. the open libraries reference

Hint: It also fills a gap, but it does something electrical as well.

It fills a gap like a filler, and adds capacitance. When many cells switch at once, the grid cannot deliver current fast enough and the local supply dips. A decap sits beside them holding charge to supply that moment. It costs leakage, so flows place them where switching is heaviest rather than everywhere. the open libraries reference

Hint: The damage it prevents happens during manufacturing, not in use.

While a layer is etched, metal connected to a gate accumulates charge that can break the thin oxide. A diode gives that charge a path to the substrate. repair_antennas inserts them after routing, where the check finds violations. Protection at the pins is a different cell, in the pad library. the open libraries reference

Hint: Ask why an input that needs a constant is not simply wired to a rail.

Wiring a gate input straight to a rail exposes its thin oxide to the full supply and to any damage the rail collects. A tie cell drives the constant through a transistor instead. repair_tie_fanout gives each load its own copy so the constant nets stay short. sky130 combines both polarities in one cell, conb_1. the open libraries reference

Hint: Three files for one library. Ask which stage of the flow needs each.

The three views are timing and power, geometry, and layout. A flow reads the Liberty file to time, the LEF (Library Exchange Format) file to place and route, and merges the layout only at the end. The three must agree: a cell missing from one of them fails in whichever stage needs it. the open libraries reference

Hint: One library, three files. Ask what differs, and why one is not enough.

The conditions are process, voltage, and temperature. Silicon varies, so a cell's delay is measured at several of them and the design must work at all of them. Setup is usually worst in the slow corner and hold in the fast one, which is why sign-off analyses several corners rather than picking one. the open libraries reference

Hint: These are not measurements. Ask who has to obey them.

Beyond these values a cell's delay tables are extrapolated and its behaviour is not guaranteed. repair_design fixes violations by buffering or upsizing, and the SDC (Synopsys Design Constraints) commands set_max_transition and set_max_capacitance can tighten the limits further, never relax them. the open libraries reference

Hint: It is the unit that rows and cell widths are built from.

Every standard cell is one site high (or a whole multiple, for multi-height cells) and a whole number of sites wide. That is what makes rows and legalization possible, and it is why a library belongs to a site rather than to a process alone. the open libraries reference

Hint: One cell, several bits. Ask which network benefits.

Each clock pin is a sink the clock tree must drive, so folding four flops into one cell removes three sinks and the wire to them. The saving is in clock power and tree size; the cost is that the four bits must sit together. The library has to provide such cells. the open libraries reference

Hint: Ask what has to survive when a domain's supply is switched off.

An always-on supply feeds the small latch that holds it. Restoring state is faster and cheaper than recomputing it, so the flops worth keeping are given a small always-on latch inside. The isolation cells at the domain boundary are a different cell: they hold the domain's outputs at a defined value while it is off. the open libraries reference

Hint: Its output has a third state besides 0 and 1.

Releasing the output lets several drivers share one net, one at a time. Timing tools treat such a net carefully, since it has no driver at all in some states, and physical verification checks that two drivers can never be enabled together. the open libraries reference

Hint: It sits between two domains, and what differs between them is not the clock.

A signal driven at a low supply may not register fully at a higher one, and can leave the receiving gate partly on, burning current. A shifter re-drives it at the receiving domain's supply. It needs both supplies, so it is placed at the boundary. the open libraries reference

Hint: The cells exist and work. Ask what else makes a cell a poor choice.

A tall compound gate can have pins that the router struggles to reach, and a weak cell can be chosen too readily by sizing. Flows exclude such cells outright rather than repair the results. Nangate45's flow configuration excludes AOI211_X1 and OAI211_X1 for exactly this. the open libraries reference

Hint: Three things get worse when you take the stronger cell. Name the one that is not area.

Wider transistors switch more current, but they also have larger gates, so the previous stage sees a bigger load. Upsizing a cell can therefore push the problem one stage back, which is why repair sizes along a path rather than one cell at a time. the open libraries reference

Hint: Rows are one site high. Ask what a cell twice that height needs.

Rows alternate orientation so that neighbouring rows share their power and ground rails. A cell spanning two rows has to match that pattern, which is why legalizers list mixed-height support as a feature, and why initialize_floorplan takes extra sites for cells that appear later. the open libraries reference

Hint: Two axes. Ask what the tool does when a real value lands between them.

Values between the grid points are interpolated. A cell's delay depends mostly on how fast its input arrives and how much it has to drive, so it is characterized on that grid and interpolated in between. report_dcalc prints the lookup for one arc, which is the way to see it happen. the open libraries reference

Hint: Divide the cell height by the routing pitch and see what the name says.

Nangate45 cells are ten tracks tall and the ASAP7 library says 7.5 in its name. A shorter cell packs more logic into the same area but has less room for wide transistors, so it is slower and harder to route inside. A library is chosen partly on this number. the open libraries reference

Hint: The cells do the same thing. Ask what does not carry across.

An output may be Z, ZN, Y, or X, and inputs may be A and B or A1 and A2. A script that hardcodes a pin name works on one library and fails on the next, which is why flows query the library instead, with commands such as get_pins or the library cell reports. the open libraries reference

Hint: One function appears many times over. Ask along which axes.

A library is a grid of choices: function by drive strength, and in a modern library by threshold voltage as well. Corners do not multiply the cell count, since they are separate Liberty files over the same cells. A production library runs to a thousand cells or more. the open libraries reference

Hint: Think about which transistors end up in series in each one.

In a not-and gate the parallel transistors are the pull-up ones, which are the weaker type and benefit most from being in parallel. In a not-or gate they are stacked, so the gate must be made wide to match. Libraries therefore offer stronger and cheaper not-and cells, and synthesis maps toward them. the open libraries reference

Hint: Ask what happens to the transistors in series as the input count grows.

Each transistor added in series adds resistance and adds its own capacitance to the internal nodes, so delay grows faster than linearly. Beyond about four the tool is better off building a tree of smaller gates, which is why libraries stop there. the open libraries reference

Hint: Count the gates the signal passes through in each version.

Inverting logic is what the transistors naturally build, so an and-or-invert cell is a single stage rather than two. Synthesis leans on these heavily, and the inversions it introduces are absorbed by the cells around them or by swapping a cell for its complement. the open libraries reference

Hint: One of the two contains the other, twice over.

A master latch takes the data while the clock is low and a slave passes it on when the clock rises, which is what makes the cell edge-triggered. Latch-based designs trade that area and power saving for timing that is much harder to reason about. the open libraries reference

Hint: Both keep a value. Ask what the clock is doing in each case.

Recirculating the output through a multiplexer holds the value but the register still toggles internally and still draws clock power. A clock gate shared across a bank of registers removes that power, which is why tools convert the one into the other during synthesis. the open libraries reference

Hint: Ask what happens to a pulse after twenty unmatched stages.

If a cell's rising delay differs from its falling one, every stage shifts one edge relative to the other and the high phase shrinks. After a deep tree the pulse can be too narrow for the registers at the leaves, which is what the minimum pulse width check catches. the open libraries reference

Hint: A buffer is two inverters. Ask what that costs at every level.

Since a buffer is a pair of inverters, building with inverters halves the number of stages for the same drive, which means less accumulated variation and a cleaner edge. The tree must then have an even number of levels to every leaf, or the registers see opposite phases. the open libraries reference

Hint: The rule behind this number is about the wells, not about timing.

Wells and substrate must be held at a fixed voltage. If they float, the parasitic structures between them can turn on and short the supply, which destroys the chip. The foundry gives a maximum distance, and tap cells are placed in rows at that spacing before anything else. the open libraries reference

Hint: Ask what a late fix can do if the transistor masks are already made.

Rewiring existing gates changes only the metal masks, which is far cheaper than a new mask set. Teams therefore scatter a mix of gates and registers across the die in advance, accepting the wasted area and leakage as insurance. What is left unused is tied off. the open libraries reference

Hint: Both fill a gap in a row. Ask what one of them adds.

A gap in a row breaks the continuity of the wells and implant layers, so something must fill it. A decoupling cell fills the same gap with a transistor wired as a capacitor, which supplies charge locally when nearby cells switch. It leaks, so it is used where the supply needs it. the open libraries reference

Hint: Ask what a higher threshold does to speed, and what it does to leakage.

Leakage falls roughly exponentially with threshold voltage while delay rises gently, so swapping the cells off the critical path is close to free. Flows do this as a late pass, and the reverse swap is a way to recover a small amount of timing. the open libraries reference

Hint: The bigger cell drives more. Ask what it does to whatever drives it.

Input capacitance grows with drive strength, so the delay moves upstream rather than disappearing. Sizing helps when the cell is genuinely overloaded and stops helping once the load is mostly the gate that drives it, which is why repair sizes a whole path rather than one cell. the open libraries reference

Hint: There is an optimum, and it is not the biggest possible step.

A larger step per stage needs fewer stages but each is slower; a smaller step is quick per stage but needs more of them. The total is flat near a ratio of about four, which is why buffer trees are built that way and why driving a huge load from one cell is always wrong. the open libraries reference

Hint: Wire delay grows with the square of the length.

The resistance and the capacitance of a wire both scale with its length, so its delay scales with the square. Two halves cost two quarters plus the buffer. Sizing the driver fights the resistance of the whole wire and runs out of benefit quickly, which is why repair buffers long nets. the open libraries reference

Hint: Ask what could be changed without moving anything else.

A threshold voltage swap is the clearest case: the cells are drawn to the same footprint on purpose, so the change touches no metal at all. Where the replacement is wider, everything to the right of it has to move, which is why late sizing is constrained to what fits. the open libraries reference

Hint: Ask what happens to a cell asked to work outside these numbers.

Inside the grid the values are interpolated between measured points. Outside it, they are extrapolated, and the further out the worse. This is the real reason behind the maximum transition and maximum capacitance limits: past them, nobody knows the delay. the open libraries reference

Hint: The views are built by different teams and different tools.

A pin present in the timing view and missing in the abstract, or an abstract whose size disagrees with the layout, breaks the flow far downstream and in confusing ways. This is why a library is checked view against view before any design uses it. the open libraries reference

Hint: The gap needs occupying, not connecting.

Filler cells carry no logic and no pins beyond the rails; they exist to keep the row continuous. A well tap ties the wells to a voltage and is placed on a spacing rule instead, and a diode and a tie cell both connect to something. the open libraries reference

Hint: Something has to stand between the rail and the gate.

A tie cell drives a constant through a transistor, which protects the gate from the rail during manufacturing and gives the net a real driver for the checks. A buffer would work electrically but costs more and needs an input of its own. the open libraries reference

Hint: The fix is a device that conducts to the substrate.

A diode bleeds the accumulated charge away before it can damage the thin gate oxide. The alternative fix is to break the long wire with a jump to another layer. A decoupling cell is also a capacitor to the rails, but it protects the supply, not a gate. the open libraries reference

1. place well taps and endcaps
2. place the standard cells
3. insert antenna diodes
4. insert filler

Hint: One of them can only be judged once the wires exist.

Taps and endcaps are placed on the empty floorplan, since everything else has to fit around them. Diodes come after routing, because only then is it known which wires are too long. Filler is last, once nothing else will move. the open libraries reference