Placement

A large empty die with the cells gathered into a loose cloud in the middle, occupying maybe a third of the area, with wide empty margins.

The placer did its job: with a utilization target of 8 percent it spread the design as evenly as its density constraint allowed, and it still cannot fill the die. Empty silicon is not free, because every net grows with it. This run routes 69 percent more wire than the same design on a sensible floorplan.

On the left, cells in a loose cloud with wide empty margins. On the right, cells filling the core evenly from edge to edge.

Even fill means short nets and predictable congestion. The loose one wastes area and lengthens every connection, and the cost lands on timing before it lands on power. There is a limit in the other direction too: packed past about 80 percent, repair runs out of room to insert anything.

Rows packed end to end with almost no gaps, like a brick wall, filling the whole core.

This is 92 percent utilization. Repair buffers, hold fixes, and late engineering changes all need free sites, and at this density there are none nearby, so the legalizer has to push cells around to make space. Most flows aim for 60 to 80 percent for exactly this reason. The clock tree and the grid live above the cells and are not the constraint.

Cells gathered in a loose cloud in the middle and upper left, with the right-hand fifth of the die and the top-left corner completely bare.

Empty silicon is paid for twice: once in area, and again in the wire needed to cross it. The placer is not at fault here, since it spread the design as evenly as its density target allowed. The floorplan is what needs changing, and the give-away is that the empty space is at the edges rather than in pockets.

A dense field of cells with darker bands weaving between clusters of roughly equal size, repeating across the block, and pins along all four edges.

This cipher is built from identical parallel units, and the placer keeps each one together because the connectivity inside a unit is far denser than between them. The same pattern appears in this design's congestion map, which is the useful part: architecture shows up in more than one view, and recognizing it stops you hunting for a fault that is not there.

Standard cells fill most of the core. Two tall rectangles sit near the bottom corners, each one surrounded by empty black space with a dashed line running through it, and the cells stop at that line rather than at the rectangle.

The macro placer was given a halo of 22.4 by 15.12 micrometres and treats it as part of the macro. The cost is easy to underrate. These two macros are 2481 square micrometres of silicon and 11928 square micrometres once the halos are counted, which is close to five times the area, on a block whose whole design area is 55855 square micrometres. What it buys is room at the macro edge, where every one of the macro's connections has to land, and a strip of quiet routing for nets that pass by. A floorplan that looks wasteful around its macros is usually paying that bill on purpose. The halo is a knob, not a law, and shrinking it is a normal thing to try.

Cells cover most of the die in a ragged blob, thinning out towards the bottom right, where a wedge of the core is left bare. Pins run along all four edges.

A placer minimizes wire length and pays a penalty only when a region gets too dense. At 51 percent utilization that penalty almost never bites, so the cells gather wherever the connectivity pulls them and the ground nobody needs stays bare. Compare it with the block on the oversized die, where the design sits in a small cloud in the middle and every net is longer for it. The difference is not how square the blob looks, it is what the shape cost: this run wired 262811 micrometres, overflowed no layer, and finished with zero routing violations. If you wanted the fill even you could ask for it, and you would pay in wire.

Rows of outlined cells across the core, broken by black gaps of every size, including one wide one near the middle.

The placement view switches off physical cells on purpose, and that is the more useful picture. What you see is the design, and what you do not see is the slack: the black is free row space, which is where repair buffers, hold fixes and any late change have to fit. This block is 76 percent utilized, so a quarter of the rows are open and there is room almost everywhere. Hold that against the Skywater block in this drill, which looks like a brick wall because at 92 percent it nearly is, and has almost nowhere left to put anything.

The left one has black gaps of every size between the cells. The right one is a brick wall with hardly a gap in it.

Both views leave the fill cells out, so the black is honest free row space and the comparison is fair even across two processes, because what you are reading is a fraction and not a size. The left block is 76 percent utilized and has open sites almost everywhere. The right is 92 percent, and a buffer that has to go in at a particular place has nowhere near it to go, so the legalizer starts shoving neighbours along the row to make space, which moves cells that were fine where they were. Density is not only an area number. It is how much freedom every later stage has.