Every map

Almost the whole core is orange, the level just below the top of the scale, with a green margin around the edge and a handful of isolated green tiles inside.

Uniform heat across an entire core, rather than a hotspot, points at capacity rather than at any one part of the design: every tile lost the same fraction of its tracks. This run was held to metal1 through metal3 out of ten. A placement problem shows as a hot region, not a hot core.

Mostly green and olive, with four small deep-red tiles: one left of centre, one right of centre, one near the top, and one below the middle.

A handful of tiles at capacity in an otherwise green map is the normal state of a routed design, not a problem. They are where several nets had to cross the same boundary, and the detailed router resolves them by detouring. What matters is whether they cluster: four scattered tiles route, a solid red region does not.

A regular grid of dark red blobs, roughly sixteen of them in rows and columns, separated by green channels, over an orange background.

This cipher is built from identical parallel units, and the placer kept each one together because their internal connectivity is dense. The green channels between them are where almost nothing crosses. Structure in a congestion map is usually the architecture, and it is a sign the placer understood the design rather than a fault to fix.

Two maps of similar shape: a cool band at the top, a dark red region through the middle, and warmer colours below. Their colour legends read up to 3.698 millivolts on the left and 13.921 on the right.

They look alike because each map normalizes its colours to its own range, so the worst region is always dark red whatever the numbers are. The legends differ by nearly four times: 3.7 millivolts against 13.9. Read the scale before reacting to the colour, on this map and on every other one a tool draws.

A gradient from a cool band along the top to a dark red region filling the right and centre of the middle, with orange along the bottom.

The drop grows with distance from where the current enters, so the worst place is the area furthest from the straps that feed it, not the area with the most cells. Fixing it means getting metal closer to that region: more straps, wider ones, or a connection from another direction.

A large empty die with the cells gathered into a loose cloud in the middle, occupying maybe a third of the area, with wide empty margins.

The placer did its job: with a utilization target of 8 percent it spread the design as evenly as its density constraint allowed, and it still cannot fill the die. Empty silicon is not free, because every net grows with it. This run routes 69 percent more wire than the same design on a sensible floorplan.

On the left, cells in a loose cloud with wide empty margins. On the right, cells filling the core evenly from edge to edge.

Even fill means short nets and predictable congestion. The loose one wastes area and lengthens every connection, and the cost lands on timing before it lands on power. There is a limit in the other direction too: packed past about 80 percent, repair runs out of room to insert anything.

A single root entering from the left, splitting into four coloured branches, each one serving a quarter of the block: red at the top left, yellow at the top right, orange at the bottom left, green at the bottom right.

Bisecting the sink region and balancing the halves is what produces this shape, and the colours are the branches the tool built. A mesh would cover the block in a grid and cost far more power; a spine would show one heavy trunk. The structure is worth recognizing because it tells you immediately whether the tool balanced by region, which is what keeps skew low.

On the left, four short balanced branches, one per quarter of the block. On the right, two long branches wandering across the block, with more turns and longer runs between splits.

The right-hand run was told to place a buffer every micrometre, which sounds harmless and is not: it produced 7 buffers instead of 5, a minimum depth of 3 instead of 2, and 48 more square micrometres of cells. Depth costs variation, and every extra level is one more place for skew to accumulate. A knob that fights the tool usually loses.

Both are dense grids of wire. The left one carries several colours including pale yellow and white strands; the right one is built almost entirely from red, green and blue.

The tool draws each metal layer in its own colour, so the palette counts the layers for you. The restricted run has no upper-layer colours at all: everything is on the first three. It routed anyway, on 8 percent more wire, because a block this small has short nets. The same picture on a large design is what an unroutable block looks like.

The full placement in outline, with scattered cells filled in yellow and a handful in red. Most of the highlighted cells sit along the top and bottom rows and down the left edge.

Repair works where the timing is tight, and on this design much of that is near the boundary, because the port paths are given a fifth of the period as external delay and have to cross the block in what remains. A map like this one is the quickest way to see where the tool spent its effort, which is usually where the design needs attention.

Rows packed end to end with almost no gaps, like a brick wall, filling the whole core.

This is 92 percent utilization. Repair buffers, hold fixes, and late engineering changes all need free sites, and at this density there are none nearby, so the legalizer has to push cells around to make space. Most flows aim for 60 to 80 percent for exactly this reason. The clock tree and the grid live above the cells and are not the constraint.

Cells gathered in a loose cloud in the middle and upper left, with the right-hand fifth of the die and the top-left corner completely bare.

Empty silicon is paid for twice: once in area, and again in the wire needed to cross it. The placer is not at fault here, since it spread the design as evenly as its density target allowed. The floorplan is what needs changing, and the give-away is that the empty space is at the edges rather than in pockets.

The placement in faint outline, with a red route running down the right of the block, a cyan route wandering through the middle and lower half, and magenta boxes marking cells along the way. A legend in the corner names capture, launch, signal, instance and terminal.

A timing check is a race between two things, and this picture draws both: the data working its way from one register to another, and the clock arriving at each end. The clock route is usually the longer of the two on screen, because it comes from the root of the tree rather than from a neighbouring cell. The cells on the path are boxed, which is how you spot a path that runs through more logic than you expected.

A dense grey block with a red route that leaves the middle, runs down to the bottom edge, along it, and back up the right side, with green and cyan clock routes crossing the upper half.

A path that crosses the die is usually dominated by wire rather than by logic, and no amount of resizing fixes distance: the answer is to move the two ends closer together. This is why the worst path is worth looking at on the layout rather than only in a report, where it is a list of cells with no geometry at all.

On the left, mostly green and olive with four small deep-red tiles. On the right, deep-red tiles everywhere, joined into ribbons across the middle of the block, with green only at the edges.

The right-hand one is the same design on sky130 at 92 percent utilization, against 62 on the left. Packing a block leaves the router fewer tracks between the cells, and the map fills with tiles at capacity. Two things differ here, the process and the density, and the density is what dominates: a design packed this hard is hard to route on any process.

Deep-red tiles spread across the whole core, joined into ribbons through the middle, with a green margin at the edges.

There are dozens to choose from here, against four on the same design at a sensible density, and they run together rather than sitting apart. A handful of scattered tiles is a detour; a connected region is a block the router may not finish. The shape of the red matters as much as how much of it there is.

A dense weave of coloured wires over the whole core, crossed by three wide pink bands running left to right and three running top to bottom, with regular blue horizontal lines behind everything.

The straps are wide because they carry current, and they run in both directions on two upper layers so the grid is a mesh rather than a comb. The evenly spaced blue lines underneath are the rails that feed each row of cells. Signals weave around all of it, which is why a heavy grid and a congested design fight each other.

A green field with a cluster of red and orange tiles in the middle where the cells are, and a faint regular scatter of orange across the empty area around it.

Spreading a design over a larger die does not spread its connections. The cells stayed in a cloud and the traffic stayed with them, so a bigger die is not a fix for a congested block: it moves the same problem into a smaller fraction of a larger picture. Congestion follows cells, not area.

A dense field of cells with darker bands weaving between clusters of roughly equal size, repeating across the block, and pins along all four edges.

This cipher is built from identical parallel units, and the placer keeps each one together because the connectivity inside a unit is far denser than between them. The same pattern appears in this design's congestion map, which is the useful part: architecture shows up in more than one view, and recognizing it stops you hunting for a fault that is not there.

Both show deep red bands through the middle on a cooler background. The left legend runs to 845 microvolts, the right to 13.921 millivolts.

The left one is sixteen times healthier and looks every bit as alarming, because each map stretches its colours across its own range. On its 1.8 volt supply, 845 microvolts is five hundredths of a percent, while the right is 1.14 percent of 1.1 volts. Two maps of different designs on different processes cannot be compared by colour at all: only the numbers beside them mean anything.

A coarse grid of tiles over the core, green and olive through the middle with a dozen orange and dark red tiles scattered through it, and a cool teal band around the outside.

The colour in each tile is how much of that tile's wiring capacity the router asked for, and the scale stretches over whatever range the map happens to contain, so a block with nothing wrong still fills out the palette. The log settles it: the busiest layer, M2, is at 28.37 percent, the whole block uses 12.73 percent of its routing resource, and the maximum horizontal and vertical congestion is zero on every layer. Warm colours on a small block mean the scale is doing its job, not that the block is in trouble.

A chain of highlighted cells steps down and to the right across the core, joined by short red data wires, while the cyan launch clock runs out to the left edge of the die and back.

Read the stage delays in the timing report and the answer is not close. Every gate on the path costs between 10 and 30 picoseconds, and every net between them costs between 0.03 and 0.35 picoseconds. On a die 46 square micrometres across there is no wire long enough to matter. The picture is misleading in exactly the way a plan view always is: it shows distance, and distance is not what this path is spending. The reported minimum period is 331.69 picoseconds against the 310 asked for, so no amount of moving cells or rerouting closes it. Fewer logic levels or a slower clock will.

A magenta wire enters from the clock pin on the left edge and runs to the middle of the core, where the tree splits into four coloured branches: yellow over the top left, red over the top right, orange over the bottom left, green over the bottom right. Each branch ends on the flip-flops under it.

Clock tree synthesis groups sinks by position, because the cost it is trying to hold down is wire, and wire is distance. Four quadrants of flip-flops get four buffers sitting near the middle of each quadrant. The names confirm the shape: one root buffer at the pin and four leaf buffers, five in all, feeding 34 sinks, and the tree came out with 3.30 picoseconds of setup skew. Nothing about the logic entered into it. Two flip-flops in the same byte of the same register land on different colours if they were placed apart.

The core is solid with metal. Long wires in one colour run only up and down, long wires in two other colours run only left and right, and the short stubs that join them sit at the crossings.

Routing layers alternate their preferred direction, horizontal then vertical then horizontal, so a wire that needs to go around a corner goes up a layer through a via, travels the other way, and comes back down. Two consequences follow, and both matter more than the picture does. Adding one layer to a stack adds capacity in one direction only, which is why layers are worth counting in pairs. And every corner costs a via, so the vias, not the metal, are usually what runs out first in a congested block. This one is packed at 92 percent utilization on five routing layers and still came out clean, though the detailed router needed three passes to get there: 131 violations, then 86, then none.

Standard cells fill most of the core. Two tall rectangles sit near the bottom corners, each one surrounded by empty black space with a dashed line running through it, and the cells stop at that line rather than at the rectangle.

The macro placer was given a halo of 22.4 by 15.12 micrometres and treats it as part of the macro. The cost is easy to underrate. These two macros are 2481 square micrometres of silicon and 11928 square micrometres once the halos are counted, which is close to five times the area, on a block whose whole design area is 55855 square micrometres. What it buys is room at the macro edge, where every one of the macro's connections has to land, and a strip of quiet routing for nets that pass by. A floorplan that looks wasteful around its macros is usually paying that bill on purpose. The halo is a knob, not a law, and shrinking it is a normal thing to try.

Deep red over most of the cell area. The two macros at the bottom read red as well, and a cool green channel runs around each of them, separating them from the red field above.

A macro is an obstruction, not empty ground. Its own metal fills the lower layers across the whole footprint, the router's grid marks those tracks unusable, and a tile with nothing left to give sits at the top of the scale whether or not a single signal ever goes there. The routing view of this same run settles that last part: almost nothing crosses these two macros. One wire clips a corner and the rest of the traffic goes around. The cool channel beside each macro is the other half of the story. That is the halo, with no cells to wire and every track free, so it reads as cool as anything inside the core. Neither colour is a fault. Global routing finished with zero overflow on all ten layers, at 62.40 percent on metal2 and 35.51 percent overall.

Thousands of small boxes scattered across the core, wired together in red, green and yellow, with several large black voids between them and the two macros outlined at the bottom.

This block has 3913 sequential cells out of 27315 instances, so about one cell in seven is drawn here and the voids are solid combinational logic. Two things are worth taking from that. A clock view is not a floorplan and reading it as one will have you hunting for empty space that is not empty. And the tree that feeds those 3913 sinks needed 621 buffers of its own, cells that exist only to carry the clock and that burn power on every edge whether the logic does anything or not.

Cells cover most of the die in a ragged blob, thinning out towards the bottom right, where a wedge of the core is left bare. Pins run along all four edges.

A placer minimizes wire length and pays a penalty only when a region gets too dense. At 51 percent utilization that penalty almost never bites, so the cells gather wherever the connectivity pulls them and the ground nobody needs stays bare. Compare it with the block on the oversized die, where the design sits in a small cloud in the middle and every net is longer for it. The difference is not how square the blob looks, it is what the shape cost: this run wired 262811 micrometres, overflowed no layer, and finished with zero routing violations. If you wanted the fill even you could ask for it, and you would pay in wire.

Both are banded, cool at the edges and deep red in a broad stripe across the middle. The left legend runs to 8.866 millivolts, the right to 14.419 millivolts.

This is the case the other voltage pair does not cover. When the process and the supply match, the legends are in the same units against the same 1.1 volts, so the numbers compare directly: 0.81 percent on the left against 1.31 percent on the right. The colours still do not compare, because each map stretches its palette over its own range, and the two deepest reds here stand for readings that differ by a factor of 1.6. So the rule survives intact. Read the legend, then decide. One more thing worth knowing about these maps: they are drawn on the ground net, so what they show is the ground rising under the cells rather than the supply sagging above them. The same runs report 0.83 and 1.54 percent on the supply, and a cell that sits in both hot spots loses from both ends.

Wire covers the core edge to edge. The two macros near the bottom are pale rectangles with their own vertical stripes inside and almost nothing laid across them, and a band of bare rows surrounds each one.

Routing over a macro is allowed and routinely done, but only on the layers above the ones the macro's own metal occupies, and those are the same upper layers the power grid and the long global nets want. So the router treats it as expensive and takes it only when the detour costs more. Here there is room to go around, and it does: one wire clips a corner and everything else turns. Two things follow. When a floorplan gets tight, over-the-macro routing is a lever you can pull, at the cost of upper-layer resource. And the bare rows around each macro are the halo, which is why the same run's congestion map reads cold in exactly that ring.

The launch clock, the data path and the capture clock all sit inside the top left corner of the die. The rest of the block, including both macros, is untouched grey.

The worst path is the single deepest hole, and a plan view of it tells you nothing about how many other holes there are. The number that does is the total negative slack, which came to -47.93 nanoseconds against a worst path of -0.13. No endpoint can contribute more than the worst one, so at least 369 endpoints are failing, and they are not all in this corner. This is the most common misread of a worst-path view. Fix what it shows and the report comes back with a different path, sometimes hundreds of times over. Look at the worst path to understand the shape of the problem, and at the total to understand the size of it.

A warm orange and red field over most of the core, with an even green wedge along the bottom right and a green band round the outside. The warm area has a ragged edge.

Congestion follows demand and demand follows cells. Put the placement view of this run beside this one and the ragged warm edge traces the ragged edge of the cell blob exactly, which is worth knowing on its own: a congestion map hands you the floorplan for free. Spare capacity over bare silicon cannot be lent to the crowded middle. The only way to use it is to move cells into it, and that trades congestion for wire length on every net you stretch. Whether the trade is worth making is what the two maps together are for.

Dense signal routing in green, yellow and red, crossed by thick pink stripes that run the full width of the die at a regular spacing. A dark blue region at the bottom right has the stripes but almost nothing else.

The supply comes in as a grid of wide straps on the upper layers, dropping through vias to the rails that run along every cell row. The spacing is a real design choice: closer straps mean less voltage drop and less routing resource left for signals. Two things in the drill are worth checking against this picture. The voltage map from this same run is banded, and the bands share this pitch, because how far a cell sits from a strap is most of what sets its drop. And the routing view of the same run is this picture with the supply nets switched off, which is the only difference between them.

The placement in outline with two kinds of cell filled in. Yellow ones line the top edge and both sides, more than forty of them. Red ones, eight in all, sit scattered in the interior.

The yellow ones are the port buffers, 35 on the inputs and 18 on the outputs, and they went in before placement started, one on every port, as a matter of course rather than in response to anything. That is why they sit around the edge. The red ones are rebuffering from setup repair, added later and only where the timing asked. So the colour tells you routine work from real work, and the useful habit is to look at the interior. Forty-odd cells around the rim of a block is the flow saying hello. Eight in the middle is the flow saying it had to try.

Rows of outlined cells across the core, broken by black gaps of every size, including one wide one near the middle.

The placement view switches off physical cells on purpose, and that is the more useful picture. What you see is the design, and what you do not see is the slack: the black is free row space, which is where repair buffers, hold fixes and any late change have to fit. This block is 76 percent utilized, so a quarter of the rows are open and there is room almost everywhere. Hold that against the Skywater block in this drill, which looks like a brick wall because at 92 percent it nearly is, and has almost nowhere left to put anything.

Two kinds of highlighted cell over the placement outline. Several dozen yellow ones around the rim of the core, and nine red ones out in the middle of the block.

The red ones. Those are the rebuffering cells, added during repair and only where the timing asked for them. The yellow crowd around the edge is the port buffers, 53 of them, put in before placement had even started because every port gets one whether it needs help or not. So the two colours answer two different questions. Yellow tells you where the block's boundary is. Red tells you where it hurt.

A hot orange and red field over the cells. Both macros read red, and beside each one, on its outer side, a band of green tiles separates it from everything else.

The halo is the quietest routing on the block for the simple reason that there are no cells in it to wire. Two things are worth taking from that. Capacity in the halo is not free capacity, because nets only go where their cells are, and a cool band beside a hot block is not relief. And the width of that band is a number you chose. Shrink the halo and the green shrinks with it, the cells move closer to the macro, and the crowding at the macro edge is yours to deal with.

The left one is one warm colour almost everywhere, near the top of its scale, with a cool margin. The right one is green and olive with a dozen hot tiles scattered through it.

The shape of the heat tells you which kind of problem you have. A shortage that applies to the whole block, such as taking its upper layers away, raises every tile at once and paints one flat colour. Local crowding leaves the background cool and puts peaks on top of it. So before reading any single tile, ask whether the map is flat or spiky. Flat sends you to the resources, the layer count, the track pitch, the die size. Spiky sends you to the placement. The left run was held to the lowest three layers and routed anyway, because the design is small. The right one had seven and used 12.73 percent of them.

The left one has black gaps of every size between the cells. The right one is a brick wall with hardly a gap in it.

Both views leave the fill cells out, so the black is honest free row space and the comparison is fair even across two processes, because what you are reading is a fraction and not a size. The left block is 76 percent utilized and has open sites almost everywhere. The right is 92 percent, and a buffer that has to go in at a particular place has nowhere near it to go, so the legalizer starts shoving neighbours along the row to make space, which moves cells that were fine where they were. Density is not only an area number. It is how much freedom every later stage has.

A red path that sprawls over half the block, branching into stubs and dead ends rather than running from one place to another. The launch clock enters from the left edge, and green capture branches sit near the middle and bottom.

The red is the net the path runs on, and this path starts at the reset port, so the net drawn is the reset tree with its whole fan-out to the register file. A single logical path lights up half the die. Two things are worth keeping. A high fan-out control net is one of the hardest things in a block to time, because one driver has to reach everywhere and every load waits for the slowest. And the check here is not the one most people picture: this is a recovery check, asking that the reset go inactive early enough before a clock edge, in a path group of its own called asynchronous. The block passes it with 0.02 nanoseconds in hand on a 2.2 nanosecond clock, which is as close as closure gets.

A red mesh of clock wiring covering the entire core, thousands of small cells hanging off it, with one branch picked out in orange running from the clock pin at the top left down to the bottom right.

Insertion delay is common to the launch and the capture flip-flop, so on a path between two of them it subtracts out and only the difference between the two arrivals, the skew, is left. That is the arithmetic, and it is why a deep tree does not obviously hurt. What it does cost is everything that has nothing to cancel against. A path to or from a port is measured against the port, which waits for nobody. A reset release is checked against a clock edge that arrived late. And a longer chain of buffers has more places for variation to accumulate, so the skew you budgeted grows with the depth you allowed. Shallow trees are not about the delay. They are about everything that does not cancel.