Speed
Each summary describes a real run. Say whether the metric lands over or under the number asked, and the measured value is revealed against it. Keys o and u answer, h shows a hint, and Enter moves on. Guessing gets half right, so the score only means something above that. Progress is stored in this browser.
All 8 summaries in this family, with their numbers
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gcd on Nangate45, 45 nanometre: Is the smallest period this design can hold over 0.50 nanoseconds?0.46 nanoseconds, so under
Closing at 0.46 with no slack to spare means the minimum period is 0.46, which is 2.2 gigahertz. Small blocks reach frequencies that a whole chip never will, because they have short paths and no interface to speak of. Quoting a block's frequency as though it were the chip's is a classic mistake.
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gcd on Nangate45, 45 nanometre: Is the smallest period now over 0.50 nanoseconds?0.46 nanoseconds, so under
Nothing moved. The design still closes at 0.46 nanoseconds, because a block this small has short nets whichever layers it uses. Layer count matters through congestion and through the resistance of long wires, and neither bites here. On a large block the same restriction is severe.
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gcd, the same source on sky130 high density, 130 nanometre: Is the smallest period it can hold over 2 nanoseconds?2.56 nanoseconds, so over
2.56 nanoseconds, against 0.46 at 45 nanometres: five and a half times slower for three times the feature size. It also means this run misses its 1.10 nanosecond target badly, which the flow reports as a worst slack of -1.46. A default configuration is not a promise that the design closes.
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ibex, a RISC-V (Reduced Instruction Set Computer, fifth generation) core on Nangate45, 45 nanometre: Is the smallest period this core can hold over 1.5 nanoseconds?2.18 nanoseconds, so over
2.18 nanoseconds, 460 megahertz, against 2.2 gigahertz for the gcd block on the same process. Frequency is set by the longest path between registers, and a processor's decode and arithmetic paths are far deeper than anything in a small block. This is why a process is quoted with a design, and why block-level frequencies never survive integration.
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gcd on ASAP7, 7 nanometre: Is the clock target more than 1 nanosecond?0.31 nanoseconds, so under
310 picoseconds is 0.31 nanoseconds, so the target is over three gigahertz. Every platform declares its own time unit, and a number read in the wrong one is out by a thousand. The run reaches 331.69 picoseconds, so it misses its target slightly, which is invisible if you read the constraint as nanoseconds and think it passed by miles.
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jpeg on Nangate45, 45 nanometre: Is the smallest period it can hold over 1 nanosecond?1.11 nanoseconds, so over
1.11 nanoseconds against a target of 1.00, so it misses by 11 percent. A design packed to 85 percent has little room for repair to work in, and the same target with a looser floorplan may well close. Missing by a tenth is the ordinary state of a design in progress, not a disaster.
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aes on sky130 high density, 130 nanometre: Is the smallest period it can hold over 3 nanoseconds?3.74 nanoseconds, so over
3.74 nanoseconds, 4.6 times the Nangate45 constraint, and it misses its own 3.60 target by four percent. Both the gcd and aes comparisons put this process in the range of four to five times slower, which is the sort of rule of thumb worth carrying: it is how you sanity-check a schedule before anyone has run anything.
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gcd, run three times on Nangate45, 45 nanometre: Does the smallest period vary by more than 10 percent across them?4.5 percent, so under
0.44, 0.46 and 0.44 nanoseconds, under five percent apart, from 22 percent of wire length. On a small block at 45 nanometres the delay is mostly cells, so interconnect changes move it very little. The same sweep on a large block at an advanced node would tell a different story, which is the point: rules of thumb carry a scale with them.