Every metric

3605 micrometres for 648 nets is an average of about 5.6 micrometres a net, which is the right order for a block this small: most nets connect neighbours. Wire length scales with the square root of the area for a given cell count, so it is one of the easier numbers to estimate once you know the die.

The same netlist routes 3605 micrometres at the default utilization and 6099 here. Spreading a design out lengthens every net, which costs delay and power and forces repair to add buffers. Empty space is not free.

Taking away seven layers added only 8 percent of wire, and the design still routed with no violations. On a small block the router has room to detour; the same restriction on a dense design is what makes routing fail. Knowing which designs are sensitive is the useful part.

Chasing 0.30 nanoseconds cost 32 percent more area and never met the constraint. This is the shape of an over-constrained block: the area climbs, the slack barely moves, and the run still fails. The area is the evidence that the target, not the implementation, is wrong.

The same source occupies 7.5 times the area at 130 nanometres that it does at 45, and that is not purely the node: synthesis produced a different netlist for this library, 222 instances against 521. Both effects push the same way, and neither can be separated from the other by looking at the total. A figure quoted without its process and its netlist says almost nothing.

Starving the grid tripled the drop and it is still comfortable, because this design draws milliwatts. Voltage drop follows current, and a small block does not pull enough to trouble even a thin grid. The same change on a design drawing amperes is a different story.

Nearly 10 percent is past what most projects allow, and it is the current that does it: a control run of the same design with nothing changed drops 9.28 percent, against 9.9 with restricted routing. Half a watt is a different regime from the milliwatts the small block draws. Voltage drop is analysed per design for exactly this reason: the same grid is generous for one block and inadequate for the next.

275000 micrometres is 76 times the gcd figure for 28 times the cells, because a larger block has longer average nets as well as more of them. This superlinear growth is the reason wire delay dominates at scale and why hierarchy exists.

The netlist had 521 instances and the layout holds 1086. The difference is 458 filler cells, 48 well taps, 68 buffers added by timing repair, and the clock tree. A cell count quoted without saying which stage it came from can be out by a factor of two.

Filler is 458 cells, 42 percent of the count, and contributes no logic. It exists to keep the rows continuous, and the emptier the design, the more of it there is. This is why counting cells is a poor measure of a design and why area and utilization are quoted instead.

Five buffers, two deep at the shallowest point, for 35 registers. A tree is mostly about balance rather than drive at this scale, and a block this small barely needs levels at all. The count grows with sinks, but much more slowly than one to one.

107 buffers for 562 sinks is about one for every five, against one for every seven on the small block, so the tree grew a little faster than the sink count but nothing like as fast as a guess of one per register would suggest. The minimum depth went from two levels to three.

3771 buffers, a third as many as the cells doing the logic. On a design pushed for speed, repair is not a finishing touch: it is a large part of what ends up on the die, and it is the first place to look when the area comes back bigger than synthesis promised.

Closing at 0.46 with no slack to spare means the minimum period is 0.46, which is 2.2 gigahertz. Small blocks reach frequencies that a whole chip never will, because they have short paths and no interface to speak of. Quoting a block's frequency as though it were the chip's is a classic mistake.

Nothing moved. The design still closes at 0.46 nanoseconds, because a block this small has short nets whichever layers it uses. Layer count matters through congestion and through the resistance of long wires, and neither bites here. On a large block the same restriction is severe.

2.56 nanoseconds, against 0.46 at 45 nanometres: five and a half times slower for three times the feature size. It also means this run misses its 1.10 nanosecond target badly, which the flow reports as a worst slack of -1.46. A default configuration is not a promise that the design closes.

222 against 521, from identical source. A relaxed clock target needs less parallel structure, and a different library maps the same logic onto different cells. Comparing two platforms is never comparing one design: it is comparing two netlists that happen to share a source file.

9.38 milliwatts, three and a half times as much, despite running at a third of the frequency. The supply ratio alone squares to 2.7, and the larger transistors and longer wires carry more capacitance. This is the whole argument for moving to a smaller node, in one number.

1.26 square micrometres a cell against 1.14, which is 10 percent. Cell area is a property of the library and the mix of cells, not of the size of the design, so it stays put as a design grows. Wire length is the thing that grows superlinearly, which is why interconnect, not cells, is what limits large blocks.

5.60 milliwatts against 2.62, for a design that still failed timing. Upsizing raises capacitance, repair buffers add more, and the clock they all hang off runs faster. Pushing a block past what it can do costs area and power together, and buys nothing.

3599 micrometres against 3605, a fifth of a percent. At this density the grid was never what the signals were routing around. On a dense block with a heavy grid the two do compete, which is the trade a power plan makes: enough metal to hold the voltage, not so much that the signals cannot get through.

2.87 milliwatts against 2.62, under ten percent, from 69 percent more wire. Most of the power here is the cells and the clock rather than the interconnect, so lengthening the wires moves the total far less than it moves the delay. The cost of a loose floorplan is timing first, power second.

5434 after the first pass, then 2304, 1925, 100, and zero. A large count early is normal and says nothing on its own; what matters is whether each pass clears most of what the last one left. A count that stops falling is the one to worry about.

2.18 nanoseconds, 460 megahertz, against 2.2 gigahertz for the gcd block on the same process. Frequency is set by the longest path between registers, and a processor's decode and arithmetic paths are far deeper than anything in a small block. This is why a process is quoted with a design, and why block-level frequencies never survive integration.

424 buffers for 1938 registers, about one for every 4.6, continuing a trend from one in seven on the small block. Bigger designs need more levels and longer runs, so the tree grows faster than the sink count. At 509 square micrometres it is 1.7 percent of the cell area, and a good deal more of the power.

262811 micrometres against 275000 for aes, within five percent, for two designs that do entirely different things. Wire length follows the cell count and the floorplan far more than it follows what the logic computes, which is what makes it estimable at all.

31 milliwatts against 472, a factor of fifteen, for a similar amount of silicon. Most of that is the clock: aes runs 2.7 times faster, and its pipeline toggles far more of itself each cycle. Power is a statement about activity and frequency, not about size, which is why a power figure without its operating point means nothing.

46 square micrometres, against 716 at 45 nanometres and 5400 at 130. The whole block fits in a square about seven micrometres on a side. Scaling is the reason a design that was a chip in one generation is a corner of a chip in the next, and why area comparisons across nodes are close to meaningless without both numbers.

1.45 milliwatts, the lowest of the three, while running at three gigahertz. Lower supply, smaller transistors, and shorter wires all cut switching power faster than the frequency raises it. Leakage is the part that does not improve, which is why modern nodes fight it with threshold choice and power gating.

310 picoseconds is 0.31 nanoseconds, so the target is over three gigahertz. Every platform declares its own time unit, and a number read in the wrong one is out by a thousand. The run reaches 331.69 picoseconds, so it misses its target slightly, which is invisible if you read the constraint as nanoseconds and think it passed by miles.

568656 micrometres, 2.2 times the ibex figure for 3.8 times the cells. Wire length per cell actually falls here, because this design is packed at 85 percent utilization against 51 and its logic is more local. Density buys short wires, and pays for them in congestion and in voltage drop.

6.9 percent on the default grid, past what most projects allow. Density and current work together here: the same grid that is generous for a milliwatt block cannot feed a packed half-watt one. This is why the power plan is a design decision rather than a platform setting.

12618 inverters, over a third as many as the combinational cells that do the work, plus 5358 repair buffers and 934 clock buffers on top. A large fraction of a finished design exists only to carry signals far enough, fast enough, which is the same story as wire length told in cells.

1.11 nanoseconds against a target of 1.00, so it misses by 11 percent. A design packed to 85 percent has little room for repair to work in, and the same target with a looser floorplan may well close. Missing by a tenth is the ordinary state of a design in progress, not a disaster.

562 on both platforms, exactly. Registers are written in the source, so the count survives any library and any target: what changes between platforms is the combinational logic, which the mapper rebuilds from scratch. The register count is one of the few numbers that travels.

126974 square micrometres, 6.4 times the Nangate45 figure, close to the 7.5 the small block showed. The ratio between two processes is stable enough across designs to estimate with, which is what makes these comparisons worth learning rather than looking up each time.

3.74 nanoseconds, 4.6 times the Nangate45 constraint, and it misses its own 3.60 target by four percent. Both the gcd and aes comparisons put this process in the range of four to five times slower, which is the sort of rule of thumb worth carrying: it is how you sanity-check a schedule before anyone has run anything.

723, 716 and 709 square micrometres, a spread of two percent, and the loosest run is the largest because repair had longer wires to drive. Utilization sets how much empty space surrounds the cells, not how many there are. Within the normal range the knob does far less than people expect, which is worth knowing before spending a day sweeping it.

4193, 3605 and 3448 micrometres: 22 percent from end to end, and monotonic, so packing tighter does shorten wires. The effect is real but mild compared with the extreme case, where dropping to 9 percent utilization added 69 percent. Most of the damage lives outside the range anyone would actually choose.

0.44, 0.46 and 0.44 nanoseconds, under five percent apart, from 22 percent of wire length. On a small block at 45 nanometres the delay is mostly cells, so interconnect changes move it very little. The same sweep on a large block at an advanced node would tell a different story, which is the point: rules of thumb carry a scale with them.

274995 against 222438, 24 percent more wire for the same design, where the gcd block paid only 8 percent. A bigger design has more long nets, and long nets are the ones that need the upper layers, so the cost of a thin stack grows with the block. Both runs still closed, which says more about how much slack this design had than about the restriction.