Games / Log forensics / Constraints

Constraints

Each case shows the tail of a real run, ending where the tool stopped or warned. Say what caused it, or what to do about it. A case you miss returns later in the round and starts its schedule over; one you get right returns after 1, 3, 7, then 21 days. Keys 1 to 4 choose an option, h shows a hint, and Enter moves on. Progress is stored in this browser.

SourceEach case is the tail of a real run of the gcd design on Nangate45 in the openroad/orfs container, with one thing wrong. The same failures happen on commercial tools in different words: what carries across is the reasoning from the last few lines back to the cause. Reference: the OpenROAD documentation (OpenROAD-flow-scripts on GitHub).

All 5 cases in this stage, with answers

The constraints have just been read. What do these warnings mean?
1_synth log
```
read_sdc ./results/nangate45/gcd/no_clock/1_2_yosys.sdc
[WARNING STA-0351] clock 'core_clock' not found.
[WARNING STA-0351] clock 'vclk_core_clock' not found.
[WARNING STA-0138] clock arg 'vclk_core_clock' clock not found.
[WARNING STA-0138] clock arg 'vclk_core_clock' clock not found.
```
Later constraints name a clock that was never created.

Hint: Ask what kind of command names a clock without creating one.

Latency, uncertainty, and the port delays all refer to a clock by name, and each one warns separately when that name is unknown. They are warnings, not errors, so the run carries on and the consequences appear several stages later. This is the earliest point at which the mistake is visible.
```
create_clock -name core_clock -period 0.46 [get_ports clk]
```
The run is carrying on from here. What will the timing reports look like?
2_1_floorplan log
```
==========================================================================
Floorplan check_setup
--------------------------------------------------------------------------
Warning: There are 35 unclocked register/latch pins.
Warning: There are 53 unconstrained endpoints.
number instances in verilog is 521
```
Empty and perfect, because almost nothing is being checked.

Hint: Ask what a timing check needs at both ends of a path.

An unclocked register pin has no clock defined on it, so no path through it can be timed, and an unconstrained endpoint is one nothing checks. Worst negative slack then comes back as zero and the run looks like its best ever. A clean run reports neither of these lines, which is why this check is printed at the start of the floorplan.
```
check_setup
report_checks -unconstrained
```
The clock is fine and the run continues. What is not being checked?
2_1_floorplan log
```
==========================================================================
Floorplan check_setup
--------------------------------------------------------------------------
Warning: There are 35 input ports missing set_input_delay.
Warning: There are 18 output ports missing set_output_delay.
Warning: There are 18 unconstrained endpoints.
number instances in verilog is 521
```
Every path that starts or ends at a port.

Hint: Count the ports named, and ask what a path from a port needs before it can be timed.

A port has no arrival time of its own, so without an input delay the timer has nothing to start from, and without an output delay nothing to finish against. Those paths simply vanish from the reports. The interface is usually the tightest part of a block, so this is a comfortable way to close timing on a design that will fail in the system.
```
set_input_delay  [expr 0.2 * $clk_period] -clock $clk [all_inputs -no_clocks]
set_output_delay [expr 0.2 * $clk_period] -clock $clk [all_outputs]
```
The constraints do create a clock. What has this warning cost?
1_synth log
```
link_design gcd
read_sdc ./results/nangate45/gcd/bad_port/1_2_yosys.sdc
[WARNING STA-0366] port 'nosuchport' not found.
source /OpenROAD-flow-scripts/flow/platforms/nangate45/setRC.tcl
eliminate_dead_logic
Removed 0 unused instances and 0 unused nets.
```
The clock was created on nothing, so it clocks nothing.

Hint: Ask what `create_clock` does when the object list it is given is empty.

A port query that matches nothing returns an empty list, and creating a clock on an empty list is legal: it makes a virtual clock. The constraints file looks right, the clock is defined, and not one register is clocked. One warning line, among the normal output of reading the constraints, is the whole of the evidence.
```
set clk_port_name clk
```
Two clocks report the same thing. Which one is the problem?
4_1_cts log
```
[INFO GRT-0014] Routed nets: 612
[INFO GRT-0303] Global routing runtime = 00:00:00
[WARNING STA-0450] virtual clock core_clock can not be propagated.
[WARNING STA-0450] virtual clock vclk_core_clock can not be propagated.
estimate_parasitics -global_routing
Perform buffer insertion and gate resizing...
```
The core clock, since only the interface one should be virtual.

Hint: One of these two clocks is meant to be virtual. Ask which, and why.

A constraints file usually defines a second, source-less clock for the port delays, so the message about it is expected. The same message about the clock that should drive the registers means it never found its port. Reading warnings is often like this: the line is not new, the name in it is.
```
create_clock -name core_clock -period 0.46 [get_ports clk]
create_clock -name vclk_core_clock -period 0.46
```