Games / Command flash cards / Sign-off checks and violations / Electrical and reliability checks

Electrical and reliability checks

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SourceThese cards describe the checks a design must pass before tapeout, using the rule decks that ship with OpenROAD-flow-scripts: the KLayout runsets for sky130 and ASAP7 and the sky130 layout-versus-schematic runset. Rule names and values are quoted from those files. Every process has its own rules; the families and the reasons behind them are what carry across. Reference: the sky130 design rule documentation (the open rule decks on GitHub).
All 11 cards in this section, with answers
  • check_antennas -report_violating_nets
    The metal connected to a gate collects more charge than its oxide survives.

    Hint: The rule is about a ratio, and the damage happens before the chip ever runs.

    During etch, a metal piece attached to a gate but not yet to a diffusion collects charge, and the rule limits the ratio of that metal's area to the gate's. Fixes are a diode to bleed the charge away, or jumping the net to another layer so no single piece is large. the open rule decks reference

  • an ERC floating-gate error
    A gate input is left unconnected, so its voltage is undefined.

    Hint: Ask what a gate input that connects to nothing actually does.

    A floating input sits at an undefined level, which can leave both transistor stacks partly on and burn current. ERC (Electrical Rule Check) finds them; the fix is a tie cell, never a direct connection to the rail. the open rule decks reference

  • an electromigration violation on a power strap
    Current density is high enough that the metal will erode over time.

    Hint: It is a wear-out mechanism: the chip works at first.

    Electrons moving through a conductor gradually displace its atoms, so a wire carrying too much current per unit area eventually thins and opens. The rule is a current density limit, which is why supply straps are widened rather than lengthened. analyze_power_grid -enable_em reports the current per segment. the open rule decks reference

  • analyze_power_grid -net VDD
    The voltage the cells receive is lower than the supply, which slows them.

    Hint: The grid has resistance, and cells draw current through it.

    IR (current times resistance) drop is a static loss along the grid. Timing is characterized at a supply voltage, so a cell seeing less is slower than the analysis assumed. Fixes are a denser grid, wider straps, more bumps, or spreading the current-hungry cells. the open rule decks reference

  • a latch-up rule violation
    A transistor sits too far from a well tap, risking a self-sustaining short.

    Hint: It concerns the well and the substrate, not the wires.

    The parasitic bipolar structures in CMOS (Complementary Metal-Oxide-Semiconductor) can trigger and conduct until power is removed, destroying the part. Tying the wells and substrate firmly and often prevents it, which is the reason for the tap spacing rule and for inserting taps before placement. the open rule decks reference

  • a guard ring around an analog block
    A tied ring that collects substrate current before it arrives.

    Hint: Ask what travels through the substrate between neighbouring circuits.

    The ring is diffusion tied to a supply. Switching digital logic injects current into the shared substrate, where it becomes noise in a sensitive analog circuit. A guard ring tied to a supply gives that current a path away. It is also the standard defence against latch-up around large drivers. the open rule decks reference

  • an ESD check on an I/O pad
    Checks the pad's discharge path can carry a static event.

    Hint: The event happens before the chip is ever powered, in handling.

    The energy comes from a static discharge: ESD (Electrostatic Discharge) is a few amps for a few nanoseconds arriving at a pin. The pad cell contains clamps to conduct it to the rails, and the check confirms the metal between pad, clamp, and rail is wide enough and the path short enough. It is a pad-level check, distinct from the antenna rule. the open rule decks reference

  • a diode against a layer jump
    A diode costs area and leakage; jumping layers costs routing resources.

    Hint: Two ways to fix the same violation. Ask what each one costs.

    A diode drains the charge but is a cell that must be placed and connected. Jumping to a higher layer breaks the long piece of metal into parts, each small enough to pass, at the cost of vias and track space. repair_antennas -jumper_only chooses the second. the open rule decks reference

  • a static voltage drop analysis, against a dynamic one
    Average currents against the worst instant, when many cells switch together.

    Hint: One assumes an average current, the other a moment in time.

    Static analysis finds a weak grid. Dynamic analysis finds the moment when a clock edge switches a region at once and the local supply sags, which the average never shows. It needs switching activity, either from a simulation or generated by the tool. the open rule decks reference

  • electromigration on a signal net, not a power net
    The alternating current partly heals the metal, so the limits differ.

    Hint: A signal carries current in both directions. Ask what that changes.

    Current that reverses pushes atoms back, so the effective damage is much lower than for the one-way current in a supply. What remains is checked as an average and a peak, and the nets at risk are the fast, heavily loaded ones, above all the clock. the open rule decks reference

  • timing analysed at the voltage each cell actually sees
    Cells in a sagging region are slower than the library corner says.

    Hint: A cell's delay came from a library characterized at a fixed voltage.

    A flat margin for supply droop over-margins most of the die and can still miss a hotspot. Passing the per-instance voltage into timing catches the paths that run through the weak region, which is the point of a voltage-aware analysis. the open rule decks reference