Games / Command flash cards / Sign-off checks and violations / Connectivity and LVS

Connectivity and LVS

Each card shows a command to explain. A missed card returns later in the round and starts the schedule over. A card answered correctly moves up the schedule and next appears after 1, 3, 7, then 21 days. Keys 1 to 4 choose an option, h shows a hint, and Enter moves on. A hint keeps the card where it is on the schedule. An ordering card is answered by clicking its items in order, and one wrong click ends it. Time values are in nanoseconds. Progress is stored in this browser.

SourceThese cards describe the checks a design must pass before tapeout, using the rule decks that ship with OpenROAD-flow-scripts: the KLayout runsets for sky130 and ASAP7 and the sky130 layout-versus-schematic runset. Rule names and values are quoted from those files. Every process has its own rules; the families and the reasons behind them are what carry across. Reference: the sky130 design rule documentation (the open rule decks on GitHub).
All 9 cards in this section, with answers
  • extract_devices(mos4("nfet_01v8"), { "SD" => NSD, "G" => STD_NGATE, ... })
    Recognizes transistors in the layout from the layers that overlap.

    Hint: The layout is only shapes. Ask what this turns them into.

    A gate is polysilicon crossing active area; the parts either side are source and drain. Device recognition turns the drawing back into a circuit, which is the first half of LVS (Layout Versus Schematic). The connect statements that follow build the nets between those devices. the open rule decks reference

  • schematic("sky130hd.cdl")
    Gives the intended netlist that the extracted layout is compared against.

    Hint: Two netlists exist by this point. Ask where the second one comes from.

    LVS (Layout Versus Schematic) compares two graphs: the one extracted from the layout and the one the design intends, here a CDL (Circuit Description Language) netlist written by the flow. A mismatch means the layout is not the circuit that was verified. the open rule decks reference

  • an LVS short
    Two nets that should be separate are connected in the layout.

    Hint: Two things in the netlist became one in the layout.

    A short usually comes from overlapping metal or a misplaced via, and it is reported as one extracted net matching two schematic nets. It is the most common serious LVS (Layout Versus Schematic) error, and the extracted net's name usually names both signals that were merged. the open rule decks reference

  • an LVS open
    One net appears as two disconnected pieces in the layout.

    Hint: The opposite failure to a short.

    The pieces belong to one net in the netlist. An open comes from a missing via or a wire that does not quite reach. Because each piece may still connect to real pins, the report shows one schematic net matching two extracted nets, the mirror image of a short. the open rule decks reference

  • a device property mismatch in LVS
    The devices connect correctly but their sizes or types differ.

    Hint: The connectivity matches. Ask what else the comparison checks.

    Comparison checks parameters as well as topology: transistor width and length, and the device model (a regular against a high-threshold transistor, for instance). A wrong size passes connectivity and changes the circuit's behaviour, which is why properties are checked too. the open rule decks reference

  • a device parameter tolerance in LVS
    How far an extracted device size may differ from the schematic.

    Hint: Two numbers are compared. Ask whether they must be identical.

    The tolerance is what makes it not an error. Extraction measures a drawn shape and computes a width and length, which will not match the schematic's number to the last digit. The deck sets a tolerance so that rounding does not become an error, while a real size mistake still is. the open rule decks reference

  • an ERC check on a domain crossing
    Reports a signal crossing between supplies without a level shifter or isolation.

    Hint: Two domains, two supplies. Ask what must sit between them.

    A crossing that skips its interface cell works in simulation and burns current or fails on silicon. ERC (Electrical Rule Check) compares the supplies of a net's driver and loads, which is why the power intent has to be readable by the checker. the open rule decks reference

  • a hard macro treated as a black box in layout versus schematic
    Its pins are compared but its contents are not descended into.

    Hint: The macro was already checked once, by whoever built it.

    Checking a memory's transistors again at every level would be enormous and pointless, so the macro is verified once and then trusted. The risk is a macro whose layout and netlist were never checked together, which nothing above will catch. the open rule decks reference

  • the supply pins that no netlist line ever mentions
    Supplies are implicit in the netlist and must be made explicit.

    Hint: The layout has rails everywhere. Ask what the gate-level netlist says about them.

    A gate-level netlist usually leaves the rails out, while the layout is full of them. Verification either adds the connections by rule or reads a netlist that declares them, and multiple-supply designs must be checked this way or a cell tied to the wrong rail will pass. the open rule decks reference