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Hint: Four rules on one layer. Ask what each one measures.

Nearly every geometric rule is one of these: how narrow a shape may be, how close two shapes may come, how small a shape may be, and how far one layer must extend past another. The names and values here are sky130's, quoted from the rule deck the flow ships. the open rule decks reference

Hint: Both encode a layer and a check. Ask which one also encodes the kind of check.

Both give the layer and a number. In ASAP7 the middle letter also says what is measured: W for width, S for spacing, A for area, EN for enclosure, so GATE.S.1 is a gate spacing rule. sky130 puts the meaning in the description instead, as in m1.2 : min. m1 spacing. the open rule decks reference

Hint: Read the word before the dimension. It is not a minimum.

At small nodes lithography can only print one pitch for the critical layers, so fins and gates are not drawn freely: they sit on a fixed grid at a fixed width. This is why cells at such nodes are drawn to a standard template rather than shaped by hand. the open rule decks reference

Hint: The second rule mentions a size as well as a spacing.

A wide conductor is more prone to the etch and lithography effects that close a gap, so the rule deck keys the spacing to the width. Timing tools see the same thing from the other side: a non-default rule that widens a net must also widen its spacing. the open rule decks reference

Hint: Two layers are named. Ask which one has to be bigger, and why.

Layers are printed by separate masks that never align perfectly, so the upper layer must overhang enough that the contact is still covered when they shift. Too little enclosure gives a weak or open connection. This is the same rule family as via enclosure higher in the stack. the open rule decks reference

Hint: One is about the shape; the other is about the gap inside it.

A tiny island of metal may not print or may lift off, and a tiny hole may close up during etch. Minimum-area violations usually appear where a via lands on a short stub, which is why routers extend such stubs. the open rule decks reference

Hint: Ask how the end of a wire differs from its side.

A line end rounds and pulls back as it prints, so its position is less certain than a long edge. The rule keeps extra distance there, and it commonly applies only below a width threshold and within a distance window, which is why it has more parameters than plain spacing. the open rule decks reference

Hint: Ask whether the chip is slow or unbuildable.

Timing violations cost performance; geometric violations cost yield, and a foundry will not accept the design at all. This is why detailed routing iterates until the violation count is zero, and why a tapeout gate treats any remaining violation as blocking unless it is waived. the open rule decks reference

Hint: The layout is only shapes. Ask what this turns them into.

A gate is polysilicon crossing active area; the parts either side are source and drain. Device recognition turns the drawing back into a circuit, which is the first half of LVS (Layout Versus Schematic). The connect statements that follow build the nets between those devices. the open rule decks reference

Hint: Two netlists exist by this point. Ask where the second one comes from.

LVS (Layout Versus Schematic) compares two graphs: the one extracted from the layout and the one the design intends, here a CDL (Circuit Description Language) netlist written by the flow. A mismatch means the layout is not the circuit that was verified. the open rule decks reference

Hint: Two things in the netlist became one in the layout.

A short usually comes from overlapping metal or a misplaced via, and it is reported as one extracted net matching two schematic nets. It is the most common serious LVS (Layout Versus Schematic) error, and the extracted net's name usually names both signals that were merged. the open rule decks reference

Hint: The opposite failure to a short.

The pieces belong to one net in the netlist. An open comes from a missing via or a wire that does not quite reach. Because each piece may still connect to real pins, the report shows one schematic net matching two extracted nets, the mirror image of a short. the open rule decks reference

Hint: The connectivity matches. Ask what else the comparison checks.

Comparison checks parameters as well as topology: transistor width and length, and the device model (a regular against a high-threshold transistor, for instance). A wrong size passes connectivity and changes the circuit's behaviour, which is why properties are checked too. the open rule decks reference

Hint: The rule is about a ratio, and the damage happens before the chip ever runs.

During etch, a metal piece attached to a gate but not yet to a diffusion collects charge, and the rule limits the ratio of that metal's area to the gate's. Fixes are a diode to bleed the charge away, or jumping the net to another layer so no single piece is large. the open rule decks reference

Hint: Ask what a gate input that connects to nothing actually does.

A floating input sits at an undefined level, which can leave both transistor stacks partly on and burn current. ERC (Electrical Rule Check) finds them; the fix is a tie cell, never a direct connection to the rail. the open rule decks reference

Hint: It is a wear-out mechanism: the chip works at first.

Electrons moving through a conductor gradually displace its atoms, so a wire carrying too much current per unit area eventually thins and opens. The rule is a current density limit, which is why supply straps are widened rather than lengthened. analyze_power_grid -enable_em reports the current per segment. the open rule decks reference

Hint: The grid has resistance, and cells draw current through it.

IR (current times resistance) drop is a static loss along the grid. Timing is characterized at a supply voltage, so a cell seeing less is slower than the analysis assumed. Fixes are a denser grid, wider straps, more bumps, or spreading the current-hungry cells. the open rule decks reference

Hint: It concerns the well and the substrate, not the wires.

The parasitic bipolar structures in CMOS (Complementary Metal-Oxide-Semiconductor) can trigger and conduct until power is removed, destroying the part. Tying the wells and substrate firmly and often prevents it, which is the reason for the tap spacing rule and for inserting taps before placement. the open rule decks reference

Hint: Ask what the manufacturing step after deposition does to an uneven surface.

The limit applies to metal in each window, top and bottom. Chemical mechanical polishing removes material faster where there is less metal, so an uneven layer ends up dished or domed, which ruins the layers above it. The rule is checked over a sliding window, so a design can pass overall and still fail locally. the open rule decks reference

Hint: The design cannot add real wires. Ask what it adds instead.

Fill shapes are electrically inert; they exist to satisfy density. They do add capacitance to nearby wires, which is why extraction runs after fill in a careful flow, and why fill is kept away from sensitive nets. The flow turns it on with USE_FILL. the open rule decks reference

Hint: This one is an upper bound. Ask where a maximum would matter.

Density rules run both ways: too little metal polishes unevenly, too much can trap stress or interfere with a structure underneath. This rule comes from the sky130 deck and applies inside a parallel-plate capacitor structure, where extra metal3 would change the device. the open rule decks reference

Hint: Ask which checks need the foundry's rule deck, and which the design tools can do alone.

Geometry and connectivity come from the runsets; antennas do not. Extraction needs the foundry's own encoding of the rules, which is what a runset is. OpenROAD checks antennas from the routed database and the technology file, so that one can be run and repaired inside the flow. the open rule decks reference

Hint: Ask what a single number can and cannot tell you about a rule run.

Per rule, per run. A count is how progress is tracked, but it hides what matters: one violation can be a systematic problem repeated in a cell, and another can be a single stray shape. The flow writes the report so the results can be opened in the viewer. the open rule decks reference

Hint: Ask who has the authority to accept a violation, and on what basis.

Some rules are conservative or are met by construction in a macro the foundry supplied. Those cases are agreed and documented rather than fixed. A waiver is a decision with a name attached to it, not a way of silencing a checker. the open rule decks reference

Hint: Ask what has to be true at once, and whether timing alone is enough.

The checks constrain each other: fixing antennas adds diodes, fixing density adds fill that changes parasitics, and fixing timing moves cells. They must all hold on the same database, which is why sign-off is a gate on one final version rather than a series of independent passes. the open rule decks reference

Hint: Ask what travels through the substrate between neighbouring circuits.

The ring is diffusion tied to a supply. Switching digital logic injects current into the shared substrate, where it becomes noise in a sensitive analog circuit. A guard ring tied to a supply gives that current a path away. It is also the standard defence against latch-up around large drivers. the open rule decks reference

Hint: The event happens before the chip is ever powered, in handling.

The energy comes from a static discharge: ESD (Electrostatic Discharge) is a few amps for a few nanoseconds arriving at a pin. The pad cell contains clamps to conduct it to the rails, and the check confirms the metal between pad, clamp, and rail is wide enough and the path short enough. It is a pad-level check, distinct from the antenna rule. the open rule decks reference

Hint: A single via can fail; ask what costs almost nothing to add.

Doubling raises yield. A via is one of the most failure-prone features in manufacturing, and a lone via in a signal path makes the whole net fail. Where the layout allows it, a second via in parallel removes that single point of failure. It is a recommended rule rather than a hard one. the open rule decks reference

Hint: Ask what happens at the foundry if you break each one.

Decks carry both. Required rules define what can be manufactured at all; recommended rules, such as via doubling and extra spacing, raise yield. A team decides how many recommended violations it accepts, which is a business decision, not a technical one. the open rule decks reference

Hint: It is the opposite of a minimum-width rule: ask what being too wide causes.

Wide metal can lift or dish during polishing and can trap stress. The rule forces slots in it, which is why power straps in a real layout have holes. It constrains the power grid, since a strap must be wide for current but then needs slotting. the open rule decks reference

Hint: Two numbers are compared. Ask whether they must be identical.

The tolerance is what makes it not an error. Extraction measures a drawn shape and computes a width and length, which will not match the schematic's number to the last digit. The deck sets a tolerance so that rounding does not become an error, while a real size mistake still is. the open rule decks reference

Hint: Two domains, two supplies. Ask what must sit between them.

A crossing that skips its interface cell works in simulation and burns current or fails on silicon. ERC (Electrical Rule Check) compares the supplies of a net's driver and loads, which is why the power intent has to be readable by the checker. the open rule decks reference

Hint: Ask what fill does to the wires beside it, and which step must see that.

Fill shapes are not connected, but they are metal next to signal wires, so they add coupling capacitance. Extracting before fill gives an optimistic answer. This is why the order in a finishing flow is fixed rather than a matter of taste. the open rule decks reference

Hint: Same idea as metal fill, one layer group lower.

Lithography and etch depend on what surrounds a feature, so an isolated transistor prints differently from one in a dense field. Dummy shapes make the surroundings uniform. In standard-cell rows this is built into the cells; it matters most at the edges of a block and around macros. the open rule decks reference

Hint: Ask why passing at the typical condition is not enough.

Setup is usually worst slow and hot, hold worst fast and cold, and voltage drop worst when the supply is low and activity high. A part sold over a temperature and voltage range must meet all of them, which is what multi-corner analysis is for. Geometry is indeed corner-free. the open rule decks reference

Hint: Ask what has to be repeated after any change to the database.

Adding a buffer moves cells, which moves wires, which changes parasitics, density, and possibly antenna ratios. This coupling is why late changes are made as small, local edits and why a full sign-off run is expensive enough to be scheduled rather than casual. the open rule decks reference

Hint: Ask whether a design can pass on average and still fail.

The window is typically tens of microns square and steps across the die, so an empty region next to a dense one fails even when the layer's overall density is fine. Fill is therefore added per region, not globally. the open rule decks reference

Hint: Two ways to fix the same violation. Ask what each one costs.

A diode drains the charge but is a cell that must be placed and connected. Jumping to a higher layer breaks the long piece of metal into parts, each small enough to pass, at the cost of vias and track space. repair_antennas -jumper_only chooses the second. the open rule decks reference

Hint: Ask which check needs the most complete database.

The geometric and connectivity checks need everything: fill, the macros' real layouts, the seal ring. They therefore run on the merged layout at the end, while timing and electrical checks run repeatedly through the flow on the design database. the open rule decks reference

Hint: Ask what a clean result actually proves, and what it does not.

A deck has a version, a set of enabled rule groups, and often waivers. Running an old deck, or one missing the metal stack in use, gives a clean result that means little. This is why sign-off records which deck version was run, not only that it passed. the open rule decks reference

Hint: The wire is wide because it carries a lot. Ask what the one cut carries.

One cut is a bottleneck in both resistance and current density, and it is a single point of failure if it is malformed. The rule states how many cuts a wire of a given width needs, and routers satisfy it by dropping a via array rather than a single via. the open rule decks reference

Hint: Think about what the lithography can actually resolve on an edge.

A tiny jog does not print as drawn: it rounds away or pinches the shape. Minimum step and notch rules forbid features the process cannot hold, and they are a common output of a script that merges shapes without cleaning up what it produced. the open rule decks reference

Hint: Two shapes too close must go on different masks. Now make it three.

Below the resolution limit a layer is printed with two or more masks, and neighbours must alternate. Three shapes each too close to the other two form a cycle that cannot be two-coloured, so the layout must change. It is a graph problem the router has to respect while it routes. the open rule decks reference

Hint: Each cell passed on its own. Ask what only exists once they touch.

A cell is drawn so that any neighbour is legal in most combinations, but some pairs are not, and some need a gap. Flows handle it with placement padding, with rules forbidding certain neighbours, or by inserting a filler cell between them. the open rule decks reference

Hint: The macro was already checked once, by whoever built it.

Checking a memory's transistors again at every level would be enormous and pointless, so the macro is verified once and then trusted. The risk is a macro whose layout and netlist were never checked together, which nothing above will catch. the open rule decks reference

Hint: The layout has rails everywhere. Ask what the gate-level netlist says about them.

A gate-level netlist usually leaves the rails out, while the layout is full of them. Verification either adds the connections by rule or reads a netlist that declares them, and multiple-supply designs must be checked this way or a cell tied to the wrong rail will pass. the open rule decks reference

Hint: One assumes an average current, the other a moment in time.

Static analysis finds a weak grid. Dynamic analysis finds the moment when a clock edge switches a region at once and the local supply sags, which the average never shows. It needs switching activity, either from a simulation or generated by the tool. the open rule decks reference

Hint: A signal carries current in both directions. Ask what that changes.

Current that reverses pushes atoms back, so the effective damage is much lower than for the one-way current in a supply. What remains is checked as an average and a peak, and the nets at risk are the fast, heavily loaded ones, above all the clock. the open rule decks reference

Hint: A cell's delay came from a library characterized at a fixed voltage.

A flat margin for supply droop over-margins most of the die and can still miss a hotspot. Passing the per-instance voltage into timing catches the paths that run through the weak region, which is the point of a voltage-aware analysis. the open rule decks reference

Hint: The fill shapes sit next to the signal wires.

Fill is electrically present whether or not it is connected, and a wire running beside a field of it sees more capacitance than the pre-fill extraction assumed. That is why the order is route, fill, extract, then time, and why a late fill change means timing again. the open rule decks reference

Hint: Ask which one has a defined voltage, and what that does to coupling.

A floating shape between two wires passes coupling from one to the other and its own voltage is unpredictable. Tying fill to a rail makes it a shield and makes extraction straightforward, at the cost of connecting every piece and of the capacitance it adds to the supply. the open rule decks reference

Hint: Two layouts can both be legal and still not yield the same.

Two wires at minimum spacing over a long run are more likely to be bridged by a particle than the same wires spread apart. The analysis turns layout into a predicted defect rate, and it is why spreading wires and widening them where there is room is worth doing. the open rule decks reference

Hint: The rules are a simplification of what the lithography really does.

Rules are a conservative summary of a physical process, and some combinations slip through. Simulating the optics, or matching the layout against a library of known bad patterns, catches those. The fix is usually a small local change to the routing. the open rule decks reference

Hint: The wafer is polished flat after each layer.

The surface has to be flat before the next layer is printed, or that layer is out of focus. Chemical and mechanical polishing removes more where there is less metal to resist it, so the rule forces an even spread. Fill exists to satisfy it. the open rule decks reference

Hint: A full chip flat is enormous. Ask what can be checked only once.

A block used many times is verified once, and assembly checks the boundaries, the routing over the blocks, and the space between them. What this can miss is an interaction between a block's internals and something routed over it, so a final flat run is usually still done. the open rule decks reference

Hint: The rules are a document with a version, like anything else.

A revision can loosen a rule, tighten one, or replace it with a differently shaped one. Sign-off therefore records the exact deck version alongside the result, and a change of revision means running everything again. the open rule decks reference