Exact Zero-Skew Tree Construction

The idea

Stop balancing geometry and balance delay. Model every wire segment as resistance and capacitance and use the Elmore delay model (see its page in the Timing Analysis catalog) to compute signal delay through the tree. Then build bottom-up: pair up sinks (or subtrees), connect each pair with a wire, and solve exactly for the tapping point along that wire where the driver must attach so that Elmore delay to every sink on the left equals delay to every sink on the right. The balance equation is quadratic in the tap position and accounts for both sides' downstream capacitance, so a heavily loaded side correctly receives the shorter wire arm. If even placing the tap at one end cannot balance (one side much faster), elongate: add serpentine wire to the fast side until balance holds. Recurse pairing merged subtrees until one root remains: a tree with exactly zero skew in the model.

Why it was a landmark

It converted clock synthesis from heuristic balancing into exact construction: skew is eliminated by algebra, not statistics, load asymmetry included. The remaining inefficiency was that merge locations were chosen without foresight, so wire was sometimes wasted; characterizing all optimal merge locations is precisely what the Deferred-Merge Embedding (next page) added a year later.

Where you meet it today

The tapping-point balance computation is the arithmetic core inside essentially every tree-based clock synthesizer's merge step, whatever topology surrounds it.