mkdir -p results/nangate45/gcd/rt_min3/ echo 0.46 > results/nangate45/gcd/rt_min3/clock_period.txt /OpenROAD-flow-scripts/flow/scripts/synth.sh /OpenROAD-flow-scripts/flow/scripts/synth_canonicalize.tcl ./logs/nangate45/gcd/rt_min3/1_1_yosys_canonicalize.log Using ABC area script. Extracting clock period from SDC file: ./results/nangate45/gcd/rt_min3/clock_period.txt Setting clock period to 0.46 1. Executing Liberty frontend: /OpenROAD-flow-scripts/flow/platforms/nangate45/lib/NangateOpenCellLibrary_typical.lib 2. Executing Liberty frontend: /OpenROAD-flow-scripts/flow/platforms/nangate45/lib/NangateOpenCellLibrary_typical.lib 3. Executing Verilog-2005 frontend: /OpenROAD-flow-scripts/flow/designs/src/gcd/gcd.v 4. Executing Verilog-2005 frontend: /OpenROAD-flow-scripts/flow/platforms/nangate45/cells_clkgate.v 5. Executing HIERARCHY pass (managing design hierarchy). 6. Executing AST frontend in derive mode using pre-parsed AST for module `\gcd'. 6.1. Analyzing design hierarchy.. 6.2. Executing AST frontend in derive mode using pre-parsed AST for module `\GcdUnitDpathRTL_0x4d0fc71ead8d3d9e'. 6.3. Executing AST frontend in derive mode using pre-parsed AST for module `\GcdUnitCtrlRTL_0x4d0fc71ead8d3d9e'. 6.4. Analyzing design hierarchy.. 6.5. Executing AST frontend in derive mode using pre-parsed AST for module `\RegRst_0x9f365fdf6c8998a'. 6.6. Executing AST frontend in derive mode using pre-parsed AST for module `\RegEn_0x68db79c4ec1d6e5b'. 6.7. Executing AST frontend in derive mode using pre-parsed AST for module `\Subtractor_0x422b1f52edd46a85'. 6.8. Executing AST frontend in derive mode using pre-parsed AST for module `\Mux_0xdd6473406d1a99a'. 6.9. Executing AST frontend in derive mode using pre-parsed AST for module `\Mux_0x683fa1a418b072c9'. 6.10. Executing AST frontend in derive mode using pre-parsed AST for module `\ZeroComparator_0x422b1f52edd46a85'. 6.11. Executing AST frontend in derive mode using pre-parsed AST for module `\LtComparator_0x422b1f52edd46a85'. 6.12. Analyzing design hierarchy.. 6.13. Analyzing design hierarchy.. 7. Executing OPT_CLEAN pass (remove unused cells and wires). Warning: Ignoring module ZeroComparator_0x422b1f52edd46a85 because it contains processes (run 'proc' command first). Warning: Ignoring module Mux_0x683fa1a418b072c9 because it contains processes (run 'proc' command first). Warning: Ignoring module Mux_0xdd6473406d1a99a because it contains processes (run 'proc' command first). Warning: Ignoring module Subtractor_0x422b1f52edd46a85 because it contains processes (run 'proc' command first). Warning: Ignoring module RegEn_0x68db79c4ec1d6e5b because it contains processes (run 'proc' command first). Warning: Ignoring module RegRst_0x9f365fdf6c8998a because it contains processes (run 'proc' command first). Warning: Ignoring module GcdUnitCtrlRTL_0x4d0fc71ead8d3d9e because it contains processes (run 'proc' command first). Warning: Ignoring module LtComparator_0x422b1f52edd46a85 because it contains processes (run 'proc' command first). 8. Executing RTLIL backend. Warnings: 8 unique messages, 8 total End of script. Logfile hash: 2a5447741a, time: 0.09s, user: 0.06s, system: 0.01s, MEM: 38.00 MB peak Yosys 0.64+post (git sha1 UNKNOWN-dirty, g++ 11.4.0-1ubuntu1~22.04.3 -fPIC -O3) Time spent: 78% 4x read_liberty (0 sec), 11% 4x read_verilog (0 sec), ... Elapsed time: 0:00.10[h:]min:sec. CPU time: user 0.07 sys 0.02 (89%). Peak memory: 42240KB. Log Ext Elapsed/s Peak Memory/MB sha1sum result [0:20) 1_1_yosys_canonicalize .rtlil 0 41 0143866d45d6a9e39c47 /OpenROAD-flow-scripts/flow/scripts/synth.sh /OpenROAD-flow-scripts/flow/scripts/synth.tcl ./logs/nangate45/gcd/rt_min3/1_2_yosys.log Using ABC area script. Extracting clock period from SDC file: ./results/nangate45/gcd/rt_min3/clock_period.txt Setting clock period to 0.46 1. Executing RTLIL frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. 2.2. Analyzing design hierarchy.. 3. Executing SYNTH pass. 3.1. Executing HIERARCHY pass (managing design hierarchy). 3.1.1. Analyzing design hierarchy.. 3.1.2. Analyzing design hierarchy.. 3.2. Executing PROC pass (convert processes to netlists). 3.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 3.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 3.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 3.2.4. Executing PROC_INIT pass (extract init attributes). 3.2.5. Executing PROC_ARST pass (detect async resets in processes). 3.2.6. Executing PROC_ROM pass (convert switches to ROMs). 3.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 3.2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 3.2.9. Executing PROC_DFF pass (convert process syncs to FFs). 3.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 3.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 3.2.12. Executing OPT_EXPR pass (perform const folding). 3.3. Executing FLATTEN pass (flatten design). 3.4. Executing OPT_EXPR pass (perform const folding). 3.5. Executing OPT_CLEAN pass (remove unused cells and wires). 3.6. Executing CHECK pass (checking for obvious problems). 3.7. Executing OPT pass (performing simple optimizations). 3.7.1. Executing OPT_EXPR pass (perform const folding). 3.7.2. Executing OPT_MERGE pass (detect identical cells). 3.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 3.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 3.7.5. Executing OPT_MERGE pass (detect identical cells). 3.7.6. Executing OPT_DFF pass (perform DFF optimizations). 3.7.7. Executing OPT_CLEAN pass (remove unused cells and wires). 3.7.8. Executing OPT_EXPR pass (perform const folding). 3.7.9. Rerunning OPT passes. (Maybe there is more to do..) 3.7.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 3.7.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 3.7.12. Executing OPT_MERGE pass (detect identical cells). 3.7.13. Executing OPT_DFF pass (perform DFF optimizations). 3.7.14. Executing OPT_CLEAN pass (remove unused cells and wires). 3.7.15. Executing OPT_EXPR pass (perform const folding). 3.7.16. Finished fast OPT passes. (There is nothing left to do.) 3.8. Executing FSM pass (extract and optimize FSM). 3.8.1. Executing FSM_DETECT pass (finding FSMs in design). 3.8.2. Executing FSM_EXTRACT pass (extracting FSM from design). 3.8.3. Executing FSM_OPT pass (simple optimizations of FSMs). 3.8.4. Executing OPT_CLEAN pass (remove unused cells and wires). 3.8.5. Executing FSM_OPT pass (simple optimizations of FSMs). 3.8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 3.8.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 3.8.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 3.9. Executing OPT pass (performing simple optimizations). 3.9.1. Executing OPT_EXPR pass (perform const folding). 3.9.2. Executing OPT_MERGE pass (detect identical cells). 3.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 3.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 3.9.5. Executing OPT_MERGE pass (detect identical cells). 3.9.6. Executing OPT_DFF pass (perform DFF optimizations). 3.9.7. Executing OPT_CLEAN pass (remove unused cells and wires). 3.9.8. Executing OPT_EXPR pass (perform const folding). 3.9.9. Rerunning OPT passes. (Maybe there is more to do..) 3.9.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 3.9.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 3.9.12. Executing OPT_MERGE pass (detect identical cells). 3.9.13. Executing OPT_DFF pass (perform DFF optimizations). 3.9.14. Executing OPT_CLEAN pass (remove unused cells and wires). 3.9.15. Executing OPT_EXPR pass (perform const folding). 3.9.16. Finished fast OPT passes. (There is nothing left to do.) 3.10. Executing WREDUCE pass (reducing word size of cells). 3.11. Executing PEEPOPT pass (run peephole optimizers). 3.12. Executing OPT_CLEAN pass (remove unused cells and wires). 3.13. Executing ALUMACC pass (create $alu and $macc cells). 3.14. Executing SHARE pass (SAT-based resource sharing). 3.15. Executing OPT pass (performing simple optimizations). 3.15.1. Executing OPT_EXPR pass (perform const folding). 3.15.2. Executing OPT_MERGE pass (detect identical cells). 3.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 3.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 3.15.5. Executing OPT_MERGE pass (detect identical cells). 3.15.6. Executing OPT_DFF pass (perform DFF optimizations). 3.15.7. Executing OPT_CLEAN pass (remove unused cells and wires). 3.15.8. Executing OPT_EXPR pass (perform const folding). 3.15.9. Rerunning OPT passes. (Maybe there is more to do..) 3.15.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 3.15.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 3.15.12. Executing OPT_MERGE pass (detect identical cells). 3.15.13. Executing OPT_DFF pass (perform DFF optimizations). 3.15.14. Executing OPT_CLEAN pass (remove unused cells and wires). 3.15.15. Executing OPT_EXPR pass (perform const folding). 3.15.16. Finished fast OPT passes. (There is nothing left to do.) 3.16. Executing MEMORY pass. 3.16.1. Executing OPT_MEM pass (optimize memories). 3.16.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). 3.16.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 3.16.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 3.16.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 3.16.6. Executing OPT_CLEAN pass (remove unused cells and wires). 3.16.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 3.16.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). 3.16.9. Executing OPT_CLEAN pass (remove unused cells and wires). 3.16.10. Executing MEMORY_COLLECT pass (generating $mem cells). 3.17. Executing OPT_CLEAN pass (remove unused cells and wires). 4. Executing SYNTH pass. 4.1. Executing OPT pass (performing simple optimizations). 4.1.1. Executing OPT_EXPR pass (perform const folding). 4.1.2. Executing OPT_MERGE pass (detect identical cells). 4.1.3. Executing OPT_DFF pass (perform DFF optimizations). 4.1.4. Executing OPT_CLEAN pass (remove unused cells and wires). 4.1.5. Finished fast OPT passes. 4.2. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 4.3. Executing OPT pass (performing simple optimizations). 4.3.1. Executing OPT_EXPR pass (perform const folding). 4.3.2. Executing OPT_MERGE pass (detect identical cells). 4.3.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 4.3.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 4.3.5. Executing OPT_MERGE pass (detect identical cells). 4.3.6. Executing OPT_SHARE pass. 4.3.7. Executing OPT_DFF pass (perform DFF optimizations). 4.3.8. Executing OPT_CLEAN pass (remove unused cells and wires). 4.3.9. Executing OPT_EXPR pass (perform const folding). 4.3.10. Finished fast OPT passes. (There is nothing left to do.) 4.4. Executing TECHMAP pass (map to technology primitives). 4.4.1. Executing Verilog-2005 frontend: /OpenROAD-flow-scripts/tools/install/yosys/bin/../share/yosys/techmap.v 4.4.2. Executing Verilog-2005 frontend: /OpenROAD-flow-scripts/flow/platforms/common/lcu_kogge_stone.v 4.4.3. Continuing TECHMAP pass. 4.5. Executing OPT pass (performing simple optimizations). 4.5.1. Executing OPT_EXPR pass (perform const folding). 4.5.2. Executing OPT_MERGE pass (detect identical cells). 4.5.3. Executing OPT_DFF pass (perform DFF optimizations). 4.5.4. Executing OPT_CLEAN pass (remove unused cells and wires). 4.5.5. Finished fast OPT passes. 4.6. Executing HIERARCHY pass (managing design hierarchy). 4.6.1. Analyzing design hierarchy.. 4.6.2. Analyzing design hierarchy.. 4.7. Printing statistics. 4.8. Executing CHECK pass (checking for obvious problems). 5. Executing OPT pass (performing simple optimizations). 5.1. Executing OPT_EXPR pass (perform const folding). 5.2. Executing OPT_MERGE pass (detect identical cells). 5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 5.5. Executing OPT_MERGE pass (detect identical cells). 5.6. Executing OPT_DFF pass (perform DFF optimizations). 5.7. Executing OPT_CLEAN pass (remove unused cells and wires). 5.8. Executing OPT_EXPR pass (perform const folding). 5.9. Rerunning OPT passes. (Maybe there is more to do..) 5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 5.12. Executing OPT_MERGE pass (detect identical cells). 5.13. Executing OPT_DFF pass (perform DFF optimizations). 5.14. Executing OPT_CLEAN pass (remove unused cells and wires). 5.15. Executing OPT_EXPR pass (perform const folding). 5.16. Finished fast OPT passes. (There is nothing left to do.) 6. Executing TECHMAP pass (map to technology primitives). 6.1. Executing Verilog-2005 frontend: /OpenROAD-flow-scripts/flow/platforms/nangate45/cells_latch.v 6.2. Continuing TECHMAP pass. 7. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file). 7.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 8. Executing OPT pass (performing simple optimizations). 8.1. Executing OPT_EXPR pass (perform const folding). 8.2. Executing OPT_MERGE pass (detect identical cells). 8.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 8.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 8.5. Executing OPT_MERGE pass (detect identical cells). 8.6. Executing OPT_DFF pass (perform DFF optimizations). 8.7. Executing OPT_CLEAN pass (remove unused cells and wires). 8.8. Executing OPT_EXPR pass (perform const folding). 8.9. Rerunning OPT passes. (Maybe there is more to do..) 8.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 8.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 8.12. Executing OPT_MERGE pass (detect identical cells). 8.13. Executing OPT_DFF pass (perform DFF optimizations). 8.14. Executing OPT_CLEAN pass (remove unused cells and wires). 8.15. Executing OPT_EXPR pass (perform const folding). 8.16. Finished fast OPT passes. (There is nothing left to do.) 9. Executing SETUNDEF pass (replace undef values with defined constants). abc -script /OpenROAD-flow-scripts/flow/scripts/abc_area.script -liberty /OpenROAD-flow-scripts/flow/platforms/nangate45/lib/NangateOpenCellLibrary_typical.lib -dont_use TAPCELL_X1 -dont_use FILLCELL_X1 -dont_use AOI211_X1 -dont_use OAI211_X1 -constr ./objects/nangate45/gcd/rt_min3/abc.constr -D 0.46 10. Executing ABC pass (technology mapping using ABC). 10.1. Extracting gate netlist of module `\gcd' to `/input.blif'.. 10.1.1. Executed ABC. 10.1.2. Re-integrating ABC results. 11. Executing SPLITNETS pass (splitting up multi-bit signals). 12. Executing OPT_CLEAN pass (remove unused cells and wires). 13. Executing HILOMAP pass (mapping to constant drivers). 14. Executing INSBUF pass (insert buffer cells for connected wires). 15. Executing CHECK pass (checking for obvious problems). 16. Printing statistics. 17. Executing CHECK pass (checking for obvious problems). 18. Executing Verilog backend. 18.1. Executing BMUXMAP pass. 18.2. Executing DEMUXMAP pass. exec cp /OpenROAD-flow-scripts/flow/designs/nangate45/gcd/constraint.sdc ./results/nangate45/gcd/rt_min3/1_synth.sdc End of script. Logfile hash: d2ad92443e, time: 0.34s, user: 0.14s, system: 0.04s, MEM: 42.50 MB peak Yosys 0.64+post (git sha1 UNKNOWN-dirty, g++ 11.4.0-1ubuntu1~22.04.3 -fPIC -O3) Time spent: 45% 1x abc (0 sec), 9% 21x opt_clean (0 sec), ... Elapsed time: 0:00.34[h:]min:sec. CPU time: user 0.27 sys 0.05 (95%). Peak memory: 45056KB. Log Ext Elapsed/s Peak Memory/MB sha1sum result [0:20) 1_2_yosys .v 0 44 756ad24f74de658d5044 cp /OpenROAD-flow-scripts/flow/designs/nangate45/gcd/constraint.sdc ./results/nangate45/gcd/rt_min3/1_2_yosys.sdc OpenROAD 26Q3-173-gf5df0085c2 Features included (+) or not (-): +GPU +GUI +Python This program is licensed under the BSD-3 license. See the LICENSE file for details. Components of this program may be licensed under more restrictive licenses which must be honored. [INFO ORD-0030] Using 32 thread(s). mkdir -p ./objects/nangate45/gcd/rt_min3 /OpenROAD-flow-scripts/flow/scripts/flow.sh 1_synth synth_odb Running synth_odb.tcl, stage 1_synth read_liberty /OpenROAD-flow-scripts/flow/platforms/nangate45/lib/NangateOpenCellLibrary_typical.lib [INFO ODB-0227] LEF file: /OpenROAD-flow-scripts/flow/platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef, created 22 layers, 27 vias [INFO ODB-0227] LEF file: /OpenROAD-flow-scripts/flow/platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef, created 135 library cells link_design gcd read_sdc ./results/nangate45/gcd/rt_min3/1_2_yosys.sdc source /OpenROAD-flow-scripts/flow/platforms/nangate45/setRC.tcl eliminate_dead_logic Removed 0 unused instances and 0 unused nets. Design area 663 um^2 100% utilization. write_db ./results/nangate45/gcd/rt_min3/1_synth.odb write_sdc -no_timestamp ./results/nangate45/gcd/rt_min3/1_synth.sdc Elapsed time: 0:00.22[h:]min:sec. CPU time: user 0.19 sys 0.03 (97%). Peak memory: 113616KB. Log Ext Elapsed/s Peak Memory/MB sha1sum result [0:20) 1_synth .odb 0 110 5574db6bc0e99d58e06a 1_synth .sdc 7fe61694c034e1755ac1 /OpenROAD-flow-scripts/flow/scripts/flow.sh 2_1_floorplan floorplan Running floorplan.tcl, stage 2_1_floorplan read_liberty /OpenROAD-flow-scripts/flow/platforms/nangate45/lib/NangateOpenCellLibrary_typical.lib read_db ./results/nangate45/gcd/rt_min3/1_synth.odb read_sdc ./results/nangate45/gcd/rt_min3/1_synth.sdc source /OpenROAD-flow-scripts/flow/platforms/nangate45/setRC.tcl ========================================================================== Floorplan check_setup -------------------------------------------------------------------------- number instances in verilog is 521 [INFO IFP-0107] Defining die area using utilization: 55.00% and aspect ratio: 1. [WARNING IFP-0028] Core area lower left (1.000, 1.000) snapped to (1.140, 1.400). [INFO IFP-0001] Added 24 rows of 182 site FreePDK45_38x28_10R_NP_162NW_34O. [INFO IFP-0100] Die BBox: ( 0.000 0.000 ) ( 36.725 36.725 ) um [INFO IFP-0101] Core BBox: ( 1.140 1.400 ) ( 35.720 35.000 ) um [INFO IFP-0102] Core area: 1161.888 um^2 [INFO IFP-0103] Total instances area: 663.138 um^2 [INFO IFP-0104] Effective utilization: 0.571 [INFO IFP-0105] Number of instances: 521 source /OpenROAD-flow-scripts/flow/platforms/nangate45/make_tracks.tcl source /OpenROAD-flow-scripts/flow/platforms/nangate45/fastroute.tcl Repair tie lo fanout... Repair tie hi fanout... repair_timing -setup_margin 0 -hold_margin 0 -repair_tns 100 -setup -skip_last_gasp -sequence unbuffer,sizeup,swap,vt_swap -verbose [WARNING EST-0027] no estimated parasitics. Using wire load models. [INFO RSZ-0100] Repair move sequence: UnbufferMove SizeUpMove SwapPinsMove [INFO RSZ-0098] No setup violations found [INFO RSZ-0505] Runtime: 0.03s Default units for flow time 1ns capacitance 1fF resistance 1kohm voltage 1v current 1mA power 1nW distance 1um Layer | Unit Resistance | Unit Capacitance | (kohm/um) | (fF/um) ------------------------------------------------ metal1 | 5.43e-03 | 7.42e-02 metal2 | 3.57e-03 | 8.34e-02 metal3 | 3.57e-03 | 1.04e-01 metal4 | 1.50e-03 | 1.19e-01 metal5 | 1.50e-03 | 1.09e-01 metal6 | 1.50e-03 | 1.14e-01 metal7 | 1.88e-04 | 1.17e-01 metal8 | 1.88e-04 | 9.45e-02 metal9 | 3.75e-05 | 1.06e-01 metal10 | 3.75e-05 | 7.37e-01 ------------------------------------------------ Layer | Via Resistance | (kohm) ---------------------------- via1 | 5.00e-03 via2 | 5.00e-03 via3 | 5.00e-03 via4 | 3.00e-03 via5 | 3.00e-03 via6 | 3.00e-03 via7 | 1.00e-03 via8 | 1.00e-03 via9 | 5.00e-04 ---------------------------- Report metrics stage 2, floorplan final... ========================================================================== floorplan final report_design_area -------------------------------------------------------------------------- Design area 663 um^2 57% utilization. write_db ./results/nangate45/gcd/rt_min3/2_1_floorplan.odb write_sdc -no_timestamp ./results/nangate45/gcd/rt_min3/2_1_floorplan.sdc Elapsed time: 0:00.29[h:]min:sec. CPU time: user 0.24 sys 0.05 (98%). Peak memory: 132940KB. Log Ext Elapsed/s Peak Memory/MB sha1sum result [0:20) 2_1_floorplan .odb 0 129 756823344d91a4c3b0ef 2_1_floorplan .sdc 7fe61694c034e1755ac1 /OpenROAD-flow-scripts/flow/scripts/flow.sh 2_2_floorplan_macro macro_place Running macro_place.tcl, stage 2_2_floorplan_macro read_liberty /OpenROAD-flow-scripts/flow/platforms/nangate45/lib/NangateOpenCellLibrary_typical.lib read_db ./results/nangate45/gcd/rt_min3/2_1_floorplan.odb read_sdc ./results/nangate45/gcd/rt_min3/2_1_floorplan.sdc source /OpenROAD-flow-scripts/flow/platforms/nangate45/setRC.tcl No macros found: Skipping macro_placement Design area 663 um^2 57% utilization. write_db ./results/nangate45/gcd/rt_min3/2_2_floorplan_macro.odb Elapsed time: 0:00.22[h:]min:sec. CPU time: user 0.18 sys 0.02 (91%). Peak memory: 112356KB. Log Ext Elapsed/s Peak Memory/MB sha1sum result [0:20) 2_2_floorplan_macro .odb 0 109 756823344d91a4c3b0ef /OpenROAD-flow-scripts/flow/scripts/flow.sh 2_3_floorplan_tapcell tapcell Running tapcell.tcl, stage 2_3_floorplan_tapcell read_liberty /OpenROAD-flow-scripts/flow/platforms/nangate45/lib/NangateOpenCellLibrary_typical.lib read_db ./results/nangate45/gcd/rt_min3/2_2_floorplan_macro.odb read_sdc ./results/nangate45/gcd/rt_min3/2_1_floorplan.sdc source /OpenROAD-flow-scripts/flow/platforms/nangate45/setRC.tcl [INFO TAP-0004] Inserted 48 endcaps. [INFO TAP-0005] Inserted 0 tapcells. Design area 676 um^2 58% utilization. write_db ./results/nangate45/gcd/rt_min3/2_3_floorplan_tapcell.odb Elapsed time: 0:00.22[h:]min:sec. CPU time: user 0.18 sys 0.03 (92%). Peak memory: 112516KB. Log Ext Elapsed/s Peak Memory/MB sha1sum result [0:20) 2_3_floorplan_tapcell .odb 0 109 49259c794e061c9e9198 /OpenROAD-flow-scripts/flow/scripts/flow.sh 2_4_floorplan_pdn pdn Running pdn.tcl, stage 2_4_floorplan_pdn read_liberty /OpenROAD-flow-scripts/flow/platforms/nangate45/lib/NangateOpenCellLibrary_typical.lib read_db ./results/nangate45/gcd/rt_min3/2_3_floorplan_tapcell.odb read_sdc ./results/nangate45/gcd/rt_min3/2_1_floorplan.sdc source /OpenROAD-flow-scripts/flow/platforms/nangate45/setRC.tcl [INFO PDN-0001] Inserting grid: grid [INFO PDN-0500] Runtime: 0.00s Design area 676 um^2 58% utilization. write_db ./results/nangate45/gcd/rt_min3/2_4_floorplan_pdn.odb Elapsed time: 0:00.22[h:]min:sec. CPU time: user 0.18 sys 0.03 (94%). Peak memory: 114532KB. Log Ext Elapsed/s Peak Memory/MB sha1sum result [0:20) 2_4_floorplan_pdn .odb 0 111 64fba4e3d4b83b73ae9d cp ./results/nangate45/gcd/rt_min3/2_4_floorplan_pdn.odb ./results/nangate45/gcd/rt_min3/2_floorplan.odb cp ./results/nangate45/gcd/rt_min3/2_1_floorplan.sdc ./results/nangate45/gcd/rt_min3/2_floorplan.sdc /OpenROAD-flow-scripts/flow/scripts/flow.sh 3_1_place_gp_skip_io global_place_skip_io Running global_place_skip_io.tcl, stage 3_1_place_gp_skip_io read_liberty /OpenROAD-flow-scripts/flow/platforms/nangate45/lib/NangateOpenCellLibrary_typical.lib read_db ./results/nangate45/gcd/rt_min3/2_floorplan.odb read_sdc ./results/nangate45/gcd/rt_min3/2_floorplan.sdc source /OpenROAD-flow-scripts/flow/platforms/nangate45/setRC.tcl [INFO GPL-0022] Initialize gpl and calculate uniform density. Placement density is 0.738000020980835, computed from PLACE_DENSITY_LB_ADDON 0.20 and lower bound 0.6600000262260437 global_placement -skip_io -density 0.738000020980835 -pad_left 0 -pad_right 0 [INFO GPL-0001] ---- Initialize GPL Main Data Structures [INFO GPL-0002] DBU: 2000 [INFO GPL-0003] SiteSize: ( 0.190 1.400 ) um [INFO GPL-0004] CoreBBox: ( 1.140 1.400 ) ( 35.720 35.000 ) um [INFO GPL-0036] Movable instances area: 663.138 um^2 [INFO GPL-0037] Total instances area: 675.906 um^2 [INFO GPL-0035] Pin density area adjust: 86.630 um^2 [INFO GPL-0032] ---- Initialize Region: Top-level [INFO GPL-0006] Number of instances: 569 [INFO GPL-0007] Movable instances: 521 [INFO GPL-0008] Fixed instances: 48 [INFO GPL-0009] Dummy instances: 0 [INFO GPL-0010] Number of nets: 592 [INFO GPL-0011] Number of pins: 1644 [INFO GPL-0012] Die BBox: ( 0.000 0.000 ) ( 36.725 36.725 ) um [INFO GPL-0013] Core BBox: ( 1.140 1.400 ) ( 35.720 35.000 ) um [INFO GPL-0016] Core area: 1161.888 um^2 [INFO GPL-0014] Region name: top-level. [INFO GPL-0015] Region area: 1161.888 um^2 [INFO GPL-0017] Fixed instances area: 12.768 um^2 [INFO GPL-0018] Movable instances area: 749.768 um^2 [INFO GPL-0019] Utilization: 65.247 % [INFO GPL-0020] Standard cells area: 749.768 um^2 [INFO GPL-0021] Large instances area: 0.000 um^2 [INFO GPL-0005] ---- Execute Conjugate Gradient Initial Placement. [INFO GPL-0051] Source of initial instance position counters: Odb location = 0 Core center = 521 Region center = 0 [INFO GPL-0033] ---- Initialize Nesterov Region: Top-level [INFO GPL-0023] Placement target density: 0.7380 [INFO GPL-0024] Movable insts average area: 1.439 um^2 [INFO GPL-0025] Ideal bin area: 1.950 um^2 [INFO GPL-0026] Ideal bin count: 595 [INFO GPL-0027] Total bin area: 1161.888 um^2 [INFO GPL-0028] Bin count (X, Y): 16 , 16 [INFO GPL-0029] Bin size (W * H): 2.161 * 2.100 um [INFO GPL-0030] Number of bins: 256 [INFO GPL-0084] ---- Execute Nesterov Global Placement. [INFO GPL-0031] HPWL: Half-Perimeter Wirelength Iteration | Overflow | HPWL (um) | HPWL(%) | Penalty | Group --------------------------------------------------------------- 0 | 0.9817 | 3.199455e+02 | +0.00% | 3.94e-14 | 10 | 0.9798 | 2.289245e+02 | -28.45% | 6.41e-14 | 20 | 0.9790 | 2.274645e+02 | -0.64% | 1.04e-13 | 30 | 0.9792 | 2.272620e+02 | -0.09% | 1.70e-13 | 40 | 0.9793 | 2.273350e+02 | +0.03% | 2.77e-13 | 50 | 0.9792 | 2.274340e+02 | +0.04% | 4.51e-13 | 60 | 0.9791 | 2.274780e+02 | +0.02% | 7.35e-13 | 70 | 0.9790 | 2.276450e+02 | +0.07% | 1.20e-12 | 80 | 0.9788 | 2.279145e+02 | +0.12% | 1.95e-12 | 90 | 0.9784 | 2.283615e+02 | +0.20% | 3.18e-12 | 100 | 0.9777 | 2.291680e+02 | +0.35% | 5.18e-12 | 110 | 0.9761 | 2.307655e+02 | +0.70% | 8.43e-12 | 120 | 0.9718 | 2.337715e+02 | +1.30% | 1.37e-11 | 130 | 0.9651 | 2.415315e+02 | +3.32% | 2.24e-11 | 140 | 0.9636 | 2.965320e+02 | +22.77% | 3.64e-11 | 150 | 0.9410 | 4.665525e+02 | +57.34% | 5.94e-11 | 160 | 0.9076 | 5.819390e+02 | +24.73% | 9.67e-11 | 170 | 0.8664 | 8.017450e+02 | +37.77% | 1.57e-10 | 180 | 0.8461 | 9.085175e+02 | +13.32% | 2.57e-10 | 190 | 0.8137 | 1.075541e+03 | +18.38% | 4.18e-10 | 200 | 0.7781 | 1.199770e+03 | +11.55% | 6.81e-10 | 210 | 0.7319 | 1.361718e+03 | +13.50% | 1.11e-09 | 220 | 0.6871 | 1.502515e+03 | +10.34% | 1.81e-09 | 230 | 0.6442 | 1.642466e+03 | +9.31% | 2.94e-09 | 240 | 0.5937 | 1.785176e+03 | +8.69% | 4.79e-09 | 250 | 0.5405 | 1.920123e+03 | +7.56% | 7.80e-09 | 260 | 0.4881 | 2.045541e+03 | +6.53% | 1.27e-08 | 270 | 0.4377 | 2.159877e+03 | +5.59% | 2.07e-08 | 280 | 0.3833 | 2.260182e+03 | +4.64% | 3.37e-08 | 290 | 0.3233 | 2.311885e+03 | +2.29% | 5.33e-08 | 300 | 0.2790 | 2.349137e+03 | +1.61% | 7.85e-08 | 310 | 0.2405 | 2.384722e+03 | +1.51% | 1.16e-07 | 320 | 0.2101 | 2.419448e+03 | +1.46% | 1.70e-07 | 330 | 0.1812 | 2.445770e+03 | +1.09% | 2.51e-07 | 340 | 0.1607 | 2.461423e+03 | +0.64% | 3.70e-07 | 350 | 0.1343 | 2.476029e+03 | +0.59% | 5.45e-07 | 360 | 0.1140 | 2.486427e+03 | +0.42% | 8.02e-07 | 368 | 0.0994 | 2.493246e+03 | | 1.14e-06 | --------------------------------------------------------------- [INFO GPL-1001] Global placement finished at iteration 368 [INFO GPL-1002] Placed Cell Area 749.7678 [INFO GPL-1003] Available Free Area 1149.1200 [INFO GPL-1004] Minimum Feasible Density 0.6600 (cell_area / free_area) [INFO GPL-1006] Suggested Target Densities: [INFO GPL-1007] - For 90% usage of free space: 0.7250 [INFO GPL-1008] - For 80% usage of free space: 0.8156 [INFO GPL-1014] Final placement area: 749.77 (+0.00%) Took 83 seconds: global_placement -skip_io -density 0.738000020980835 -pad_left 0 -pad_right 0 Design area 676 um^2 58% utilization. write_db ./results/nangate45/gcd/rt_min3/3_1_place_gp_skip_io.odb Elapsed time: 1:23.20[h:]min:sec. CPU time: user 978.35 sys 1.00 (1177%). Peak memory: 114144KB. Log Ext Elapsed/s Peak Memory/MB sha1sum result [0:20) 3_1_place_gp_skip_io .odb 83 111 7cae8082a5762fcc875a /OpenROAD-flow-scripts/flow/scripts/flow.sh 3_2_place_iop io_placement Running io_placement.tcl, stage 3_2_place_iop read_liberty /OpenROAD-flow-scripts/flow/platforms/nangate45/lib/NangateOpenCellLibrary_typical.lib read_db ./results/nangate45/gcd/rt_min3/3_1_place_gp_skip_io.odb read_sdc ./results/nangate45/gcd/rt_min3/2_floorplan.sdc source /OpenROAD-flow-scripts/flow/platforms/nangate45/setRC.tcl place_pins -hor_layers metal5 -ver_layers metal6 Found 0 macro blocks. Using 2 tracks default min distance between IO pins. [INFO PPL-0001] Number of available slots 248 [INFO PPL-0002] Number of I/O 54 [INFO PPL-0003] Number of I/O w/sink 54 [INFO PPL-0004] Number of I/O w/o sink 0 [INFO PPL-0005] Slots per section 200 [INFO PPL-0008] Successfully assigned pins to sections. [INFO PPL-0012] I/O nets HPWL: 564.61 um. Design area 676 um^2 58% utilization. write_db ./results/nangate45/gcd/rt_min3/3_2_place_iop.odb Elapsed time: 0:00.34[h:]min:sec. CPU time: user 0.26 sys 0.03 (84%). Peak memory: 112840KB. Log Ext Elapsed/s Peak Memory/MB sha1sum result [0:20) 3_2_place_iop .odb 0 110 ea8758d8bcef7e75522f /OpenROAD-flow-scripts/flow/scripts/flow.sh 3_3_place_gp global_place Running global_place.tcl, stage 3_3_place_gp read_liberty /OpenROAD-flow-scripts/flow/platforms/nangate45/lib/NangateOpenCellLibrary_typical.lib read_db ./results/nangate45/gcd/rt_min3/3_2_place_iop.odb read_sdc ./results/nangate45/gcd/rt_min3/2_floorplan.sdc source /OpenROAD-flow-scripts/flow/platforms/nangate45/setRC.tcl [INFO RSZ-0026] Removed 17 buffers. Perform port buffering... [INFO RSZ-0027] Inserted 35 BUF_X1 input buffers. [INFO RSZ-0028] Inserted 18 BUF_X1 output buffers. [INFO GPL-0022] Initialize gpl and calculate uniform density. Placement density is 0.7460000133514404, computed from PLACE_DENSITY_LB_ADDON 0.20 and lower bound 0.6700000166893005 global_placement -density 0.7460000133514404 -pad_left 0 -pad_right 0 -routability_driven -timing_driven -force_center_initial_place -min_phi_coef 0.95 -max_phi_coef 1.05 [INFO GPL-0001] ---- Initialize GPL Main Data Structures [INFO GPL-0002] DBU: 2000 [INFO GPL-0003] SiteSize: ( 0.190 1.400 ) um [INFO GPL-0004] CoreBBox: ( 1.140 1.400 ) ( 35.720 35.000 ) um [INFO GPL-0036] Movable instances area: 675.640 um^2 [INFO GPL-0037] Total instances area: 688.408 um^2 [INFO GPL-0035] Pin density area adjust: 85.983 um^2 [INFO GPL-0032] ---- Initialize Region: Top-level [INFO GPL-0006] Number of instances: 605 [INFO GPL-0007] Movable instances: 557 [INFO GPL-0008] Fixed instances: 48 [INFO GPL-0009] Dummy instances: 0 [INFO GPL-0010] Number of nets: 628 [INFO GPL-0011] Number of pins: 1770 [INFO GPL-0012] Die BBox: ( 0.000 0.000 ) ( 36.725 36.725 ) um [INFO GPL-0013] Core BBox: ( 1.140 1.400 ) ( 35.720 35.000 ) um [INFO GPL-0016] Core area: 1161.888 um^2 [INFO GPL-0014] Region name: top-level. [INFO GPL-0015] Region area: 1161.888 um^2 [INFO GPL-0017] Fixed instances area: 12.768 um^2 [INFO GPL-0018] Movable instances area: 761.623 um^2 [INFO GPL-0019] Utilization: 66.279 % [INFO GPL-0020] Standard cells area: 761.623 um^2 [INFO GPL-0021] Large instances area: 0.000 um^2 [INFO GPL-0005] ---- Execute Conjugate Gradient Initial Placement. [INFO GPL-0051] Source of initial instance position counters: Odb location = 0 Core center = 557 Region center = 0 [InitialPlace] Iter: 1 conjugate gradient residual: 0.00000008 HPWL: 8463021 [InitialPlace] Iter: 2 conjugate gradient residual: 0.00000010 HPWL: 5903494 [InitialPlace] Iter: 3 conjugate gradient residual: 0.00000006 HPWL: 5916037 [InitialPlace] Iter: 4 conjugate gradient residual: 0.00000012 HPWL: 5919518 [InitialPlace] Iter: 5 conjugate gradient residual: 0.00000011 HPWL: 5923447 [INFO GPL-0033] ---- Initialize Nesterov Region: Top-level [INFO GPL-0023] Placement target density: 0.7460 [INFO GPL-0024] Movable insts average area: 1.367 um^2 [INFO GPL-0025] Ideal bin area: 1.833 um^2 [INFO GPL-0026] Ideal bin count: 633 [INFO GPL-0027] Total bin area: 1161.888 um^2 [INFO GPL-0028] Bin count (X, Y): 16 , 16 [INFO GPL-0029] Bin size (W * H): 2.161 * 2.100 um [INFO GPL-0030] Number of bins: 256 [INFO GPL-0084] ---- Execute Nesterov Global Placement. [INFO GPL-0031] HPWL: Half-Perimeter Wirelength Iteration | Overflow | HPWL (um) | HPWL(%) | Penalty | Group --------------------------------------------------------------- 0 | 0.8751 | 1.457625e+03 | +0.00% | 3.54e-14 | 10 | 0.7488 | 1.788887e+03 | +22.73% | 5.76e-14 | 20 | 0.7303 | 1.810900e+03 | +1.23% | 9.38e-14 | 30 | 0.7305 | 1.810921e+03 | +0.00% | 1.53e-13 | 40 | 0.7342 | 1.806647e+03 | -0.24% | 2.49e-13 | 50 | 0.7323 | 1.812428e+03 | +0.32% | 4.05e-13 | 60 | 0.7316 | 1.813855e+03 | +0.08% | 6.60e-13 | 70 | 0.7324 | 1.810754e+03 | -0.17% | 1.08e-12 | 80 | 0.7318 | 1.809896e+03 | -0.05% | 1.75e-12 | 90 | 0.7310 | 1.810464e+03 | +0.03% | 2.85e-12 | 100 | 0.7310 | 1.811017e+03 | +0.03% | 4.65e-12 | 110 | 0.7307 | 1.812787e+03 | +0.10% | 7.57e-12 | 120 | 0.7298 | 1.815736e+03 | +0.16% | 1.23e-11 | 130 | 0.7284 | 1.819156e+03 | +0.19% | 2.01e-11 | 140 | 0.7261 | 1.824495e+03 | +0.29% | 3.27e-11 | 150 | 0.7228 | 1.833001e+03 | +0.47% | 5.33e-11 | 160 | 0.7182 | 1.845971e+03 | +0.71% | 8.68e-11 | 170 | 0.7110 | 1.865052e+03 | +1.03% | 1.41e-10 | 180 | 0.6997 | 1.892462e+03 | +1.47% | 2.30e-10 | 190 | 0.6854 | 1.929974e+03 | +1.98% | 3.75e-10 | 200 | 0.6687 | 1.977607e+03 | +2.47% | 6.11e-10 | 210 | 0.6429 | 2.034985e+03 | +2.90% | 9.96e-10 | [INFO GPL-0100] Timing-driven iteration 1/2, virtual: false. [INFO GPL-0101] Iter: 214, overflow: 0.634, keep resizer changes at: 1, HPWL: 4103889 Iteration | Area | Resized | Buffers | Nets repaired | Remaining --------------------------------------------------------------------- 0 | +0.0% | 0 | 0 | 0 | 628 final | +0.0% | 0 | 0 | 0 | 0 --------------------------------------------------------------------- Iter | Area | Removed | Inserted | Pins | | Buffers | Buffers | Remaining ------------------------------------------------------- 0 | +0.0% | 0 | 0 | 592 59 | +0.0% | 0 | 0 | 533 118 | +0.3% | 0 | 1 | 474 177 | +1.2% | 0 | 4 | 415 236 | +1.4% | 0 | 6 | 356 295 | +1.6% | 0 | 8 | 297 354 | +1.8% | 0 | 9 | 238 413 | +2.0% | 0 | 11 | 179 472 | +2.5% | 0 | 15 | 120 531 | +2.5% | 0 | 15 | 61 590 | +2.7% | 0 | 17 | 2 final | +2.7% | 0 | 17 | 0 ------------------------------------------------------- [INFO GPL-0106] Timing-driven: worst slack 2.05332e-11 [INFO GPL-0107] Timing-driven: repair_design delta area: 18.886 um^2 (+2.48%) [INFO GPL-0108] Timing-driven: repair_design, gpl delta gcells: 17 (+3.05%) [INFO GPL-0109] Timing-driven: repair_design, gcells created: 17, deleted: 0 [INFO GPL-0110] Timing-driven: new target density: 0.7624352 Iteration | Overflow | HPWL (um) | HPWL(%) | Penalty | Group --------------------------------------------------------------- 220 | 0.6074 | 2.233628e+03 | +9.76% | 1.62e-09 | [INFO GPL-0038] Routability snapshot saved at iter = 223 222 | 0.5993 | 2.249135e+03 | | | 230 | 0.5724 | 2.262375e+03 | +1.29% | 2.64e-09 | 240 | 0.5346 | 2.305507e+03 | +1.91% | 4.30e-09 | 250 | 0.4953 | 2.373412e+03 | +2.95% | 7.01e-09 | 260 | 0.4484 | 2.436425e+03 | +2.65% | 1.14e-08 | 270 | 0.4090 | 2.485782e+03 | +2.03% | 1.86e-08 | 280 | 0.3588 | 2.544639e+03 | +2.37% | 3.03e-08 | 290 | 0.3065 | 2.577309e+03 | +1.28% | 4.60e-08 | [INFO GPL-0040] Routability iteration: 1 [INFO GPL-0041] Total routing overflow: 0.0000 [INFO GPL-0042] Number of overflowed tiles: 0 (0.00%) [INFO GPL-0043] Average top 0.5% routing congestion: 0.7796 [INFO GPL-0044] Average top 1.0% routing congestion: 0.7751 [INFO GPL-0045] Average top 2.0% routing congestion: 0.7578 [INFO GPL-0046] Average top 5.0% routing congestion: 0.7236 [INFO GPL-0047] Routability iteration weighted routing congestion: 0.7774 [INFO GPL-0050] Weighted routing congestion is lower than target routing congestion(1.0100), end routability optimization. [INFO GPL-0090] Routability finished. Target routing congestion achieved succesfully. Iteration | Overflow | HPWL (um) | HPWL(%) | Penalty | Group --------------------------------------------------------------- 300 | 0.2766 | 2.606086e+03 | +1.12% | 6.78e-08 | 310 | 0.2443 | 2.645660e+03 | +1.52% | 9.98e-08 | 320 | 0.2126 | 2.682617e+03 | +1.40% | 1.47e-07 | [INFO GPL-0100] Timing-driven iteration 2/2, virtual: false. [INFO GPL-0101] Iter: 327, overflow: 0.194, keep resizer changes at: 1, HPWL: 5393579 Iteration | Area | Resized | Buffers | Nets repaired | Remaining --------------------------------------------------------------------- 0 | +0.0% | 0 | 0 | 0 | 645 final | +0.0% | 0 | 0 | 0 | 0 --------------------------------------------------------------------- Iter | Area | Removed | Inserted | Pins | | Buffers | Buffers | Remaining ------------------------------------------------------- 0 | +0.0% | 0 | 0 | 592 59 | +0.0% | 0 | 0 | 533 118 | +0.0% | 1 | 1 | 474 177 | -0.3% | 4 | 5 | 415 236 | -0.6% | 6 | 5 | 356 295 | -0.6% | 8 | 7 | 297 354 | -0.5% | 9 | 9 | 238 413 | -0.5% | 11 | 11 | 179 472 | -0.5% | 15 | 13 | 120 531 | -0.5% | 15 | 13 | 61 590 | -0.6% | 17 | 14 | 2 final | -0.6% | 17 | 14 | 0 ------------------------------------------------------- [INFO GPL-0106] Timing-driven: worst slack 1.4868717e-11 [INFO GPL-0107] Timing-driven: repair_design delta area: -4.522 um^2 (-0.58%) [INFO GPL-0108] Timing-driven: repair_design, gpl delta gcells: -3 (-0.52%) [INFO GPL-0109] Timing-driven: repair_design, gcells created: 14, deleted: 17 [INFO GPL-0110] Timing-driven: new target density: 0.75850004 Iteration | Overflow | HPWL (um) | HPWL(%) | Penalty | Group --------------------------------------------------------------- 330 | 0.1975 | 2.758242e+03 | +2.82% | 2.17e-07 | 340 | 0.1705 | 2.785827e+03 | +1.00% | 3.19e-07 | 350 | 0.1512 | 2.790358e+03 | +0.16% | 4.70e-07 | 360 | 0.1312 | 2.797039e+03 | +0.24% | 6.93e-07 | 370 | 0.1127 | 2.796593e+03 | -0.02% | 1.02e-06 | 380 | 0.1010 | 2.804272e+03 | +0.27% | 1.50e-06 | 381 | 0.0999 | 2.807524e+03 | | 1.62e-06 | --------------------------------------------------------------- [INFO GPL-1001] Global placement finished at iteration 381 [INFO GPL-1017] Routability mode iteration count: 69 [INFO GPL-1005] Routability final weighted congestion: 0.7402 [INFO GPL-1002] Placed Cell Area 775.9868 [INFO GPL-1003] Available Free Area 1149.1200 [INFO GPL-1004] Minimum Feasible Density 0.6700 (cell_area / free_area) [INFO GPL-1006] Suggested Target Densities: [INFO GPL-1007] - For 90% usage of free space: 0.7503 [INFO GPL-1008] - For 80% usage of free space: 0.8441 [INFO GPL-1011] Original area (um^2): 761.62 [INFO GPL-1012] Total routability artificial inflation: 0.00 (+0.00%) [INFO GPL-1013] Total timing-driven delta area: 14.36 (+1.89%) [INFO GPL-1014] Final placement area: 775.99 (+1.89%) Took 155 seconds: global_placement -density 0.7460000133514404 -pad_left 0 -pad_right 0 -routability_driven -timing_driven -force_center_initial_place -min_phi_coef 0.95 -max_phi_coef 1.05 estimate_parasitics -placement Report metrics stage 3, global place... ========================================================================== global place report_design_area -------------------------------------------------------------------------- Design area 703 um^2 60% utilization. write_db ./results/nangate45/gcd/rt_min3/3_3_place_gp.odb Elapsed time: 2:36.05[h:]min:sec. CPU time: user 1011.19 sys 0.98 (648%). Peak memory: 288688KB. Log Ext Elapsed/s Peak Memory/MB sha1sum result [0:20) 3_3_place_gp .odb 156 281 7d18049b0761a28b050f /OpenROAD-flow-scripts/flow/scripts/flow.sh 3_4_place_resized resize Running resize.tcl, stage 3_4_place_resized read_liberty /OpenROAD-flow-scripts/flow/platforms/nangate45/lib/NangateOpenCellLibrary_typical.lib read_db ./results/nangate45/gcd/rt_min3/3_3_place_gp.odb read_sdc ./results/nangate45/gcd/rt_min3/2_floorplan.sdc source /OpenROAD-flow-scripts/flow/platforms/nangate45/setRC.tcl estimate_parasitics -placement Perform buffer insertion and gate resizing... repair_design -verbose Iteration | Area | Resized | Buffers | Nets repaired | Remaining --------------------------------------------------------------------- 0 | +0.0% | 0 | 0 | 0 | 642 10 | +0.0% | 0 | 0 | 0 | 632 20 | +0.0% | 0 | 0 | 0 | 622 30 | +0.0% | 0 | 0 | 0 | 612 40 | +0.0% | 0 | 0 | 0 | 602 50 | +0.0% | 0 | 0 | 0 | 592 60 | +0.0% | 0 | 0 | 0 | 582 70 | +0.0% | 0 | 0 | 0 | 572 80 | +0.0% | 0 | 0 | 0 | 562 90 | +0.0% | 0 | 0 | 0 | 552 100 | +0.0% | 0 | 0 | 0 | 542 110 | +0.0% | 0 | 0 | 0 | 532 120 | +0.0% | 0 | 0 | 0 | 522 130 | +0.0% | 0 | 0 | 0 | 512 140 | +0.0% | 0 | 0 | 0 | 502 150 | +0.0% | 0 | 0 | 0 | 492 160 | +0.0% | 0 | 0 | 0 | 482 170 | +0.0% | 0 | 0 | 0 | 472 180 | +0.0% | 0 | 0 | 0 | 462 190 | +0.0% | 0 | 0 | 0 | 452 200 | +0.0% | 0 | 0 | 0 | 442 210 | +0.0% | 0 | 0 | 0 | 432 220 | +0.0% | 0 | 0 | 0 | 422 230 | +0.0% | 0 | 0 | 0 | 412 240 | +0.0% | 0 | 0 | 0 | 402 250 | +0.0% | 0 | 0 | 0 | 392 260 | +0.0% | 0 | 0 | 0 | 382 270 | +0.0% | 0 | 0 | 0 | 372 280 | +0.0% | 0 | 0 | 0 | 362 290 | +0.0% | 0 | 0 | 0 | 352 300 | +0.0% | 0 | 0 | 0 | 342 310 | +0.0% | 0 | 0 | 0 | 332 320 | +0.0% | 0 | 0 | 0 | 322 330 | +0.0% | 0 | 0 | 0 | 312 340 | +0.0% | 0 | 0 | 0 | 302 350 | +0.0% | 0 | 0 | 0 | 292 360 | +0.0% | 0 | 0 | 0 | 282 370 | +0.0% | 0 | 0 | 0 | 272 380 | +0.0% | 0 | 0 | 0 | 262 390 | +0.0% | 0 | 0 | 0 | 252 400 | +0.0% | 0 | 0 | 0 | 242 410 | +0.0% | 0 | 0 | 0 | 232 420 | +0.0% | 0 | 0 | 0 | 222 430 | +0.0% | 0 | 0 | 0 | 212 440 | +0.0% | 0 | 0 | 0 | 202 450 | +0.0% | 0 | 0 | 0 | 192 460 | +0.0% | 0 | 0 | 0 | 182 470 | +0.0% | 0 | 0 | 0 | 172 480 | +0.0% | 0 | 0 | 0 | 162 490 | +0.0% | 0 | 0 | 0 | 152 500 | +0.0% | 0 | 0 | 0 | 142 510 | +0.0% | 0 | 0 | 0 | 132 520 | +0.0% | 0 | 0 | 0 | 122 530 | +0.0% | 0 | 0 | 0 | 112 540 | +0.0% | 0 | 0 | 0 | 102 550 | +0.0% | 0 | 0 | 0 | 92 560 | +0.0% | 0 | 0 | 0 | 82 570 | +0.0% | 0 | 0 | 0 | 72 580 | +0.0% | 0 | 0 | 0 | 62 590 | +0.0% | 0 | 0 | 0 | 52 600 | +0.0% | 0 | 0 | 0 | 42 610 | +0.0% | 0 | 0 | 0 | 32 620 | +0.0% | 0 | 0 | 0 | 22 630 | +0.0% | 0 | 0 | 0 | 12 640 | +0.0% | 0 | 0 | 0 | 2 final | +0.0% | 0 | 0 | 0 | 0 --------------------------------------------------------------------- [INFO RSZ-0504] Runtime: 0.09s Floating nets: Report metrics stage 3, resizer... ========================================================================== resizer report_design_area -------------------------------------------------------------------------- Design area 703 um^2 60% utilization. Instance count before 619, after 619 Pin count before 1744, after 1744 write_db ./results/nangate45/gcd/rt_min3/3_4_place_resized.odb Elapsed time: 0:00.55[h:]min:sec. CPU time: user 0.39 sys 0.08 (85%). Peak memory: 132904KB. Log Ext Elapsed/s Peak Memory/MB sha1sum result [0:20) 3_4_place_resized .odb 0 129 7d18049b0761a28b050f /OpenROAD-flow-scripts/flow/scripts/flow.sh 3_5_place_dp detail_place Running detail_place.tcl, stage 3_5_place_dp read_liberty /OpenROAD-flow-scripts/flow/platforms/nangate45/lib/NangateOpenCellLibrary_typical.lib read_db ./results/nangate45/gcd/rt_min3/3_4_place_resized.odb read_sdc ./results/nangate45/gcd/rt_min3/2_floorplan.sdc source /OpenROAD-flow-scripts/flow/platforms/nangate45/setRC.tcl detailed_placement [INFO DPL-0006] Core area: 1161.89 um^2, Instances area: 702.77 um^2, Utilization: 60.5% [INFO DPL-0005] Diamond search max displacement: +/- 500 sites horizontally, +/- 100 rows vertically. [INFO DPL-1101] Legalizing using diamond search. Movements Summary --------------------------------------- Total cells: 571 Diamond Move Success: 571 (100.00%) Diamond Move Failure: 0 Rip-up and replace Success: 0 ( 0.00% of diamond failures) Rip-up and replace Failure: 0 Total Placement Failures: 0 --------------------------------------- [INFO DPL-0500] Runtime: 0.02s Placement Analysis --------------------------------- total displacement 539.0 u average displacement 0.9 u max displacement 2.7 u original HPWL 2828.9 u legalized HPWL 3270.6 u delta HPWL 16 % improve_placement -max_displacement "5 1" Detailed placement improvement. [INFO DPL-0401] Setting random seed to 1. [INFO DPL-0402] Setting maximum displacement 5 1 to 14000 2800 units. [INFO DPL-0320] Collected 102 fixed cells. [INFO DPL-0318] Collected 571 single height cells. [INFO DPL-0321] Collected 0 wide cells. [INFO DPL-0322] Image (2280, 2800) - (71440, 70000) [INFO DPL-0310] Assigned 571 cells into segments. Movement in X-direction is 0.000000, movement in Y-direction is 0.000000. [INFO DPL-0313] Found 0 cells in wrong regions. [INFO DPL-0315] Found 0 row alignment problems. [INFO DPL-0314] Found 0 site alignment problems. [INFO DPL-0311] Found 0 overlaps between adjacent cells. [INFO DPL-0312] Found 0 edge spacing violations and 0 padding violations. [INFO DPL-0303] Running algorithm for independent set matching. [INFO DPL-0300] Set matching objective is wirelength. [INFO DPL-0301] Pass 1 of matching; objective is 6.525640e+06. [INFO DPL-0302] End of matching; objective is 6.516230e+06, improvement is 0.14 percent. [INFO DPL-0303] Running algorithm for global swaps. [INFO DPL-0306] Pass 1 of global swaps; hpwl is 6.311625e+06. [INFO DPL-0306] Pass 2 of global swaps; hpwl is 6.265540e+06. [INFO DPL-0307] End of global swaps; objective is 6.265540e+06, improvement is 3.85 percent. [INFO DPL-0303] Running algorithm for vertical swaps. [INFO DPL-0308] Pass 1 of vertical swaps; hpwl is 6.220340e+06. [INFO DPL-0309] End of vertical swaps; objective is 6.220340e+06, improvement is 0.72 percent. [INFO DPL-0303] Running algorithm for reordering. [INFO DPL-0304] Pass 1 of reordering; objective is 6.185900e+06. [INFO DPL-0305] End of reordering; objective is 6.185900e+06, improvement is 0.55 percent. [INFO DPL-0303] Running algorithm for random improvement. [INFO DPL-0324] Random improver is using random generator. [INFO DPL-0325] Random improver is using hpwl objective. [INFO DPL-0326] Random improver cost string is (a). [INFO DPL-0332] End of pass, Generator random called 11420 times. [INFO DPL-0335] Generator random, Cumulative attempts 11420, swaps 2209, moves 3232 since last reset. [INFO DPL-0333] End of pass, Objective hpwl, Initial cost 6.185900e+06, Scratch cost 6.072210e+06, Incremental cost 6.072210e+06, Mismatch? N [INFO DPL-0338] End of pass, Total cost is 6.072210e+06. [INFO DPL-0327] Pass 1 of random improver; improvement in cost is 1.84 percent. [INFO DPL-0332] End of pass, Generator random called 11420 times. [INFO DPL-0335] Generator random, Cumulative attempts 22840, swaps 4269, moves 6587 since last reset. [INFO DPL-0333] End of pass, Objective hpwl, Initial cost 6.072210e+06, Scratch cost 6.008460e+06, Incremental cost 6.008460e+06, Mismatch? N [INFO DPL-0338] End of pass, Total cost is 6.008460e+06. [INFO DPL-0327] Pass 2 of random improver; improvement in cost is 1.05 percent. [INFO DPL-0332] End of pass, Generator random called 11420 times. [INFO DPL-0335] Generator random, Cumulative attempts 34260, swaps 6346, moves 9951 since last reset. [INFO DPL-0333] End of pass, Objective hpwl, Initial cost 6.008460e+06, Scratch cost 5.991660e+06, Incremental cost 5.991660e+06, Mismatch? N [INFO DPL-0338] End of pass, Total cost is 5.991660e+06. [INFO DPL-0327] Pass 3 of random improver; improvement in cost is 0.28 percent. [INFO DPL-0328] End of random improver; improvement is 3.140044 percent. [INFO DPL-0380] Cell flipping. [INFO DPL-0382] Changed 0 cell orientations for row compatibility. [INFO DPL-0383] Performed 197 cell flips. [INFO DPL-0384] End of flipping; objective is 5.873070e+06, improvement is 1.98 percent. [INFO DPL-0313] Found 0 cells in wrong regions. [INFO DPL-0315] Found 0 row alignment problems. [INFO DPL-0314] Found 0 site alignment problems. [INFO DPL-0311] Found 0 overlaps between adjacent cells. [INFO DPL-0312] Found 0 edge spacing violations and 0 padding violations. Detailed Improvement Results ------------------------------------------ Original HPWL 3270.6 u ( 1721.7, 1549.0) Final HPWL 2945.3 u ( 1555.7, 1389.6) Delta HPWL -9.9 % ( -9.6, -10.3) optimize_mirroring [INFO DPL-0020] Mirrored 32 instances [INFO DPL-0021] HPWL before 2945.3 u [INFO DPL-0022] HPWL after 2944.5 u [INFO DPL-0023] HPWL delta -0.0 % [INFO FLW-0012] Placement violations . estimate_parasitics -placement Report metrics stage 3, detailed place... ========================================================================== detailed place report_design_area -------------------------------------------------------------------------- Design area 703 um^2 60% utilization. write_db ./results/nangate45/gcd/rt_min3/3_5_place_dp.odb Elapsed time: 0:00.67[h:]min:sec. CPU time: user 0.51 sys 0.05 (82%). Peak memory: 118704KB. Log Ext Elapsed/s Peak Memory/MB sha1sum result [0:20) 3_5_place_dp .odb 0 115 f7690ce85663a17a768b cp ./results/nangate45/gcd/rt_min3/3_5_place_dp.odb ./results/nangate45/gcd/rt_min3/3_place.odb cp ./results/nangate45/gcd/rt_min3/2_floorplan.sdc ./results/nangate45/gcd/rt_min3/3_place.sdc /OpenROAD-flow-scripts/flow/scripts/flow.sh 4_1_cts cts Running cts.tcl, stage 4_1_cts read_liberty /OpenROAD-flow-scripts/flow/platforms/nangate45/lib/NangateOpenCellLibrary_typical.lib read_db ./results/nangate45/gcd/rt_min3/3_place.odb read_sdc ./results/nangate45/gcd/rt_min3/3_place.sdc source /OpenROAD-flow-scripts/flow/platforms/nangate45/setRC.tcl clock_tree_synthesis -sink_clustering_enable -repair_clock_nets [INFO CTS-0050] Root buffer is CLKBUF_X3. [INFO CTS-0051] Sink buffer is CLKBUF_X3. [INFO CTS-0052] The following clock buffers will be used for CTS: CLKBUF_X3 [INFO CTS-0049] Characterization buffer is CLKBUF_X3. [INFO CTS-0007] Net "clk" found for clock "core_clock". [INFO CTS-0010] Clock net "clk" has 35 sinks. [INFO CTS-0008] TritonCTS found 1 clock nets. [INFO CTS-0097] Characterization used 1 buffer(s) types. [INFO CTS-0201] 0 blockages from hard placement blockages and placed macros will be used. [INFO CTS-0027] Generating H-Tree topology for net clk. [INFO CTS-0028] Total number of sinks: 35. [INFO CTS-0090] Sinks will be clustered based on buffer max cap. [INFO CTS-0030] Number of static layers: 0. [INFO CTS-0020] Wire segment unit: 14000 dbu (7 um). [INFO CTS-0023] Original sink region: [(5890, 7170), (63650, 68770)]. [INFO CTS-0024] Normalized sink region: [(0.420714, 0.512143), (4.54643, 4.91214)]. [INFO CTS-0025] Width: 4.1257. [INFO CTS-0026] Height: 4.4000. Level 1 Direction: Vertical Sinks per sub-region: 18 Sub-region size: 4.1257 X 2.2000 [INFO CTS-0034] Segment length (rounded): 1. Level 2 Direction: Horizontal Sinks per sub-region: 9 Sub-region size: 2.0629 X 2.2000 [INFO CTS-0034] Segment length (rounded): 1. [INFO CTS-0032] Stop criterion found. Max number of sinks is 15. [INFO CTS-0035] Number of sinks covered: 35. [INFO CTS-0018] Created 5 clock buffers. [INFO CTS-0012] Minimum number of buffers in the clock path: 2. [INFO CTS-0013] Maximum number of buffers in the clock path: 2. [INFO CTS-0015] Created 5 clock nets. [INFO CTS-0016] Fanout distribution for the current clock = 8:2, 9:1, 10:1.. [INFO CTS-0017] Max level of the clock tree: 2. [INFO CTS-0098] Clock net "clk" [INFO CTS-0099] Sinks 38 [INFO CTS-0100] Leaf buffers 0 [INFO CTS-0101] Average sink wire length 50.43 um [INFO CTS-0102] Path depth 2 - 2 [INFO CTS-0207] Dummy loads inserted 3 [INFO CTS-0500] Runtime: 0.68s estimate_parasitics -placement detailed_placement [INFO DPL-0006] Core area: 1161.89 um^2, Instances area: 711.28 um^2, Utilization: 61.2% [INFO DPL-0005] Diamond search max displacement: +/- 500 sites horizontally, +/- 100 rows vertically. [INFO DPL-1101] Legalizing using diamond search. Movements Summary --------------------------------------- Total cells: 579 Diamond Move Success: 579 (100.00%) Diamond Move Failure: 0 Rip-up and replace Success: 0 ( 0.00% of diamond failures) Rip-up and replace Failure: 0 Total Placement Failures: 0 --------------------------------------- [INFO DPL-0500] Runtime: 0.00s Placement Analysis --------------------------------- total displacement 21.6 u average displacement 0.0 u max displacement 2.7 u original HPWL 3036.4 u legalized HPWL 3113.7 u delta HPWL 3 % estimate_parasitics -placement repair_timing -setup_margin 0 -hold_margin 0 -repair_tns 100 -verbose [INFO RSZ-0100] Repair move sequence: UnbufferMove SizeUpMove SwapPinsMove BufferMove CloneMove SplitLoadMove [INFO RSZ-0098] No setup violations found [INFO RSZ-0505] Runtime: 0.04s [INFO RSZ-0033] No hold violations found. [INFO RSZ-0506] Runtime: 0.01s Repair timing output passed lec test detailed_placement [INFO DPL-0006] Core area: 1161.89 um^2, Instances area: 711.28 um^2, Utilization: 61.2% [INFO DPL-0005] Diamond search max displacement: +/- 500 sites horizontally, +/- 100 rows vertically. [INFO DPL-1101] Legalizing using diamond search. Movements Summary --------------------------------------- Total cells: 579 Diamond Move Success: 579 (100.00%) Diamond Move Failure: 0 Rip-up and replace Success: 0 ( 0.00% of diamond failures) Rip-up and replace Failure: 0 Total Placement Failures: 0 --------------------------------------- [INFO DPL-0500] Runtime: 0.00s Placement Analysis --------------------------------- total displacement 0.0 u average displacement 0.0 u max displacement 0.0 u original HPWL 3113.7 u legalized HPWL 3113.7 u delta HPWL 0 % Report metrics stage 4, cts final... ========================================================================== cts final report_design_area -------------------------------------------------------------------------- Design area 711 um^2 61% utilization. write_db ./results/nangate45/gcd/rt_min3/4_1_cts.odb write_sdc -no_timestamp ./results/nangate45/gcd/rt_min3/4_cts.sdc Elapsed time: 0:01.51[h:]min:sec. CPU time: user 1.27 sys 0.11 (91%). Peak memory: 145756KB. Log Ext Elapsed/s Peak Memory/MB sha1sum result [0:20) 4_1_cts .odb 1 142 9bcbcd77cba5ee2aa168 cp ./results/nangate45/gcd/rt_min3/4_1_cts.odb ./results/nangate45/gcd/rt_min3/4_cts.odb /OpenROAD-flow-scripts/flow/scripts/flow.sh 5_1_grt global_route Running global_route.tcl, stage 5_1_grt read_liberty /OpenROAD-flow-scripts/flow/platforms/nangate45/lib/NangateOpenCellLibrary_typical.lib read_db ./results/nangate45/gcd/rt_min3/4_cts.odb read_sdc ./results/nangate45/gcd/rt_min3/4_cts.sdc source /OpenROAD-flow-scripts/flow/platforms/nangate45/setRC.tcl pin_access [INFO DRT-0149] Reading tech and libs. Units: 2000 Number of layers: 21 Number of macros: 135 Number of vias: 33 Number of viarulegen: 19 [INFO DRT-0150] Reading design. Design: gcd Die area: ( 0 0 ) ( 73450 73450 ) Number of track patterns: 20 Number of DEF vias: 0 Number of components: 627 Number of terminals: 54 Number of snets: 2 Number of nets: 647 [INFO DRT-0167] List of default vias: Layer via3 default via: via3_2 Layer via4 default via: via4_0 Layer via5 default via: via5_0 Layer via6 default via: via6_0 Layer via7 default via: via7_0 Layer via8 default via: via8_0 Layer via9 default via: via9_0 [INFO DRT-0162] Library cell analysis. [INFO DRT-0163] Instance analysis. [INFO DRT-0164] Number of unique instances = 60. [INFO DRT-0168] Init region query. [INFO DRT-0024] Complete active. [INFO DRT-0024] Complete Fr_VIA. [INFO DRT-0024] Complete metal1. [INFO DRT-0024] Complete via1. [INFO DRT-0024] Complete metal2. [INFO DRT-0024] Complete via2. [INFO DRT-0024] Complete metal3. [INFO DRT-0024] Complete via3. [INFO DRT-0024] Complete metal4. [INFO DRT-0024] Complete via4. [INFO DRT-0024] Complete metal5. [INFO DRT-0024] Complete via5. [INFO DRT-0024] Complete metal6. [INFO DRT-0024] Complete via6. [INFO DRT-0024] Complete metal7. [INFO DRT-0024] Complete via7. [INFO DRT-0024] Complete metal8. [INFO DRT-0024] Complete via8. [INFO DRT-0024] Complete metal9. [INFO DRT-0024] Complete via9. [INFO DRT-0024] Complete metal10. [INFO DRT-0033] active shape region query size = 0. [INFO DRT-0033] FR_VIA shape region query size = 0. [INFO DRT-0033] metal1 shape region query size = 8270. [INFO DRT-0033] via1 shape region query size = 114. [INFO DRT-0033] metal2 shape region query size = 76. [INFO DRT-0033] via2 shape region query size = 114. [INFO DRT-0033] metal3 shape region query size = 76. [INFO DRT-0033] via3 shape region query size = 114. [INFO DRT-0033] metal4 shape region query size = 47. [INFO DRT-0033] via4 shape region query size = 60. [INFO DRT-0033] metal5 shape region query size = 37. [INFO DRT-0033] via5 shape region query size = 60. [INFO DRT-0033] metal6 shape region query size = 41. [INFO DRT-0033] via6 shape region query size = 24. [INFO DRT-0033] metal7 shape region query size = 9. [INFO DRT-0033] via7 shape region query size = 0. [INFO DRT-0033] metal8 shape region query size = 0. [INFO DRT-0033] via8 shape region query size = 0. [INFO DRT-0033] metal9 shape region query size = 0. [INFO DRT-0033] via9 shape region query size = 0. [INFO DRT-0033] metal10 shape region query size = 0. [INFO DRT-0165] Start pin access. [INFO DRT-0078] Complete 298 pins. [INFO DRT-0081] Complete 60 unique inst patterns. [INFO DRT-0084] Complete 253 groups. #scanned instances = 627 #unique instances = 60 #stdCellGenAp = 1397 #stdCellValidPlanarAp = 0 #stdCellValidViaAp = 1017 #stdCellPinNoAp = 0 #stdCellPinCnt = 1757 #instTermValidViaApCnt = 0 #macroGenAp = 0 #macroValidPlanarAp = 0 #macroValidViaAp = 0 #macroNoAp = 0 [INFO DRT-0166] Complete pin access. [INFO DRT-0267] cpu time = 00:00:07, elapsed time = 00:00:01, memory = 117.47 (MB), peak = 113.45 (MB) global_route -congestion_report_file ./reports/nangate45/gcd/rt_min3/congestion.rpt -congestion_iterations 30 -congestion_report_iter_step 5 -verbose [INFO GRT-0020] Min routing layer: metal3 [INFO GRT-0021] Max routing layer: metal10 [INFO GRT-0022] Global adjustment: 0% [INFO GRT-0023] Grid origin: (0, 0) [INFO GRT-0088] Layer metal1 Track-Pitch = 0.1400 line-2-Via Pitch: 0.1350 [INFO GRT-0088] Layer metal2 Track-Pitch = 0.1900 line-2-Via Pitch: 0.1400 [INFO GRT-0088] Layer metal3 Track-Pitch = 0.1400 line-2-Via Pitch: 0.1400 [INFO GRT-0088] Layer metal4 Track-Pitch = 0.2800 line-2-Via Pitch: 0.2800 [INFO GRT-0088] Layer metal5 Track-Pitch = 0.2800 line-2-Via Pitch: 0.2800 [INFO GRT-0088] Layer metal6 Track-Pitch = 0.2800 line-2-Via Pitch: 0.2800 [INFO GRT-0088] Layer metal7 Track-Pitch = 0.8000 line-2-Via Pitch: 0.8000 [INFO GRT-0088] Layer metal8 Track-Pitch = 0.8000 line-2-Via Pitch: 0.8000 [INFO GRT-0088] Layer metal9 Track-Pitch = 1.6000 line-2-Via Pitch: 1.6000 [INFO GRT-0088] Layer metal10 Track-Pitch = 1.6000 line-2-Via Pitch: 1.6000 [INFO GRT-0003] Macros: 0 [INFO GRT-0004] Blockages: 0 [INFO GRT-0019] Found 6 clock nets. [INFO GRT-0001] Minimum degree: 2 [INFO GRT-0002] Maximum degree: 22 [INFO GRT-0053] Routing resources analysis: Routing Original Derated Resource Layer Direction Resources Resources Reduction (%) --------------------------------------------------------------- metal1 Horizontal 0 0 0.00% metal2 Vertical 0 0 0.00% metal3 Horizontal 2845 1394 51.00% metal4 Vertical 1364 957 29.84% metal5 Horizontal 1409 997 29.24% metal6 Vertical 1429 1013 29.11% metal7 Horizontal 425 302 28.94% metal8 Vertical 495 352 28.89% metal9 Horizontal 242 143 40.91% metal10 Vertical 242 143 40.91% --------------------------------------------------------------- [INFO GRT-0197] Via related to pin nodes: 3955 [INFO GRT-0198] Via related Steiner nodes: 30 [INFO GRT-0199] Via filling finished. [INFO GRT-0111] Final number of vias: 5276 [INFO GRT-0112] Final usage 3D: 17134 [INFO GRT-0096] Final congestion report: Layer Resource Demand Usage (%) Max H / Max V / Total Congestion --------------------------------------------------------------------------------------- metal1 0 0 0.00% 0 / 0 / 0 metal2 0 0 0.00% 0 / 0 / 0 metal3 1394 614 44.05% 0 / 0 / 0 metal4 957 510 53.29% 0 / 0 / 0 metal5 997 80 8.02% 0 / 0 / 0 metal6 1013 102 10.07% 0 / 0 / 0 metal7 302 0 0.00% 0 / 0 / 0 metal8 352 0 0.00% 0 / 0 / 0 metal9 143 0 0.00% 0 / 0 / 0 metal10 143 0 0.00% 0 / 0 / 0 --------------------------------------------------------------------------------------- Total 5301 1306 24.64% 0 / 0 / 0 [INFO GRT-0018] Total wirelength: 6298 um [INFO GRT-0014] Routed nets: 628 [INFO GRT-0303] Global routing runtime = 00:00:00 [WARNING STA-0450] virtual clock vclk_core_clock can not be propagated. estimate_parasitics -global_routing Perform buffer insertion and gate resizing... repair_design -verbose Iteration | Area | Resized | Buffers | Nets repaired | Remaining --------------------------------------------------------------------- 0 | +0.0% | 0 | 0 | 0 | 650 10 | +0.0% | 0 | 0 | 0 | 640 20 | +0.0% | 0 | 0 | 0 | 630 30 | +0.0% | 0 | 0 | 0 | 620 40 | +0.0% | 0 | 0 | 0 | 610 50 | +0.0% | 0 | 0 | 0 | 600 60 | +0.0% | 0 | 0 | 0 | 590 70 | +0.0% | 0 | 0 | 0 | 580 80 | +0.0% | 0 | 0 | 0 | 570 90 | +0.0% | 0 | 0 | 0 | 560 100 | +0.0% | 0 | 0 | 0 | 550 110 | +0.0% | 0 | 0 | 0 | 540 120 | +0.0% | 0 | 0 | 0 | 530 130 | +0.0% | 0 | 0 | 0 | 520 140 | +0.0% | 0 | 0 | 0 | 510 150 | +0.0% | 0 | 0 | 0 | 500 160 | +0.0% | 0 | 0 | 0 | 490 170 | +0.0% | 0 | 0 | 0 | 480 180 | +0.0% | 0 | 0 | 0 | 470 190 | +0.0% | 0 | 0 | 0 | 460 200 | +0.0% | 0 | 0 | 0 | 450 210 | +0.0% | 0 | 0 | 0 | 440 220 | +0.0% | 0 | 0 | 0 | 430 230 | +0.0% | 0 | 0 | 0 | 420 240 | +0.0% | 0 | 0 | 0 | 410 250 | +0.0% | 0 | 0 | 0 | 400 260 | +0.0% | 0 | 0 | 0 | 390 270 | +0.0% | 0 | 0 | 0 | 380 280 | +0.0% | 0 | 0 | 0 | 370 290 | +0.0% | 0 | 0 | 0 | 360 300 | +0.0% | 0 | 0 | 0 | 350 310 | +0.0% | 0 | 0 | 0 | 340 320 | +0.0% | 0 | 0 | 0 | 330 330 | +0.0% | 0 | 0 | 0 | 320 340 | +0.0% | 0 | 0 | 0 | 310 350 | +0.0% | 0 | 0 | 0 | 300 360 | +0.0% | 0 | 0 | 0 | 290 370 | +0.0% | 0 | 0 | 0 | 280 380 | +0.0% | 0 | 0 | 0 | 270 390 | +0.0% | 0 | 0 | 0 | 260 400 | +0.0% | 0 | 0 | 0 | 250 410 | +0.0% | 0 | 0 | 0 | 240 420 | +0.0% | 0 | 0 | 0 | 230 430 | +0.0% | 0 | 0 | 0 | 220 440 | +0.0% | 0 | 0 | 0 | 210 450 | +0.0% | 0 | 0 | 0 | 200 460 | +0.0% | 0 | 0 | 0 | 190 470 | +0.0% | 0 | 0 | 0 | 180 480 | +0.0% | 0 | 0 | 0 | 170 490 | +0.0% | 0 | 0 | 0 | 160 500 | +0.0% | 0 | 0 | 0 | 150 510 | +0.0% | 0 | 0 | 0 | 140 520 | +0.0% | 0 | 0 | 0 | 130 530 | +0.0% | 0 | 0 | 0 | 120 [WARNING RSZ-0104] Net _495_ only has one pin. Check if it is intended to be dangling. [WARNING RSZ-0104] Net _494_ only has one pin. Check if it is intended to be dangling. [WARNING RSZ-0104] Net _493_ only has one pin. Check if it is intended to be dangling. [WARNING RSZ-0104] Net _492_ only has one pin. Check if it is intended to be dangling. 540 | +0.0% | 0 | 0 | 0 | 110 [WARNING RSZ-0104] Net _491_ only has one pin. Check if it is intended to be dangling. [WARNING RSZ-0104] Net _490_ only has one pin. Check if it is intended to be dangling. [WARNING RSZ-0104] Net _489_ only has one pin. Check if it is intended to be dangling. [WARNING RSZ-0104] Net _488_ only has one pin. Check if it is intended to be dangling. [WARNING RSZ-0104] Net _487_ only has one pin. Check if it is intended to be dangling. 550 | +0.0% | 0 | 0 | 0 | 100 [WARNING RSZ-0104] Net _485_ only has one pin. Check if it is intended to be dangling. [WARNING RSZ-0104] Net _500_ only has one pin. Check if it is intended to be dangling. [WARNING RSZ-0104] Net _499_ only has one pin. Check if it is intended to be dangling. [WARNING RSZ-0104] Net _498_ only has one pin. Check if it is intended to be dangling. [WARNING RSZ-0104] Net _497_ only has one pin. Check if it is intended to be dangling. 560 | +0.0% | 0 | 0 | 0 | 90 [WARNING RSZ-0104] Net _496_ only has one pin. Check if it is intended to be dangling. [WARNING RSZ-0104] Net _503_ only has one pin. Check if it is intended to be dangling. [WARNING RSZ-0104] Net _486_ only has one pin. Check if it is intended to be dangling. [WARNING RSZ-0104] Net _502_ only has one pin. Check if it is intended to be dangling. [WARNING RSZ-0104] Net _501_ only has one pin. Check if it is intended to be dangling. 570 | +0.0% | 0 | 0 | 0 | 80 580 | +0.0% | 0 | 0 | 0 | 70 590 | +0.0% | 0 | 0 | 0 | 60 600 | +0.0% | 0 | 0 | 0 | 50 610 | +0.0% | 0 | 0 | 0 | 40 620 | +0.0% | 0 | 0 | 0 | 30 630 | +0.0% | 0 | 0 | 0 | 20 640 | +0.0% | 0 | 0 | 0 | 10 650 | +0.0% | 0 | 0 | 0 | 0 final | +0.0% | 0 | 0 | 0 | 0 --------------------------------------------------------------------- [INFO RSZ-0504] Runtime: 1.66s global_route -start_incremental detailed_placement [INFO DPL-0006] Core area: 1161.89 um^2, Instances area: 711.28 um^2, Utilization: 61.2% [INFO DPL-0005] Diamond search max displacement: +/- 500 sites horizontally, +/- 100 rows vertically. [INFO DPL-1101] Legalizing using diamond search. Movements Summary --------------------------------------- Total cells: 579 Diamond Move Success: 579 (100.00%) Diamond Move Failure: 0 Rip-up and replace Success: 0 ( 0.00% of diamond failures) Rip-up and replace Failure: 0 Total Placement Failures: 0 --------------------------------------- [INFO DPL-0500] Runtime: 0.01s Placement Analysis --------------------------------- total displacement 0.0 u average displacement 0.0 u max displacement 0.0 u original HPWL 3113.7 u legalized HPWL 3113.7 u delta HPWL 0 % global_route -end_incremental -congestion_report_file ./reports/nangate45/gcd/rt_min3/congestion_post_repair_design.rpt Repair setup and hold violations... estimate_parasitics -global_routing repair_timing -setup_margin 0 -hold_margin 0 -repair_tns 100 -verbose [INFO RSZ-0100] Repair move sequence: UnbufferMove SizeUpMove SwapPinsMove BufferMove CloneMove SplitLoadMove [INFO RSZ-0094] Found 5 endpoints with setup violations. [INFO RSZ-0099] Repairing 5 out of 5 (100.00%) violating endpoints... Iter | Removed | Resized | Inserted | Cloned | Pin | Area | WNS | StTNS | EnTNS | Viol | Worst | Buffers | Gates | Buffers | Gates | Swaps | | | | | Endpts | St/EnPt ------------------------------------------------------------------------------------------------------------------------------ 0* | 0 | 0 | 0 | 0 | 0 | +0.0% | -0.016 | -0.1 | -0.0 | 5 | resp_msg[11] 4* | 0 | 3 | 0 | 0 | 0 | +0.2% | -0.011 | -0.0 | -0.0 | 5 | resp_msg[13] 8* | 0 | 6 | 0 | 0 | 0 | +0.5% | -0.009 | -0.0 | -0.0 | 5 | resp_msg[13] 10* | 0 | 7 | 0 | 0 | 0 | +0.6% | -0.010 | -0.0 | -0.0 | 5 | resp_msg[13] 14* | 0 | 11 | 0 | 0 | 0 | +0.9% | -0.006 | -0.0 | -0.0 | 5 | resp_msg[12] 17* | 0 | 13 | 0 | 0 | 0 | +1.0% | -0.005 | -0.0 | -0.0 | 5 | dpath.a_reg.out\[10\]$_DFFE_PP_/D 20* | 0 | 13 | 1 | 0 | 1 | +1.5% | 0.000 | 0.0 | 0.0 | 5 | resp_msg[11] 20* | 0 | 13 | 1 | 0 | 1 | +1.5% | 0.000 | 0.0 | 0.0 | 5 | resp_msg[11] 20* | 0 | 13 | 1 | 0 | 1 | +1.5% | 0.000 | 0.0 | 0.0 | 5 | resp_msg[11] final | 0 | 13 | 1 | 0 | 1 | +1.5% | 0.000 | 0.0 | 0.0 | 0 | resp_msg[11] ------------------------------------------------------------------------------------------------------------------------------ [INFO RSZ-0040] Inserted 1 buffers. [INFO RSZ-0051] Resized 13 instances: 13 up, 0 up match, 0 down, 0 VT [INFO RSZ-0043] Swapped pins on 1 instances. [INFO RSZ-0505] Runtime: 2.88s [INFO RSZ-0033] No hold violations found. [INFO RSZ-0506] Runtime: 0.07s global_route -start_incremental detailed_placement [INFO DPL-0006] Core area: 1161.89 um^2, Instances area: 722.19 um^2, Utilization: 62.2% [INFO DPL-0005] Diamond search max displacement: +/- 500 sites horizontally, +/- 100 rows vertically. [INFO DPL-1101] Legalizing using diamond search. Movements Summary --------------------------------------- Total cells: 580 Diamond Move Success: 580 (100.00%) Diamond Move Failure: 0 Rip-up and replace Success: 0 ( 0.00% of diamond failures) Rip-up and replace Failure: 0 Total Placement Failures: 0 --------------------------------------- [INFO DPL-0500] Runtime: 0.01s Placement Analysis --------------------------------- total displacement 21.5 u average displacement 0.0 u max displacement 2.4 u original HPWL 3120.1 u legalized HPWL 3136.5 u delta HPWL 1 % check_placement -verbose global_route -end_incremental -congestion_report_file ./reports/nangate45/gcd/rt_min3/congestion_post_repair_timing.rpt estimate_parasitics -global_routing global_route -start_incremental global_route -end_incremental -congestion_report_file ./reports/nangate45/gcd/rt_min3/congestion_post_recover_power.rpt Repair antennas... [WARNING GRT-0246] No diode with LEF class CORE ANTENNACELL found. [INFO ANT-0002] Found 0 net violations. [INFO ANT-0001] Found 0 pin violations. Estimate parasitics... estimate_parasitics -global_routing Report metrics stage 5, global route... ========================================================================== global route report_design_area -------------------------------------------------------------------------- Design area 722 um^2 62% utilization. [INFO FLW-0007] clock core_clock period 0.460000 [WARNING FLW-0010] more than one clock found. Skipping sdc update. [INFO FLW-0011] Path endpoint path count 75 write_db ./results/nangate45/gcd/rt_min3/5_1_grt.odb write_sdc -no_timestamp ./results/nangate45/gcd/rt_min3/5_1_grt.sdc Elapsed time: 0:07.52[h:]min:sec. CPU time: user 40.39 sys 0.19 (539%). Peak memory: 294648KB. Log Ext Elapsed/s Peak Memory/MB sha1sum result [0:20) 5_1_grt .odb 7 287 da68a06692fbeb7ce6aa 5_1_grt .sdc 6dc41493824210708c18 /OpenROAD-flow-scripts/flow/scripts/flow.sh 5_2_route detail_route Running detail_route.tcl, stage 5_2_route read_liberty /OpenROAD-flow-scripts/flow/platforms/nangate45/lib/NangateOpenCellLibrary_typical.lib read_db ./results/nangate45/gcd/rt_min3/5_1_grt.odb read_sdc ./results/nangate45/gcd/rt_min3/5_1_grt.sdc source /OpenROAD-flow-scripts/flow/platforms/nangate45/setRC.tcl [WARNING STA-0450] virtual clock vclk_core_clock can not be propagated. detailed_route -output_drc ./reports/nangate45/gcd/rt_min3/5_route_drc.rpt -output_maze ./results/nangate45/gcd/rt_min3/maze.log -droute_end_iter 64 -verbose 1 -drc_report_iter_step 5 [INFO DRT-0149] Reading tech and libs. Units: 2000 Number of layers: 21 Number of macros: 135 Number of vias: 33 Number of viarulegen: 19 [INFO DRT-0150] Reading design. Design: gcd Die area: ( 0 0 ) ( 73450 73450 ) Number of track patterns: 20 Number of DEF vias: 0 Number of components: 628 Number of terminals: 54 Number of snets: 2 Number of nets: 648 [INFO DRT-0167] List of default vias: Layer via3 default via: via3_2 Layer via4 default via: via4_0 Layer via5 default via: via5_0 Layer via6 default via: via6_0 Layer via7 default via: via7_0 Layer via8 default via: via8_0 Layer via9 default via: via9_0 [INFO DRT-0162] Library cell analysis. [INFO DRT-0163] Instance analysis. [INFO DRT-0164] Number of unique instances = 61. [INFO DRT-0168] Init region query. [INFO DRT-0024] Complete active. [INFO DRT-0024] Complete Fr_VIA. [INFO DRT-0024] Complete metal1. [INFO DRT-0024] Complete via1. [INFO DRT-0024] Complete metal2. [INFO DRT-0024] Complete via2. [INFO DRT-0024] Complete metal3. [INFO DRT-0024] Complete via3. [INFO DRT-0024] Complete metal4. [INFO DRT-0024] Complete via4. [INFO DRT-0024] Complete metal5. [INFO DRT-0024] Complete via5. [INFO DRT-0024] Complete metal6. [INFO DRT-0024] Complete via6. [INFO DRT-0024] Complete metal7. [INFO DRT-0024] Complete via7. [INFO DRT-0024] Complete metal8. [INFO DRT-0024] Complete via8. [INFO DRT-0024] Complete metal9. [INFO DRT-0024] Complete via9. [INFO DRT-0024] Complete metal10. [INFO DRT-0033] active shape region query size = 0. [INFO DRT-0033] FR_VIA shape region query size = 0. [INFO DRT-0033] metal1 shape region query size = 8375. [INFO DRT-0033] via1 shape region query size = 114. [INFO DRT-0033] metal2 shape region query size = 76. [INFO DRT-0033] via2 shape region query size = 114. [INFO DRT-0033] metal3 shape region query size = 76. [INFO DRT-0033] via3 shape region query size = 114. [INFO DRT-0033] metal4 shape region query size = 47. [INFO DRT-0033] via4 shape region query size = 60. [INFO DRT-0033] metal5 shape region query size = 37. [INFO DRT-0033] via5 shape region query size = 60. [INFO DRT-0033] metal6 shape region query size = 41. [INFO DRT-0033] via6 shape region query size = 24. [INFO DRT-0033] metal7 shape region query size = 9. [INFO DRT-0033] via7 shape region query size = 0. [INFO DRT-0033] metal8 shape region query size = 0. [INFO DRT-0033] via8 shape region query size = 0. [INFO DRT-0033] metal9 shape region query size = 0. [INFO DRT-0033] via9 shape region query size = 0. [INFO DRT-0033] metal10 shape region query size = 0. [INFO DRT-0165] Start pin access. [INFO DRT-0078] Complete 302 pins. [INFO DRT-0081] Complete 61 unique inst patterns. [INFO DRT-0084] Complete 248 groups. #scanned instances = 628 #unique instances = 61 #stdCellGenAp = 1435 #stdCellValidPlanarAp = 0 #stdCellValidViaAp = 1048 #stdCellPinNoAp = 0 #stdCellPinCnt = 1759 #instTermValidViaApCnt = 0 #macroGenAp = 0 #macroValidPlanarAp = 0 #macroValidViaAp = 0 #macroNoAp = 0 [INFO DRT-0166] Complete pin access. [INFO DRT-0267] cpu time = 00:00:07, elapsed time = 00:00:01, memory = 259.04 (MB), peak = 255.95 (MB) [INFO DRT-0157] Number of guides: 5141 [INFO DRT-0169] Post process guides. [INFO DRT-0176] GCELLGRID X 0 DO 12 STEP 5700 ; [INFO DRT-0177] GCELLGRID Y 0 DO 12 STEP 5700 ; [INFO DRT-0028] Complete active. [INFO DRT-0028] Complete Fr_VIA. [INFO DRT-0028] Complete metal1. [INFO DRT-0028] Complete via1. [INFO DRT-0028] Complete metal2. [INFO DRT-0028] Complete via2. [INFO DRT-0028] Complete metal3. [INFO DRT-0028] Complete via3. [INFO DRT-0028] Complete metal4. [INFO DRT-0028] Complete via4. [INFO DRT-0028] Complete metal5. [INFO DRT-0028] Complete via5. [INFO DRT-0028] Complete metal6. [INFO DRT-0028] Complete via6. [INFO DRT-0028] Complete metal7. [INFO DRT-0028] Complete via7. [INFO DRT-0028] Complete metal8. [INFO DRT-0028] Complete via8. [INFO DRT-0028] Complete metal9. [INFO DRT-0028] Complete via9. [INFO DRT-0028] Complete metal10. [INFO DRT-0178] Init guide query. [INFO DRT-0035] Complete active (guide). [INFO DRT-0035] Complete Fr_VIA (guide). [INFO DRT-0035] Complete metal1 (guide). [INFO DRT-0035] Complete via1 (guide). [INFO DRT-0035] Complete metal2 (guide). [INFO DRT-0035] Complete via2 (guide). [INFO DRT-0035] Complete metal3 (guide). [INFO DRT-0035] Complete via3 (guide). [INFO DRT-0035] Complete metal4 (guide). [INFO DRT-0035] Complete via4 (guide). [INFO DRT-0035] Complete metal5 (guide). [INFO DRT-0035] Complete via5 (guide). [INFO DRT-0035] Complete metal6 (guide). [INFO DRT-0035] Complete via6 (guide). [INFO DRT-0035] Complete metal7 (guide). [INFO DRT-0035] Complete via7 (guide). [INFO DRT-0035] Complete metal8 (guide). [INFO DRT-0035] Complete via8 (guide). [INFO DRT-0035] Complete metal9 (guide). [INFO DRT-0035] Complete via9 (guide). [INFO DRT-0035] Complete metal10 (guide). [INFO DRT-0036] active guide region query size = 0. [INFO DRT-0036] FR_VIA guide region query size = 0. [INFO DRT-0036] metal1 guide region query size = 1314. [INFO DRT-0036] via1 guide region query size = 0. [INFO DRT-0036] metal2 guide region query size = 1096. [INFO DRT-0036] via2 guide region query size = 0. [INFO DRT-0036] metal3 guide region query size = 944. [INFO DRT-0036] via3 guide region query size = 0. [INFO DRT-0036] metal4 guide region query size = 463. [INFO DRT-0036] via4 guide region query size = 0. [INFO DRT-0036] metal5 guide region query size = 117. [INFO DRT-0036] via5 guide region query size = 0. [INFO DRT-0036] metal6 guide region query size = 59. [INFO DRT-0036] via6 guide region query size = 0. [INFO DRT-0036] metal7 guide region query size = 1. [INFO DRT-0036] via7 guide region query size = 0. [INFO DRT-0036] metal8 guide region query size = 0. [INFO DRT-0036] via8 guide region query size = 0. [INFO DRT-0036] metal9 guide region query size = 0. [INFO DRT-0036] via9 guide region query size = 0. [INFO DRT-0036] metal10 guide region query size = 0. [INFO DRT-0179] Init gr pin query. [INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 260.45 (MB), peak = 257.20 (MB) [INFO DRT-0245] skipped writing guide updates to database. [INFO DRT-0181] Start track assignment. [INFO DRT-0184] Done with 1618 vertical wires in 1 frboxes and 2376 horizontal wires in 1 frboxes. [INFO DRT-0186] Done with 396 vertical wires in 1 frboxes and 437 horizontal wires in 1 frboxes. [INFO DRT-0182] Complete track assignment. [INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 268.22 (MB), peak = 265.11 (MB) [INFO DRT-0187] Start routing data preparation. [INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 268.26 (MB), peak = 265.11 (MB) [INFO DRT-0194] Start detail routing. [INFO DRT-0195] Start 0th optimization iteration. Completing 20% with 0 violations. elapsed time = 00:00:04, memory = 281.07 (MB). Completing 50% with 190 violations. elapsed time = 00:00:08, memory = 307.36 (MB). Completing 70% with 349 violations. elapsed time = 00:00:10, memory = 331.36 (MB). Completing 100% with 564 violations. elapsed time = 00:00:12, memory = 352.22 (MB). [INFO DRT-0199] Number of violations = 597. Viol/Layer via2 metal3 via3 metal4 metal5 metal6 Cut Spacing 3 0 0 0 0 0 Metal Spacing 0 208 0 0 0 0 Recheck 0 24 0 6 2 1 Short 0 352 1 0 0 0 [INFO DRT-0267] cpu time = 00:00:15, elapsed time = 00:00:12, memory = 906.81 (MB), peak = 902.76 (MB) Total wire length = 3789 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 2258 um. Total wire length on LAYER metal4 = 1147 um. Total wire length on LAYER metal5 = 168 um. Total wire length on LAYER metal6 = 214 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4598. Up-via summary (total 4598): --------------- active 0 metal1 1758 metal2 1758 metal3 891 metal4 119 metal5 72 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4598 [INFO DRT-0195] Start 1st optimization iteration. Completing 20% with 597 violations. elapsed time = 00:00:02, memory = 925.43 (MB). Completing 50% with 594 violations. elapsed time = 00:00:04, memory = 939.64 (MB). Completing 70% with 564 violations. elapsed time = 00:00:07, memory = 965.09 (MB). Completing 100% with 492 violations. elapsed time = 00:00:13, memory = 967.22 (MB). [INFO DRT-0199] Number of violations = 492. Viol/Layer via2 metal3 Cut Spacing 2 0 Metal Spacing 0 215 Short 0 275 [INFO DRT-0267] cpu time = 00:00:16, elapsed time = 00:00:14, memory = 968.36 (MB), peak = 982.03 (MB) Total wire length = 3774 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 2248 um. Total wire length on LAYER metal4 = 1159 um. Total wire length on LAYER metal5 = 173 um. Total wire length on LAYER metal6 = 192 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4614. Up-via summary (total 4614): --------------- active 0 metal1 1763 metal2 1763 metal3 911 metal4 113 metal5 64 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4614 [INFO DRT-0195] Start 2nd optimization iteration. Completing 10% with 492 violations. elapsed time = 00:00:00, memory = 974.55 (MB). Completing 20% with 492 violations. elapsed time = 00:00:00, memory = 979.09 (MB). Completing 30% with 492 violations. elapsed time = 00:00:00, memory = 979.86 (MB). Completing 40% with 492 violations. elapsed time = 00:00:00, memory = 980.15 (MB). Completing 50% with 498 violations. elapsed time = 00:00:00, memory = 985.40 (MB). Completing 60% with 498 violations. elapsed time = 00:00:01, memory = 985.41 (MB). Completing 70% with 512 violations. elapsed time = 00:00:02, memory = 998.26 (MB). Completing 80% with 512 violations. elapsed time = 00:00:04, memory = 1002.33 (MB). Completing 100% with 496 violations. elapsed time = 00:00:12, memory = 1029.95 (MB). [INFO DRT-0199] Number of violations = 496. Viol/Layer via2 metal3 metal4 Cut Spacing 3 0 0 Metal Spacing 0 211 0 Short 0 281 1 [INFO DRT-0267] cpu time = 00:00:16, elapsed time = 00:00:12, memory = 1029.99 (MB), peak = 1045.77 (MB) Total wire length = 3767 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 2241 um. Total wire length on LAYER metal4 = 1170 um. Total wire length on LAYER metal5 = 169 um. Total wire length on LAYER metal6 = 185 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4614. Up-via summary (total 4614): --------------- active 0 metal1 1757 metal2 1757 metal3 913 metal4 124 metal5 63 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4614 [INFO DRT-0195] Start 3rd optimization iteration. Completing 20% with 496 violations. elapsed time = 00:00:31, memory = 1071.49 (MB). Completing 50% with 418 violations. elapsed time = 00:00:40, memory = 1096.77 (MB). Completing 70% with 349 violations. elapsed time = 00:00:52, memory = 1134.17 (MB). Completing 100% with 209 violations. elapsed time = 00:00:58, memory = 1166.93 (MB). [INFO DRT-0199] Number of violations = 209. Viol/Layer metal3 Metal Spacing 157 Short 52 [INFO DRT-0267] cpu time = 00:01:00, elapsed time = 00:00:58, memory = 1166.93 (MB), peak = 1163.09 (MB) Total wire length = 3718 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 2035 um. Total wire length on LAYER metal4 = 1234 um. Total wire length on LAYER metal5 = 283 um. Total wire length on LAYER metal6 = 164 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4731. Up-via summary (total 4731): --------------- active 0 metal1 1757 metal2 1757 metal3 987 metal4 172 metal5 58 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4731 [INFO DRT-0195] Start 4th optimization iteration. Completing 20% with 209 violations. elapsed time = 00:00:09, memory = 1203.25 (MB). Completing 50% with 209 violations. elapsed time = 00:00:17, memory = 1241.38 (MB). Completing 70% with 209 violations. elapsed time = 00:00:33, memory = 1278.94 (MB). Completing 100% with 186 violations. elapsed time = 00:00:46, memory = 1320.75 (MB). [INFO DRT-0199] Number of violations = 186. Viol/Layer metal3 Metal Spacing 149 NS Metal 1 Short 36 [INFO DRT-0267] cpu time = 00:00:48, elapsed time = 00:00:46, memory = 1320.75 (MB), peak = 1316.84 (MB) Total wire length = 3721 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 2005 um. Total wire length on LAYER metal4 = 1239 um. Total wire length on LAYER metal5 = 321 um. Total wire length on LAYER metal6 = 154 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4716. Up-via summary (total 4716): --------------- active 0 metal1 1756 metal2 1756 metal3 972 metal4 178 metal5 54 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4716 [INFO DRT-0195] Start 5th optimization iteration. Completing 20% with 186 violations. elapsed time = 00:00:02, memory = 1329.12 (MB). Completing 50% with 182 violations. elapsed time = 00:00:14, memory = 1329.13 (MB). Completing 70% with 182 violations. elapsed time = 00:00:24, memory = 1364.71 (MB). Completing 100% with 182 violations. elapsed time = 00:00:44, memory = 1415.53 (MB). [INFO DRT-0199] Number of violations = 182. Viol/Layer metal1 metal3 Metal Spacing 1 142 NS Metal 0 1 Short 0 38 [INFO DRT-0267] cpu time = 00:00:46, elapsed time = 00:00:44, memory = 1415.66 (MB), peak = 1421.09 (MB) Total wire length = 3715 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1985 um. Total wire length on LAYER metal4 = 1239 um. Total wire length on LAYER metal5 = 336 um. Total wire length on LAYER metal6 = 153 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4724. Up-via summary (total 4724): --------------- active 0 metal1 1759 metal2 1759 metal3 971 metal4 181 metal5 54 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4724 [INFO DRT-0195] Start 6th optimization iteration. Completing 10% with 182 violations. elapsed time = 00:00:00, memory = 1415.66 (MB). Completing 20% with 182 violations. elapsed time = 00:00:00, memory = 1415.66 (MB). Completing 30% with 182 violations. elapsed time = 00:00:00, memory = 1415.66 (MB). Completing 40% with 182 violations. elapsed time = 00:00:00, memory = 1415.66 (MB). Completing 50% with 182 violations. elapsed time = 00:00:01, memory = 1446.91 (MB). Completing 60% with 182 violations. elapsed time = 00:00:10, memory = 1448.77 (MB). Completing 70% with 182 violations. elapsed time = 00:00:10, memory = 1448.91 (MB). Completing 80% with 182 violations. elapsed time = 00:00:14, memory = 1448.91 (MB). Completing 100% with 182 violations. elapsed time = 00:00:34, memory = 1491.60 (MB). [INFO DRT-0199] Number of violations = 182. Viol/Layer metal1 metal3 Metal Spacing 1 140 NS Metal 0 1 Short 0 40 [INFO DRT-0267] cpu time = 00:00:38, elapsed time = 00:00:34, memory = 1491.60 (MB), peak = 1507.30 (MB) Total wire length = 3711 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1989 um. Total wire length on LAYER metal4 = 1233 um. Total wire length on LAYER metal5 = 334 um. Total wire length on LAYER metal6 = 153 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4720. Up-via summary (total 4720): --------------- active 0 metal1 1759 metal2 1759 metal3 967 metal4 181 metal5 54 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4720 [INFO DRT-0195] Start 7th optimization iteration. Completing 10% with 182 violations. elapsed time = 00:00:00, memory = 1491.61 (MB). Completing 20% with 182 violations. elapsed time = 00:00:00, memory = 1502.01 (MB). Completing 30% with 182 violations. elapsed time = 00:00:00, memory = 1502.04 (MB). Completing 40% with 182 violations. elapsed time = 00:00:00, memory = 1502.04 (MB). Completing 50% with 180 violations. elapsed time = 00:00:02, memory = 1502.04 (MB). Completing 60% with 180 violations. elapsed time = 00:00:05, memory = 1502.04 (MB). Completing 70% with 170 violations. elapsed time = 00:00:09, memory = 1548.49 (MB). Completing 80% with 170 violations. elapsed time = 00:00:15, memory = 1548.59 (MB). Completing 100% with 160 violations. elapsed time = 00:00:39, memory = 1581.94 (MB). [INFO DRT-0199] Number of violations = 160. Viol/Layer metal3 Metal Spacing 145 NS Metal 1 Short 14 [INFO DRT-0267] cpu time = 00:00:48, elapsed time = 00:00:40, memory = 1582.05 (MB), peak = 1588.16 (MB) Total wire length = 3724 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1976 um. Total wire length on LAYER metal4 = 1231 um. Total wire length on LAYER metal5 = 351 um. Total wire length on LAYER metal6 = 165 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4733. Up-via summary (total 4733): --------------- active 0 metal1 1759 metal2 1759 metal3 976 metal4 182 metal5 57 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4733 [INFO DRT-0195] Start 8th optimization iteration. Completing 10% with 160 violations. elapsed time = 00:00:00, memory = 1582.05 (MB). Completing 20% with 160 violations. elapsed time = 00:00:00, memory = 1587.13 (MB). Completing 30% with 160 violations. elapsed time = 00:00:00, memory = 1587.13 (MB). Completing 40% with 160 violations. elapsed time = 00:00:01, memory = 1587.13 (MB). Completing 50% with 158 violations. elapsed time = 00:00:03, memory = 1587.14 (MB). Completing 60% with 158 violations. elapsed time = 00:00:05, memory = 1587.14 (MB). Completing 70% with 158 violations. elapsed time = 00:00:08, memory = 1598.45 (MB). Completing 80% with 158 violations. elapsed time = 00:00:10, memory = 1598.63 (MB). Completing 100% with 156 violations. elapsed time = 00:00:37, memory = 1643.75 (MB). [INFO DRT-0199] Number of violations = 156. Viol/Layer metal3 Metal Spacing 142 NS Metal 1 Short 13 [INFO DRT-0267] cpu time = 00:00:44, elapsed time = 00:00:37, memory = 1643.75 (MB), peak = 1659.79 (MB) Total wire length = 3722 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1977 um. Total wire length on LAYER metal4 = 1226 um. Total wire length on LAYER metal5 = 353 um. Total wire length on LAYER metal6 = 165 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4732. Up-via summary (total 4732): --------------- active 0 metal1 1759 metal2 1759 metal3 973 metal4 184 metal5 57 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4732 [INFO DRT-0195] Start 9th optimization iteration. Completing 10% with 156 violations. elapsed time = 00:00:00, memory = 1643.75 (MB). Completing 20% with 156 violations. elapsed time = 00:00:00, memory = 1643.78 (MB). Completing 30% with 156 violations. elapsed time = 00:00:00, memory = 1652.02 (MB). Completing 40% with 156 violations. elapsed time = 00:00:03, memory = 1663.35 (MB). Completing 50% with 156 violations. elapsed time = 00:00:03, memory = 1663.35 (MB). Completing 60% with 156 violations. elapsed time = 00:00:11, memory = 1663.36 (MB). Completing 70% with 154 violations. elapsed time = 00:00:12, memory = 1685.27 (MB). Completing 80% with 154 violations. elapsed time = 00:00:18, memory = 1692.77 (MB). Completing 100% with 153 violations. elapsed time = 00:01:02, memory = 1740.86 (MB). [INFO DRT-0199] Number of violations = 153. Viol/Layer metal3 Metal Spacing 136 NS Metal 1 Short 16 [INFO DRT-0267] cpu time = 00:01:05, elapsed time = 00:01:02, memory = 1740.86 (MB), peak = 1751.06 (MB) Total wire length = 3711 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1964 um. Total wire length on LAYER metal4 = 1226 um. Total wire length on LAYER metal5 = 354 um. Total wire length on LAYER metal6 = 165 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4748. Up-via summary (total 4748): --------------- active 0 metal1 1760 metal2 1760 metal3 984 metal4 187 metal5 57 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4748 [INFO DRT-0195] Start 10th optimization iteration. Completing 20% with 153 violations. elapsed time = 00:00:46, memory = 1727.87 (MB). Completing 50% with 153 violations. elapsed time = 00:00:53, memory = 1706.93 (MB). Completing 70% with 144 violations. elapsed time = 00:01:09, memory = 1754.06 (MB). Completing 100% with 141 violations. elapsed time = 00:01:19, memory = 1754.06 (MB). [INFO DRT-0199] Number of violations = 141. Viol/Layer metal3 Metal Spacing 135 Short 6 [INFO DRT-0267] cpu time = 00:01:22, elapsed time = 00:01:20, memory = 1754.06 (MB), peak = 1768.76 (MB) Total wire length = 3706 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1962 um. Total wire length on LAYER metal4 = 1225 um. Total wire length on LAYER metal5 = 336 um. Total wire length on LAYER metal6 = 180 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4745. Up-via summary (total 4745): --------------- active 0 metal1 1760 metal2 1760 metal3 984 metal4 179 metal5 62 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4745 [INFO DRT-0195] Start 11th optimization iteration. Completing 20% with 141 violations. elapsed time = 00:00:20, memory = 1767.44 (MB). Completing 50% with 141 violations. elapsed time = 00:00:30, memory = 1803.90 (MB). Completing 70% with 141 violations. elapsed time = 00:00:52, memory = 1815.03 (MB). Completing 100% with 141 violations. elapsed time = 00:01:10, memory = 1780.04 (MB). [INFO DRT-0199] Number of violations = 141. Viol/Layer metal3 Metal Spacing 135 Short 6 [INFO DRT-0267] cpu time = 00:01:11, elapsed time = 00:01:10, memory = 1780.04 (MB), peak = 1813.30 (MB) Total wire length = 3706 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1962 um. Total wire length on LAYER metal4 = 1225 um. Total wire length on LAYER metal5 = 336 um. Total wire length on LAYER metal6 = 180 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4745. Up-via summary (total 4745): --------------- active 0 metal1 1760 metal2 1760 metal3 984 metal4 179 metal5 62 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4745 [INFO DRT-0195] Start 12th optimization iteration. Completing 20% with 141 violations. elapsed time = 00:00:06, memory = 1780.04 (MB). Completing 50% with 141 violations. elapsed time = 00:00:16, memory = 1805.87 (MB). Completing 70% with 133 violations. elapsed time = 00:00:34, memory = 1793.53 (MB). Completing 100% with 133 violations. elapsed time = 00:00:59, memory = 1800.03 (MB). [INFO DRT-0199] Number of violations = 133. Viol/Layer metal3 Metal Spacing 129 Short 4 [INFO DRT-0267] cpu time = 00:01:01, elapsed time = 00:00:59, memory = 1802.90 (MB), peak = 1824.20 (MB) Total wire length = 3702 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1960 um. Total wire length on LAYER metal4 = 1219 um. Total wire length on LAYER metal5 = 340 um. Total wire length on LAYER metal6 = 181 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4750. Up-via summary (total 4750): --------------- active 0 metal1 1760 metal2 1760 metal3 987 metal4 181 metal5 62 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4750 [INFO DRT-0195] Start 13th optimization iteration. Completing 10% with 133 violations. elapsed time = 00:00:00, memory = 1802.90 (MB). Completing 20% with 133 violations. elapsed time = 00:00:00, memory = 1802.90 (MB). Completing 30% with 133 violations. elapsed time = 00:00:00, memory = 1802.90 (MB). Completing 40% with 133 violations. elapsed time = 00:00:00, memory = 1802.90 (MB). Completing 50% with 133 violations. elapsed time = 00:00:01, memory = 1810.32 (MB). Completing 60% with 133 violations. elapsed time = 00:00:08, memory = 1810.32 (MB). Completing 70% with 131 violations. elapsed time = 00:00:09, memory = 1810.32 (MB). Completing 80% with 131 violations. elapsed time = 00:00:16, memory = 1810.84 (MB). Completing 100% with 131 violations. elapsed time = 00:00:39, memory = 1818.85 (MB). [INFO DRT-0199] Number of violations = 131. Viol/Layer metal3 Metal Spacing 125 Short 6 [INFO DRT-0267] cpu time = 00:00:44, elapsed time = 00:00:40, memory = 1818.85 (MB), peak = 1826.50 (MB) Total wire length = 3707 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1952 um. Total wire length on LAYER metal4 = 1230 um. Total wire length on LAYER metal5 = 356 um. Total wire length on LAYER metal6 = 167 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4748. Up-via summary (total 4748): --------------- active 0 metal1 1761 metal2 1761 metal3 985 metal4 181 metal5 60 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4748 [INFO DRT-0195] Start 14th optimization iteration. Completing 10% with 131 violations. elapsed time = 00:00:00, memory = 1818.85 (MB). Completing 20% with 131 violations. elapsed time = 00:00:00, memory = 1825.93 (MB). Completing 30% with 131 violations. elapsed time = 00:00:00, memory = 1825.93 (MB). Completing 40% with 131 violations. elapsed time = 00:00:00, memory = 1826.00 (MB). Completing 50% with 131 violations. elapsed time = 00:00:02, memory = 1838.12 (MB). Completing 60% with 131 violations. elapsed time = 00:00:03, memory = 1838.12 (MB). Completing 70% with 131 violations. elapsed time = 00:00:07, memory = 1864.44 (MB). Completing 80% with 131 violations. elapsed time = 00:00:12, memory = 1864.46 (MB). Completing 100% with 126 violations. elapsed time = 00:00:45, memory = 1885.10 (MB). [INFO DRT-0199] Number of violations = 126. Viol/Layer metal3 Metal Spacing 120 Short 6 [INFO DRT-0267] cpu time = 00:00:53, elapsed time = 00:00:45, memory = 1885.10 (MB), peak = 1892.99 (MB) Total wire length = 3707 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1946 um. Total wire length on LAYER metal4 = 1230 um. Total wire length on LAYER metal5 = 362 um. Total wire length on LAYER metal6 = 167 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4752. Up-via summary (total 4752): --------------- active 0 metal1 1761 metal2 1761 metal3 985 metal4 185 metal5 60 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4752 [INFO DRT-0195] Start 15th optimization iteration. Completing 10% with 126 violations. elapsed time = 00:00:00, memory = 1885.10 (MB). Completing 20% with 126 violations. elapsed time = 00:00:00, memory = 1891.01 (MB). Completing 30% with 126 violations. elapsed time = 00:00:00, memory = 1891.35 (MB). Completing 40% with 126 violations. elapsed time = 00:00:02, memory = 1891.36 (MB). Completing 50% with 126 violations. elapsed time = 00:00:02, memory = 1891.36 (MB). Completing 60% with 126 violations. elapsed time = 00:00:07, memory = 1891.36 (MB). Completing 70% with 126 violations. elapsed time = 00:00:09, memory = 1903.57 (MB). Completing 80% with 126 violations. elapsed time = 00:00:09, memory = 1903.57 (MB). Completing 100% with 124 violations. elapsed time = 00:00:45, memory = 1904.34 (MB). [INFO DRT-0199] Number of violations = 124. Viol/Layer metal3 Metal Spacing 118 Short 6 [INFO DRT-0267] cpu time = 00:00:51, elapsed time = 00:00:45, memory = 1904.34 (MB), peak = 1914.77 (MB) Total wire length = 3708 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1936 um. Total wire length on LAYER metal4 = 1232 um. Total wire length on LAYER metal5 = 372 um. Total wire length on LAYER metal6 = 167 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4752. Up-via summary (total 4752): --------------- active 0 metal1 1761 metal2 1761 metal3 981 metal4 189 metal5 60 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4752 [INFO DRT-0195] Start 16th optimization iteration. Completing 10% with 124 violations. elapsed time = 00:00:00, memory = 1904.34 (MB). Completing 20% with 124 violations. elapsed time = 00:00:00, memory = 1904.34 (MB). Completing 30% with 124 violations. elapsed time = 00:00:00, memory = 1904.34 (MB). Completing 40% with 124 violations. elapsed time = 00:00:05, memory = 1904.34 (MB). Completing 50% with 122 violations. elapsed time = 00:00:05, memory = 1904.34 (MB). Completing 60% with 122 violations. elapsed time = 00:00:15, memory = 1917.57 (MB). Completing 70% with 122 violations. elapsed time = 00:00:16, memory = 1917.60 (MB). Completing 80% with 122 violations. elapsed time = 00:00:18, memory = 1917.60 (MB). Completing 100% with 122 violations. elapsed time = 00:01:13, memory = 1958.58 (MB). [INFO DRT-0199] Number of violations = 122. Viol/Layer metal3 Metal Spacing 116 Short 6 [INFO DRT-0267] cpu time = 00:01:16, elapsed time = 00:01:13, memory = 1958.58 (MB), peak = 1969.44 (MB) Total wire length = 3709 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1937 um. Total wire length on LAYER metal4 = 1232 um. Total wire length on LAYER metal5 = 372 um. Total wire length on LAYER metal6 = 167 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4752. Up-via summary (total 4752): --------------- active 0 metal1 1761 metal2 1761 metal3 981 metal4 189 metal5 60 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4752 [INFO DRT-0195] Start 17th optimization iteration. Completing 10% with 122 violations. elapsed time = 00:00:00, memory = 1958.58 (MB). Completing 20% with 122 violations. elapsed time = 00:00:00, memory = 1958.58 (MB). Completing 30% with 122 violations. elapsed time = 00:00:00, memory = 1958.59 (MB). Completing 40% with 122 violations. elapsed time = 00:00:01, memory = 1958.59 (MB). Completing 50% with 133 violations. elapsed time = 00:00:03, memory = 1958.59 (MB). Completing 60% with 133 violations. elapsed time = 00:00:11, memory = 1958.59 (MB). Completing 70% with 176 violations. elapsed time = 00:00:13, memory = 1958.60 (MB). Completing 80% with 176 violations. elapsed time = 00:00:22, memory = 1958.60 (MB). Completing 100% with 288 violations. elapsed time = 00:00:50, memory = 2009.28 (MB). [INFO DRT-0199] Number of violations = 288. Viol/Layer metal3 Metal Spacing 181 Short 107 [INFO DRT-0267] cpu time = 00:00:56, elapsed time = 00:00:50, memory = 2009.33 (MB), peak = 2004.78 (MB) Total wire length = 3741 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1977 um. Total wire length on LAYER metal4 = 1264 um. Total wire length on LAYER metal5 = 366 um. Total wire length on LAYER metal6 = 133 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4758. Up-via summary (total 4758): --------------- active 0 metal1 1755 metal2 1755 metal3 1013 metal4 185 metal5 50 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4758 [INFO DRT-0195] Start 18th optimization iteration. Completing 20% with 288 violations. elapsed time = 00:00:48, memory = 2056.66 (MB). Completing 50% with 225 violations. elapsed time = 00:01:11, memory = 2058.54 (MB). Completing 70% with 206 violations. elapsed time = 00:01:28, memory = 2032.99 (MB). Completing 100% with 150 violations. elapsed time = 00:01:39, memory = 2032.99 (MB). [INFO DRT-0199] Number of violations = 150. Viol/Layer metal3 Metal Spacing 138 Short 12 [INFO DRT-0267] cpu time = 00:01:41, elapsed time = 00:01:39, memory = 2032.99 (MB), peak = 2066.28 (MB) Total wire length = 3719 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1934 um. Total wire length on LAYER metal4 = 1265 um. Total wire length on LAYER metal5 = 395 um. Total wire length on LAYER metal6 = 125 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4766. Up-via summary (total 4766): --------------- active 0 metal1 1757 metal2 1757 metal3 1014 metal4 191 metal5 47 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4766 [INFO DRT-0195] Start 19th optimization iteration. Completing 20% with 150 violations. elapsed time = 00:00:27, memory = 2032.99 (MB). Completing 50% with 150 violations. elapsed time = 00:00:45, memory = 2032.99 (MB). Completing 70% with 143 violations. elapsed time = 00:01:07, memory = 2049.30 (MB). Completing 100% with 136 violations. elapsed time = 00:01:26, memory = 2054.23 (MB). [INFO DRT-0199] Number of violations = 136. Viol/Layer metal3 Metal Spacing 125 Short 11 [INFO DRT-0267] cpu time = 00:01:28, elapsed time = 00:01:26, memory = 2054.23 (MB), peak = 2066.28 (MB) Total wire length = 3721 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1942 um. Total wire length on LAYER metal4 = 1260 um. Total wire length on LAYER metal5 = 395 um. Total wire length on LAYER metal6 = 123 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4774. Up-via summary (total 4774): --------------- active 0 metal1 1756 metal2 1756 metal3 1024 metal4 189 metal5 49 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4774 [INFO DRT-0195] Start 20th optimization iteration. Completing 20% with 136 violations. elapsed time = 00:00:09, memory = 2054.23 (MB). Completing 50% with 134 violations. elapsed time = 00:00:25, memory = 2061.64 (MB). Completing 70% with 134 violations. elapsed time = 00:00:40, memory = 2061.64 (MB). Completing 100% with 133 violations. elapsed time = 00:01:09, memory = 2061.64 (MB). [INFO DRT-0199] Number of violations = 133. Viol/Layer metal3 Metal Spacing 121 Short 12 [INFO DRT-0267] cpu time = 00:01:11, elapsed time = 00:01:09, memory = 2061.64 (MB), peak = 2075.82 (MB) Total wire length = 3717 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1935 um. Total wire length on LAYER metal4 = 1249 um. Total wire length on LAYER metal5 = 394 um. Total wire length on LAYER metal6 = 137 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4774. Up-via summary (total 4774): --------------- active 0 metal1 1754 metal2 1754 metal3 1021 metal4 193 metal5 52 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4774 [INFO DRT-0195] Start 21st optimization iteration. Completing 10% with 133 violations. elapsed time = 00:00:00, memory = 2061.64 (MB). Completing 20% with 133 violations. elapsed time = 00:00:00, memory = 2061.64 (MB). Completing 30% with 133 violations. elapsed time = 00:00:00, memory = 2061.64 (MB). Completing 40% with 133 violations. elapsed time = 00:00:00, memory = 2061.64 (MB). Completing 50% with 130 violations. elapsed time = 00:00:01, memory = 2070.36 (MB). Completing 60% with 130 violations. elapsed time = 00:00:18, memory = 2087.38 (MB). Completing 70% with 126 violations. elapsed time = 00:00:20, memory = 2087.38 (MB). Completing 80% with 126 violations. elapsed time = 00:00:34, memory = 2087.38 (MB). Completing 100% with 126 violations. elapsed time = 00:01:13, memory = 2099.43 (MB). [INFO DRT-0199] Number of violations = 126. Viol/Layer metal3 Metal Spacing 118 Short 8 [INFO DRT-0267] cpu time = 00:01:18, elapsed time = 00:01:13, memory = 2053.70 (MB), peak = 2127.29 (MB) Total wire length = 3721 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1922 um. Total wire length on LAYER metal4 = 1252 um. Total wire length on LAYER metal5 = 407 um. Total wire length on LAYER metal6 = 138 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4773. Up-via summary (total 4773): --------------- active 0 metal1 1754 metal2 1754 metal3 1017 metal4 195 metal5 53 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4773 [INFO DRT-0195] Start 22nd optimization iteration. Completing 10% with 126 violations. elapsed time = 00:00:00, memory = 2053.70 (MB). Completing 20% with 126 violations. elapsed time = 00:00:00, memory = 2053.77 (MB). Completing 30% with 126 violations. elapsed time = 00:00:00, memory = 2053.77 (MB). Completing 40% with 126 violations. elapsed time = 00:00:01, memory = 2053.77 (MB). Completing 50% with 121 violations. elapsed time = 00:00:03, memory = 2053.77 (MB). Completing 60% with 121 violations. elapsed time = 00:00:05, memory = 2053.77 (MB). Completing 70% with 117 violations. elapsed time = 00:00:10, memory = 2053.77 (MB). Completing 80% with 117 violations. elapsed time = 00:00:13, memory = 2053.77 (MB). Completing 100% with 113 violations. elapsed time = 00:00:42, memory = 2053.78 (MB). [INFO DRT-0199] Number of violations = 113. Viol/Layer metal3 Metal Spacing 107 Short 6 [INFO DRT-0267] cpu time = 00:00:52, elapsed time = 00:00:42, memory = 2053.78 (MB), peak = 2127.29 (MB) Total wire length = 3719 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1918 um. Total wire length on LAYER metal4 = 1251 um. Total wire length on LAYER metal5 = 407 um. Total wire length on LAYER metal6 = 141 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4777. Up-via summary (total 4777): --------------- active 0 metal1 1754 metal2 1754 metal3 1017 metal4 197 metal5 55 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4777 [INFO DRT-0195] Start 23rd optimization iteration. Completing 10% with 113 violations. elapsed time = 00:00:00, memory = 2053.78 (MB). Completing 20% with 113 violations. elapsed time = 00:00:00, memory = 2053.78 (MB). Completing 30% with 113 violations. elapsed time = 00:00:00, memory = 2053.78 (MB). Completing 40% with 113 violations. elapsed time = 00:00:01, memory = 2053.78 (MB). Completing 50% with 113 violations. elapsed time = 00:00:02, memory = 2053.78 (MB). Completing 60% with 113 violations. elapsed time = 00:00:06, memory = 2053.78 (MB). Completing 70% with 110 violations. elapsed time = 00:00:09, memory = 2053.78 (MB). Completing 80% with 110 violations. elapsed time = 00:00:16, memory = 2053.78 (MB). Completing 100% with 110 violations. elapsed time = 00:00:47, memory = 2071.52 (MB). [INFO DRT-0199] Number of violations = 110. Viol/Layer metal3 Metal Spacing 102 Short 8 [INFO DRT-0267] cpu time = 00:00:55, elapsed time = 00:00:48, memory = 2071.52 (MB), peak = 2127.29 (MB) Total wire length = 3720 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1920 um. Total wire length on LAYER metal4 = 1251 um. Total wire length on LAYER metal5 = 406 um. Total wire length on LAYER metal6 = 141 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4777. Up-via summary (total 4777): --------------- active 0 metal1 1754 metal2 1754 metal3 1017 metal4 197 metal5 55 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4777 [INFO DRT-0195] Start 24th optimization iteration. Completing 10% with 110 violations. elapsed time = 00:00:00, memory = 2071.52 (MB). Completing 20% with 110 violations. elapsed time = 00:00:00, memory = 2073.75 (MB). Completing 30% with 110 violations. elapsed time = 00:00:00, memory = 2073.75 (MB). Completing 40% with 110 violations. elapsed time = 00:00:02, memory = 2073.75 (MB). Completing 50% with 110 violations. elapsed time = 00:00:02, memory = 2073.75 (MB). Completing 60% with 110 violations. elapsed time = 00:00:06, memory = 2073.76 (MB). Completing 70% with 110 violations. elapsed time = 00:00:06, memory = 2073.76 (MB). Completing 80% with 110 violations. elapsed time = 00:00:12, memory = 2094.47 (MB). Completing 100% with 110 violations. elapsed time = 00:00:50, memory = 2144.82 (MB). [INFO DRT-0199] Number of violations = 110. Viol/Layer metal3 Metal Spacing 102 Short 8 [INFO DRT-0267] cpu time = 00:00:52, elapsed time = 00:00:50, memory = 2144.82 (MB), peak = 2172.75 (MB) Total wire length = 3721 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1922 um. Total wire length on LAYER metal4 = 1251 um. Total wire length on LAYER metal5 = 406 um. Total wire length on LAYER metal6 = 141 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4775. Up-via summary (total 4775): --------------- active 0 metal1 1754 metal2 1754 metal3 1015 metal4 197 metal5 55 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4775 [INFO DRT-0195] Start 25th optimization iteration. Completing 10% with 110 violations. elapsed time = 00:00:00, memory = 2151.08 (MB). Completing 20% with 110 violations. elapsed time = 00:00:00, memory = 2155.80 (MB). Completing 30% with 110 violations. elapsed time = 00:00:01, memory = 2155.80 (MB). Completing 40% with 110 violations. elapsed time = 00:00:02, memory = 2155.97 (MB). Completing 50% with 152 violations. elapsed time = 00:00:03, memory = 2155.97 (MB). Completing 60% with 152 violations. elapsed time = 00:00:04, memory = 2155.97 (MB). Completing 70% with 228 violations. elapsed time = 00:00:06, memory = 2155.97 (MB). Completing 80% with 228 violations. elapsed time = 00:00:08, memory = 2155.97 (MB). Completing 100% with 327 violations. elapsed time = 00:00:14, memory = 2155.97 (MB). [INFO DRT-0199] Number of violations = 327. Viol/Layer metal3 Metal Spacing 198 NS Metal 1 Short 128 [INFO DRT-0267] cpu time = 00:00:23, elapsed time = 00:00:14, memory = 2155.97 (MB), peak = 2172.75 (MB) Total wire length = 3727 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1897 um. Total wire length on LAYER metal4 = 1257 um. Total wire length on LAYER metal5 = 438 um. Total wire length on LAYER metal6 = 133 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4775. Up-via summary (total 4775): --------------- active 0 metal1 1753 metal2 1753 metal3 1011 metal4 204 metal5 54 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4775 [INFO DRT-0195] Start 26th optimization iteration. Completing 20% with 327 violations. elapsed time = 00:00:33, memory = 2155.97 (MB). Completing 50% with 285 violations. elapsed time = 00:00:49, memory = 2130.65 (MB). Completing 70% with 244 violations. elapsed time = 00:01:12, memory = 2166.96 (MB). Completing 100% with 185 violations. elapsed time = 00:01:25, memory = 2166.96 (MB). [INFO DRT-0199] Number of violations = 185. Viol/Layer metal3 Metal Spacing 166 Short 19 [INFO DRT-0267] cpu time = 00:01:27, elapsed time = 00:01:25, memory = 2166.96 (MB), peak = 2172.75 (MB) Total wire length = 3721 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1903 um. Total wire length on LAYER metal4 = 1282 um. Total wire length on LAYER metal5 = 422 um. Total wire length on LAYER metal6 = 113 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4785. Up-via summary (total 4785): --------------- active 0 metal1 1752 metal2 1752 metal3 1025 metal4 207 metal5 49 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4785 [INFO DRT-0195] Start 27th optimization iteration. Completing 20% with 185 violations. elapsed time = 00:00:15, memory = 2172.46 (MB). Completing 50% with 185 violations. elapsed time = 00:00:27, memory = 2138.11 (MB). Completing 70% with 181 violations. elapsed time = 00:00:55, memory = 2138.11 (MB). Completing 100% with 168 violations. elapsed time = 00:01:22, memory = 2138.11 (MB). [INFO DRT-0199] Number of violations = 168. Viol/Layer via2 metal3 Cut Spacing 1 0 Metal Spacing 0 147 Short 0 20 [INFO DRT-0267] cpu time = 00:01:24, elapsed time = 00:01:22, memory = 2138.11 (MB), peak = 2175.56 (MB) Total wire length = 3716 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1902 um. Total wire length on LAYER metal4 = 1292 um. Total wire length on LAYER metal5 = 421 um. Total wire length on LAYER metal6 = 100 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4772. Up-via summary (total 4772): --------------- active 0 metal1 1755 metal2 1755 metal3 1018 metal4 199 metal5 45 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4772 [INFO DRT-0195] Start 28th optimization iteration. Completing 20% with 168 violations. elapsed time = 00:00:03, memory = 2138.11 (MB). Completing 50% with 164 violations. elapsed time = 00:00:17, memory = 2138.12 (MB). Completing 70% with 164 violations. elapsed time = 00:00:32, memory = 2138.12 (MB). Completing 100% with 154 violations. elapsed time = 00:01:27, memory = 2138.12 (MB). [INFO DRT-0199] Number of violations = 154. Viol/Layer via2 metal3 Cut Spacing 1 0 Metal Spacing 0 140 Short 0 13 [INFO DRT-0267] cpu time = 00:01:29, elapsed time = 00:01:27, memory = 2138.12 (MB), peak = 2175.56 (MB) Total wire length = 3702 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1909 um. Total wire length on LAYER metal4 = 1296 um. Total wire length on LAYER metal5 = 396 um. Total wire length on LAYER metal6 = 100 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4753. Up-via summary (total 4753): --------------- active 0 metal1 1757 metal2 1757 metal3 1012 metal4 182 metal5 45 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4753 [INFO DRT-0195] Start 29th optimization iteration. Completing 10% with 154 violations. elapsed time = 00:00:00, memory = 2138.12 (MB). Completing 20% with 154 violations. elapsed time = 00:00:00, memory = 2138.12 (MB). Completing 30% with 154 violations. elapsed time = 00:00:00, memory = 2138.12 (MB). Completing 40% with 154 violations. elapsed time = 00:00:01, memory = 2138.12 (MB). Completing 50% with 151 violations. elapsed time = 00:00:01, memory = 2144.91 (MB). Completing 60% with 151 violations. elapsed time = 00:00:10, memory = 2146.13 (MB). Completing 70% with 144 violations. elapsed time = 00:00:11, memory = 2146.13 (MB). Completing 80% with 144 violations. elapsed time = 00:00:20, memory = 2146.13 (MB). Completing 100% with 139 violations. elapsed time = 00:00:59, memory = 2154.22 (MB). [INFO DRT-0199] Number of violations = 139. Viol/Layer metal3 Metal Spacing 132 Short 7 [INFO DRT-0267] cpu time = 00:01:03, elapsed time = 00:00:59, memory = 2154.22 (MB), peak = 2182.57 (MB) Total wire length = 3704 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1903 um. Total wire length on LAYER metal4 = 1308 um. Total wire length on LAYER metal5 = 395 um. Total wire length on LAYER metal6 = 96 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4752. Up-via summary (total 4752): --------------- active 0 metal1 1753 metal2 1753 metal3 1016 metal4 185 metal5 45 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4752 [INFO DRT-0195] Start 30th optimization iteration. Completing 10% with 139 violations. elapsed time = 00:00:00, memory = 2154.22 (MB). Completing 20% with 139 violations. elapsed time = 00:00:00, memory = 2154.22 (MB). Completing 30% with 139 violations. elapsed time = 00:00:00, memory = 2154.22 (MB). Completing 40% with 139 violations. elapsed time = 00:00:00, memory = 2154.22 (MB). Completing 50% with 138 violations. elapsed time = 00:00:03, memory = 2163.08 (MB). Completing 60% with 138 violations. elapsed time = 00:00:09, memory = 2163.08 (MB). Completing 70% with 138 violations. elapsed time = 00:00:15, memory = 2163.08 (MB). Completing 80% with 138 violations. elapsed time = 00:00:18, memory = 2163.08 (MB). Completing 100% with 138 violations. elapsed time = 00:00:50, memory = 2164.33 (MB). [INFO DRT-0199] Number of violations = 138. Viol/Layer metal3 Metal Spacing 128 Short 10 [INFO DRT-0267] cpu time = 00:01:02, elapsed time = 00:00:50, memory = 2164.33 (MB), peak = 2182.57 (MB) Total wire length = 3703 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1899 um. Total wire length on LAYER metal4 = 1309 um. Total wire length on LAYER metal5 = 397 um. Total wire length on LAYER metal6 = 96 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4752. Up-via summary (total 4752): --------------- active 0 metal1 1753 metal2 1753 metal3 1018 metal4 183 metal5 45 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4752 [INFO DRT-0195] Start 31st optimization iteration. Completing 10% with 138 violations. elapsed time = 00:00:00, memory = 2164.33 (MB). Completing 20% with 138 violations. elapsed time = 00:00:00, memory = 2166.26 (MB). Completing 30% with 138 violations. elapsed time = 00:00:00, memory = 2166.26 (MB). Completing 40% with 138 violations. elapsed time = 00:00:01, memory = 2166.26 (MB). Completing 50% with 136 violations. elapsed time = 00:00:02, memory = 2166.26 (MB). Completing 60% with 136 violations. elapsed time = 00:00:08, memory = 2166.26 (MB). Completing 70% with 134 violations. elapsed time = 00:00:10, memory = 2174.58 (MB). Completing 80% with 134 violations. elapsed time = 00:00:15, memory = 2166.26 (MB). Completing 100% with 134 violations. elapsed time = 00:00:48, memory = 2169.00 (MB). [INFO DRT-0199] Number of violations = 134. Viol/Layer metal3 Metal Spacing 124 Short 10 [INFO DRT-0267] cpu time = 00:00:52, elapsed time = 00:00:48, memory = 2169.00 (MB), peak = 2185.53 (MB) Total wire length = 3703 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1899 um. Total wire length on LAYER metal4 = 1309 um. Total wire length on LAYER metal5 = 397 um. Total wire length on LAYER metal6 = 96 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4752. Up-via summary (total 4752): --------------- active 0 metal1 1753 metal2 1753 metal3 1018 metal4 183 metal5 45 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4752 [INFO DRT-0195] Start 32nd optimization iteration. Completing 10% with 134 violations. elapsed time = 00:00:00, memory = 2169.00 (MB). Completing 20% with 134 violations. elapsed time = 00:00:00, memory = 2169.00 (MB). Completing 30% with 134 violations. elapsed time = 00:00:00, memory = 2169.00 (MB). Completing 40% with 134 violations. elapsed time = 00:00:05, memory = 2169.00 (MB). Completing 50% with 134 violations. elapsed time = 00:00:05, memory = 2169.00 (MB). Completing 60% with 134 violations. elapsed time = 00:00:17, memory = 2133.02 (MB). Completing 70% with 134 violations. elapsed time = 00:00:17, memory = 2152.20 (MB). Completing 80% with 134 violations. elapsed time = 00:00:25, memory = 2152.45 (MB). Completing 100% with 134 violations. elapsed time = 00:01:14, memory = 2189.21 (MB). [INFO DRT-0199] Number of violations = 134. Viol/Layer metal3 Metal Spacing 124 Short 10 [INFO DRT-0267] cpu time = 00:01:17, elapsed time = 00:01:15, memory = 2189.21 (MB), peak = 2217.23 (MB) Total wire length = 3704 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1900 um. Total wire length on LAYER metal4 = 1309 um. Total wire length on LAYER metal5 = 397 um. Total wire length on LAYER metal6 = 96 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4752. Up-via summary (total 4752): --------------- active 0 metal1 1753 metal2 1753 metal3 1018 metal4 183 metal5 45 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4752 [INFO DRT-0195] Start 33rd optimization iteration. Completing 10% with 134 violations. elapsed time = 00:00:00, memory = 2189.21 (MB). Completing 20% with 134 violations. elapsed time = 00:00:00, memory = 2189.50 (MB). Completing 30% with 134 violations. elapsed time = 00:00:00, memory = 2189.50 (MB). Completing 40% with 171 violations. elapsed time = 00:00:00, memory = 2189.50 (MB). Completing 50% with 171 violations. elapsed time = 00:00:01, memory = 2189.50 (MB). Completing 60% with 171 violations. elapsed time = 00:00:02, memory = 2189.50 (MB). Completing 70% with 239 violations. elapsed time = 00:00:02, memory = 2191.49 (MB). Completing 80% with 239 violations. elapsed time = 00:00:03, memory = 2191.49 (MB). Completing 90% with 280 violations. elapsed time = 00:00:04, memory = 2191.49 (MB). Completing 100% with 314 violations. elapsed time = 00:00:04, memory = 2191.49 (MB). [INFO DRT-0199] Number of violations = 314. Viol/Layer metal3 metal4 Metal Spacing 173 1 Short 140 0 [INFO DRT-0267] cpu time = 00:00:14, elapsed time = 00:00:04, memory = 2191.49 (MB), peak = 2217.23 (MB) Total wire length = 3764 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1895 um. Total wire length on LAYER metal4 = 1318 um. Total wire length on LAYER metal5 = 450 um. Total wire length on LAYER metal6 = 100 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4832. Up-via summary (total 4832): --------------- active 0 metal1 1755 metal2 1755 metal3 1047 metal4 228 metal5 47 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4832 [INFO DRT-0195] Start 34th optimization iteration. Completing 20% with 314 violations. elapsed time = 00:00:39, memory = 2240.65 (MB). Completing 50% with 277 violations. elapsed time = 00:00:56, memory = 2240.65 (MB). Completing 70% with 231 violations. elapsed time = 00:01:14, memory = 2268.91 (MB). Completing 100% with 142 violations. elapsed time = 00:01:25, memory = 2268.91 (MB). [INFO DRT-0199] Number of violations = 142. Viol/Layer metal3 Metal Spacing 135 Short 7 [INFO DRT-0267] cpu time = 00:01:27, elapsed time = 00:01:25, memory = 2268.91 (MB), peak = 2264.92 (MB) Total wire length = 3738 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1894 um. Total wire length on LAYER metal4 = 1319 um. Total wire length on LAYER metal5 = 429 um. Total wire length on LAYER metal6 = 95 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4790. Up-via summary (total 4790): --------------- active 0 metal1 1754 metal2 1754 metal3 1029 metal4 212 metal5 41 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4790 [INFO DRT-0195] Start 35th optimization iteration. Completing 20% with 142 violations. elapsed time = 00:00:15, memory = 2268.91 (MB). Completing 50% with 137 violations. elapsed time = 00:00:29, memory = 2268.92 (MB). Completing 70% with 137 violations. elapsed time = 00:00:48, memory = 2274.31 (MB). Completing 100% with 130 violations. elapsed time = 00:01:12, memory = 2259.84 (MB). [INFO DRT-0199] Number of violations = 130. Viol/Layer metal3 Metal Spacing 128 Short 2 [INFO DRT-0267] cpu time = 00:01:14, elapsed time = 00:01:12, memory = 2259.84 (MB), peak = 2313.92 (MB) Total wire length = 3730 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1884 um. Total wire length on LAYER metal4 = 1304 um. Total wire length on LAYER metal5 = 436 um. Total wire length on LAYER metal6 = 104 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4788. Up-via summary (total 4788): --------------- active 0 metal1 1754 metal2 1754 metal3 1020 metal4 215 metal5 45 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4788 [INFO DRT-0195] Start 36th optimization iteration. Completing 20% with 130 violations. elapsed time = 00:00:03, memory = 2259.84 (MB). Completing 50% with 130 violations. elapsed time = 00:00:23, memory = 2223.52 (MB). Completing 70% with 130 violations. elapsed time = 00:00:36, memory = 2223.53 (MB). Completing 100% with 129 violations. elapsed time = 00:01:25, memory = 2223.53 (MB). [INFO DRT-0199] Number of violations = 129. Viol/Layer metal3 Metal Spacing 127 Short 2 [INFO DRT-0267] cpu time = 00:01:27, elapsed time = 00:01:25, memory = 2223.53 (MB), peak = 2313.92 (MB) Total wire length = 3729 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1878 um. Total wire length on LAYER metal4 = 1300 um. Total wire length on LAYER metal5 = 438 um. Total wire length on LAYER metal6 = 111 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4788. Up-via summary (total 4788): --------------- active 0 metal1 1754 metal2 1754 metal3 1016 metal4 217 metal5 47 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4788 [INFO DRT-0195] Start 37th optimization iteration. Completing 10% with 129 violations. elapsed time = 00:00:00, memory = 2223.53 (MB). Completing 20% with 129 violations. elapsed time = 00:00:00, memory = 2223.53 (MB). Completing 30% with 129 violations. elapsed time = 00:00:00, memory = 2223.53 (MB). Completing 40% with 129 violations. elapsed time = 00:00:01, memory = 2223.53 (MB). Completing 50% with 128 violations. elapsed time = 00:00:01, memory = 2225.69 (MB). Completing 60% with 128 violations. elapsed time = 00:00:17, memory = 2225.69 (MB). Completing 70% with 128 violations. elapsed time = 00:00:20, memory = 2225.69 (MB). Completing 80% with 128 violations. elapsed time = 00:00:31, memory = 2225.69 (MB). Completing 100% with 128 violations. elapsed time = 00:01:03, memory = 2225.69 (MB). [INFO DRT-0199] Number of violations = 128. Viol/Layer metal3 Metal Spacing 124 Short 4 [INFO DRT-0267] cpu time = 00:01:08, elapsed time = 00:01:03, memory = 2225.69 (MB), peak = 2313.92 (MB) Total wire length = 3732 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1879 um. Total wire length on LAYER metal4 = 1302 um. Total wire length on LAYER metal5 = 438 um. Total wire length on LAYER metal6 = 111 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4790. Up-via summary (total 4790): --------------- active 0 metal1 1754 metal2 1754 metal3 1018 metal4 217 metal5 47 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4790 [INFO DRT-0195] Start 38th optimization iteration. Completing 10% with 128 violations. elapsed time = 00:00:00, memory = 2225.69 (MB). Completing 20% with 128 violations. elapsed time = 00:00:00, memory = 2225.69 (MB). Completing 30% with 128 violations. elapsed time = 00:00:00, memory = 2225.69 (MB). Completing 40% with 128 violations. elapsed time = 00:00:00, memory = 2225.69 (MB). Completing 50% with 124 violations. elapsed time = 00:00:01, memory = 2225.69 (MB). Completing 60% with 124 violations. elapsed time = 00:00:04, memory = 2225.69 (MB). Completing 70% with 122 violations. elapsed time = 00:00:09, memory = 2242.50 (MB). Completing 80% with 122 violations. elapsed time = 00:00:11, memory = 2242.50 (MB). Completing 100% with 122 violations. elapsed time = 00:00:57, memory = 2242.50 (MB). [INFO DRT-0199] Number of violations = 122. Viol/Layer metal3 Metal Spacing 119 Short 3 [INFO DRT-0267] cpu time = 00:01:06, elapsed time = 00:00:57, memory = 2242.50 (MB), peak = 2313.92 (MB) Total wire length = 3733 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1881 um. Total wire length on LAYER metal4 = 1303 um. Total wire length on LAYER metal5 = 438 um. Total wire length on LAYER metal6 = 111 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4790. Up-via summary (total 4790): --------------- active 0 metal1 1754 metal2 1754 metal3 1018 metal4 217 metal5 47 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4790 [INFO DRT-0195] Start 39th optimization iteration. Completing 10% with 122 violations. elapsed time = 00:00:00, memory = 2242.50 (MB). Completing 20% with 122 violations. elapsed time = 00:00:00, memory = 2242.50 (MB). Completing 30% with 122 violations. elapsed time = 00:00:00, memory = 2242.50 (MB). Completing 40% with 122 violations. elapsed time = 00:00:01, memory = 2242.50 (MB). Completing 50% with 119 violations. elapsed time = 00:00:02, memory = 2242.50 (MB). Completing 60% with 119 violations. elapsed time = 00:00:06, memory = 2242.50 (MB). Completing 70% with 119 violations. elapsed time = 00:00:07, memory = 2251.73 (MB). Completing 80% with 119 violations. elapsed time = 00:00:15, memory = 2242.50 (MB). Completing 100% with 119 violations. elapsed time = 00:01:05, memory = 2242.50 (MB). [INFO DRT-0199] Number of violations = 119. Viol/Layer metal3 Metal Spacing 114 Short 5 [INFO DRT-0267] cpu time = 00:01:09, elapsed time = 00:01:05, memory = 2242.50 (MB), peak = 2313.92 (MB) Total wire length = 3734 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1881 um. Total wire length on LAYER metal4 = 1303 um. Total wire length on LAYER metal5 = 438 um. Total wire length on LAYER metal6 = 111 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4791. Up-via summary (total 4791): --------------- active 0 metal1 1754 metal2 1754 metal3 1019 metal4 217 metal5 47 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4791 [INFO DRT-0195] Start 40th optimization iteration. Completing 10% with 119 violations. elapsed time = 00:00:00, memory = 2242.50 (MB). Completing 20% with 119 violations. elapsed time = 00:00:00, memory = 2242.50 (MB). Completing 30% with 119 violations. elapsed time = 00:00:00, memory = 2242.50 (MB). Completing 40% with 119 violations. elapsed time = 00:00:04, memory = 2242.50 (MB). Completing 50% with 119 violations. elapsed time = 00:00:04, memory = 2242.50 (MB). Completing 60% with 119 violations. elapsed time = 00:00:14, memory = 2242.50 (MB). Completing 70% with 119 violations. elapsed time = 00:00:14, memory = 2242.50 (MB). Completing 80% with 119 violations. elapsed time = 00:00:24, memory = 2242.50 (MB). Completing 100% with 119 violations. elapsed time = 00:01:24, memory = 2259.34 (MB). [INFO DRT-0199] Number of violations = 119. Viol/Layer metal3 Metal Spacing 114 Short 5 [INFO DRT-0267] cpu time = 00:01:26, elapsed time = 00:01:24, memory = 2259.34 (MB), peak = 2313.92 (MB) Total wire length = 3733 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1881 um. Total wire length on LAYER metal4 = 1302 um. Total wire length on LAYER metal5 = 438 um. Total wire length on LAYER metal6 = 111 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4791. Up-via summary (total 4791): --------------- active 0 metal1 1754 metal2 1754 metal3 1019 metal4 217 metal5 47 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4791 [INFO DRT-0195] Start 41st optimization iteration. Completing 10% with 119 violations. elapsed time = 00:00:00, memory = 2259.34 (MB). Completing 20% with 119 violations. elapsed time = 00:00:00, memory = 2259.34 (MB). Completing 30% with 119 violations. elapsed time = 00:00:00, memory = 2259.34 (MB). Completing 40% with 161 violations. elapsed time = 00:00:01, memory = 2259.34 (MB). Completing 50% with 161 violations. elapsed time = 00:00:01, memory = 2259.34 (MB). Completing 60% with 161 violations. elapsed time = 00:00:02, memory = 2259.34 (MB). Completing 70% with 177 violations. elapsed time = 00:00:02, memory = 2263.61 (MB). Completing 80% with 177 violations. elapsed time = 00:00:04, memory = 2265.70 (MB). Completing 90% with 223 violations. elapsed time = 00:00:05, memory = 2265.70 (MB). Completing 100% with 255 violations. elapsed time = 00:00:05, memory = 2265.70 (MB). [INFO DRT-0199] Number of violations = 255. Viol/Layer metal3 Metal Spacing 178 Short 77 [INFO DRT-0267] cpu time = 00:00:16, elapsed time = 00:00:05, memory = 2265.70 (MB), peak = 2313.92 (MB) Total wire length = 3787 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1911 um. Total wire length on LAYER metal4 = 1296 um. Total wire length on LAYER metal5 = 460 um. Total wire length on LAYER metal6 = 119 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4833. Up-via summary (total 4833): --------------- active 0 metal1 1759 metal2 1759 metal3 1032 metal4 232 metal5 51 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4833 [INFO DRT-0195] Start 42nd optimization iteration. Completing 20% with 255 violations. elapsed time = 00:01:13, memory = 2265.70 (MB). Completing 50% with 222 violations. elapsed time = 00:01:46, memory = 2268.94 (MB). Completing 70% with 203 violations. elapsed time = 00:02:27, memory = 2268.94 (MB). Completing 100% with 157 violations. elapsed time = 00:02:47, memory = 2268.94 (MB). [INFO DRT-0199] Number of violations = 157. Viol/Layer via2 metal3 Cut Spacing 1 0 Metal Spacing 0 142 Short 0 14 [INFO DRT-0267] cpu time = 00:02:49, elapsed time = 00:02:47, memory = 2268.94 (MB), peak = 2313.92 (MB) Total wire length = 3736 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1892 um. Total wire length on LAYER metal4 = 1300 um. Total wire length on LAYER metal5 = 428 um. Total wire length on LAYER metal6 = 115 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4793. Up-via summary (total 4793): --------------- active 0 metal1 1758 metal2 1758 metal3 1026 metal4 204 metal5 47 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4793 [INFO DRT-0195] Start 43rd optimization iteration. Completing 20% with 157 violations. elapsed time = 00:00:35, memory = 2294.38 (MB). Completing 50% with 157 violations. elapsed time = 00:00:54, memory = 2294.38 (MB). Completing 70% with 157 violations. elapsed time = 00:01:39, memory = 2301.54 (MB). Completing 100% with 140 violations. elapsed time = 00:02:11, memory = 2288.71 (MB). [INFO DRT-0199] Number of violations = 140. Viol/Layer metal3 Metal Spacing 132 Short 8 [INFO DRT-0267] cpu time = 00:02:13, elapsed time = 00:02:11, memory = 2288.71 (MB), peak = 2345.82 (MB) Total wire length = 3729 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1898 um. Total wire length on LAYER metal4 = 1284 um. Total wire length on LAYER metal5 = 415 um. Total wire length on LAYER metal6 = 131 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4778. Up-via summary (total 4778): --------------- active 0 metal1 1757 metal2 1757 metal3 1027 metal4 187 metal5 50 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4778 [INFO DRT-0195] Start 44th optimization iteration. Completing 20% with 140 violations. elapsed time = 00:00:12, memory = 2288.71 (MB). Completing 50% with 140 violations. elapsed time = 00:00:49, memory = 2288.71 (MB). Completing 70% with 140 violations. elapsed time = 00:01:17, memory = 2288.71 (MB). Completing 100% with 140 violations. elapsed time = 00:02:05, memory = 2288.71 (MB). [INFO DRT-0199] Number of violations = 140. Viol/Layer metal3 Metal Spacing 132 Short 8 [INFO DRT-0267] cpu time = 00:02:06, elapsed time = 00:02:05, memory = 2288.71 (MB), peak = 2345.82 (MB) Total wire length = 3729 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1898 um. Total wire length on LAYER metal4 = 1284 um. Total wire length on LAYER metal5 = 415 um. Total wire length on LAYER metal6 = 131 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4778. Up-via summary (total 4778): --------------- active 0 metal1 1757 metal2 1757 metal3 1027 metal4 187 metal5 50 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4778 [INFO DRT-0195] Start 45th optimization iteration. Completing 10% with 140 violations. elapsed time = 00:00:00, memory = 2288.71 (MB). Completing 20% with 140 violations. elapsed time = 00:00:00, memory = 2288.71 (MB). Completing 30% with 140 violations. elapsed time = 00:00:00, memory = 2290.31 (MB). Completing 40% with 140 violations. elapsed time = 00:00:01, memory = 2290.31 (MB). Completing 50% with 137 violations. elapsed time = 00:00:02, memory = 2299.66 (MB). Completing 60% with 137 violations. elapsed time = 00:00:24, memory = 2290.31 (MB). Completing 70% with 134 violations. elapsed time = 00:00:26, memory = 2300.35 (MB). Completing 80% with 134 violations. elapsed time = 00:00:43, memory = 2290.31 (MB). Completing 100% with 133 violations. elapsed time = 00:01:53, memory = 2291.76 (MB). [INFO DRT-0199] Number of violations = 133. Viol/Layer metal3 Metal Spacing 123 Short 10 [INFO DRT-0267] cpu time = 00:01:58, elapsed time = 00:01:53, memory = 2291.76 (MB), peak = 2345.82 (MB) Total wire length = 3731 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1900 um. Total wire length on LAYER metal4 = 1284 um. Total wire length on LAYER metal5 = 416 um. Total wire length on LAYER metal6 = 129 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4776. Up-via summary (total 4776): --------------- active 0 metal1 1757 metal2 1757 metal3 1023 metal4 189 metal5 50 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4776 [INFO DRT-0195] Start 46th optimization iteration. Completing 10% with 133 violations. elapsed time = 00:00:00, memory = 2291.76 (MB). Completing 20% with 133 violations. elapsed time = 00:00:00, memory = 2291.76 (MB). Completing 30% with 133 violations. elapsed time = 00:00:00, memory = 2291.76 (MB). Completing 40% with 133 violations. elapsed time = 00:00:00, memory = 2291.76 (MB). Completing 50% with 132 violations. elapsed time = 00:00:02, memory = 2298.77 (MB). Completing 60% with 132 violations. elapsed time = 00:00:07, memory = 2298.77 (MB). Completing 70% with 132 violations. elapsed time = 00:00:11, memory = 2298.77 (MB). Completing 80% with 132 violations. elapsed time = 00:00:17, memory = 2298.77 (MB). Completing 100% with 123 violations. elapsed time = 00:01:46, memory = 2298.77 (MB). [INFO DRT-0199] Number of violations = 123. Viol/Layer metal3 Metal Spacing 120 Short 3 [INFO DRT-0267] cpu time = 00:01:55, elapsed time = 00:01:46, memory = 2298.77 (MB), peak = 2345.82 (MB) Total wire length = 3725 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1893 um. Total wire length on LAYER metal4 = 1285 um. Total wire length on LAYER metal5 = 428 um. Total wire length on LAYER metal6 = 118 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4775. Up-via summary (total 4775): --------------- active 0 metal1 1757 metal2 1757 metal3 1027 metal4 187 metal5 47 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4775 [INFO DRT-0195] Start 47th optimization iteration. Completing 10% with 123 violations. elapsed time = 00:00:00, memory = 2298.77 (MB). Completing 20% with 123 violations. elapsed time = 00:00:00, memory = 2298.77 (MB). Completing 30% with 123 violations. elapsed time = 00:00:00, memory = 2298.77 (MB). Completing 40% with 123 violations. elapsed time = 00:00:02, memory = 2298.77 (MB). Completing 50% with 119 violations. elapsed time = 00:00:03, memory = 2298.77 (MB). Completing 60% with 119 violations. elapsed time = 00:00:09, memory = 2298.77 (MB). Completing 70% with 117 violations. elapsed time = 00:00:13, memory = 2307.80 (MB). Completing 80% with 117 violations. elapsed time = 00:00:18, memory = 2298.77 (MB). Completing 100% with 115 violations. elapsed time = 00:01:57, memory = 2306.78 (MB). [INFO DRT-0199] Number of violations = 115. Viol/Layer via2 metal3 Cut Spacing 1 0 Metal Spacing 0 113 Short 0 1 [INFO DRT-0267] cpu time = 00:02:04, elapsed time = 00:01:57, memory = 2306.78 (MB), peak = 2345.82 (MB) Total wire length = 3740 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1919 um. Total wire length on LAYER metal4 = 1286 um. Total wire length on LAYER metal5 = 419 um. Total wire length on LAYER metal6 = 114 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4770. Up-via summary (total 4770): --------------- active 0 metal1 1758 metal2 1758 metal3 1026 metal4 181 metal5 47 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4770 [INFO DRT-0195] Start 48th optimization iteration. Completing 10% with 115 violations. elapsed time = 00:00:00, memory = 2306.78 (MB). Completing 20% with 115 violations. elapsed time = 00:00:00, memory = 2306.78 (MB). Completing 30% with 115 violations. elapsed time = 00:00:00, memory = 2306.78 (MB). Completing 40% with 115 violations. elapsed time = 00:00:07, memory = 2306.78 (MB). Completing 50% with 112 violations. elapsed time = 00:00:07, memory = 2306.78 (MB). Completing 60% with 112 violations. elapsed time = 00:00:25, memory = 2336.62 (MB). Completing 70% with 112 violations. elapsed time = 00:00:25, memory = 2336.62 (MB). Completing 80% with 112 violations. elapsed time = 00:00:36, memory = 2336.62 (MB). Completing 100% with 111 violations. elapsed time = 00:02:10, memory = 2336.62 (MB). [INFO DRT-0199] Number of violations = 111. Viol/Layer metal3 Metal Spacing 110 Short 1 [INFO DRT-0267] cpu time = 00:02:13, elapsed time = 00:02:10, memory = 2336.62 (MB), peak = 2353.76 (MB) Total wire length = 3740 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1919 um. Total wire length on LAYER metal4 = 1288 um. Total wire length on LAYER metal5 = 419 um. Total wire length on LAYER metal6 = 114 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4771. Up-via summary (total 4771): --------------- active 0 metal1 1758 metal2 1758 metal3 1027 metal4 181 metal5 47 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4771 [INFO DRT-0195] Start 49th optimization iteration. Completing 10% with 111 violations. elapsed time = 00:00:00, memory = 2336.62 (MB). Completing 20% with 111 violations. elapsed time = 00:00:01, memory = 2336.62 (MB). Completing 30% with 146 violations. elapsed time = 00:00:01, memory = 2336.62 (MB). Completing 40% with 146 violations. elapsed time = 00:00:02, memory = 2336.62 (MB). Completing 50% with 146 violations. elapsed time = 00:00:02, memory = 2336.62 (MB). Completing 60% with 161 violations. elapsed time = 00:00:03, memory = 2297.28 (MB). Completing 70% with 161 violations. elapsed time = 00:00:04, memory = 2297.28 (MB). Completing 80% with 178 violations. elapsed time = 00:00:04, memory = 2297.28 (MB). Completing 90% with 178 violations. elapsed time = 00:00:05, memory = 2297.28 (MB). Completing 100% with 205 violations. elapsed time = 00:00:06, memory = 2297.28 (MB). [INFO DRT-0199] Number of violations = 205. Viol/Layer metal3 metal4 via4 metal5 Cut Spacing 0 0 1 0 Metal Spacing 141 1 0 0 NS Metal 1 0 0 0 Short 60 0 0 1 [INFO DRT-0267] cpu time = 00:00:18, elapsed time = 00:00:06, memory = 2297.28 (MB), peak = 2353.76 (MB) Total wire length = 3762 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1923 um. Total wire length on LAYER metal4 = 1296 um. Total wire length on LAYER metal5 = 430 um. Total wire length on LAYER metal6 = 111 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4802. Up-via summary (total 4802): --------------- active 0 metal1 1755 metal2 1755 metal3 1039 metal4 206 metal5 47 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4802 [INFO DRT-0195] Start 50th optimization iteration. Completing 20% with 205 violations. elapsed time = 00:02:02, memory = 2297.28 (MB). Completing 50% with 191 violations. elapsed time = 00:02:40, memory = 2302.43 (MB). Completing 70% with 170 violations. elapsed time = 00:03:19, memory = 2303.09 (MB). Completing 100% with 147 violations. elapsed time = 00:03:42, memory = 2317.67 (MB). [INFO DRT-0199] Number of violations = 147. Viol/Layer metal3 Metal Spacing 136 Short 11 [INFO DRT-0267] cpu time = 00:03:44, elapsed time = 00:03:42, memory = 2317.67 (MB), peak = 2353.76 (MB) Total wire length = 3732 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1910 um. Total wire length on LAYER metal4 = 1310 um. Total wire length on LAYER metal5 = 412 um. Total wire length on LAYER metal6 = 99 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4785. Up-via summary (total 4785): --------------- active 0 metal1 1755 metal2 1755 metal3 1043 metal4 191 metal5 41 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4785 [INFO DRT-0195] Start 51st optimization iteration. Completing 20% with 147 violations. elapsed time = 00:01:43, memory = 2317.67 (MB). Completing 50% with 147 violations. elapsed time = 00:02:33, memory = 2317.67 (MB). Completing 70% with 147 violations. elapsed time = 00:03:42, memory = 2317.67 (MB). Completing 100% with 147 violations. elapsed time = 00:04:29, memory = 2317.67 (MB). [INFO DRT-0199] Number of violations = 147. Viol/Layer metal3 Metal Spacing 136 Short 11 [INFO DRT-0267] cpu time = 00:04:30, elapsed time = 00:04:29, memory = 2317.67 (MB), peak = 2353.76 (MB) Total wire length = 3732 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1910 um. Total wire length on LAYER metal4 = 1310 um. Total wire length on LAYER metal5 = 412 um. Total wire length on LAYER metal6 = 99 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4785. Up-via summary (total 4785): --------------- active 0 metal1 1755 metal2 1755 metal3 1043 metal4 191 metal5 41 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4785 [INFO DRT-0195] Start 52nd optimization iteration. Completing 20% with 147 violations. elapsed time = 00:00:17, memory = 2317.67 (MB). Completing 50% with 138 violations. elapsed time = 00:01:22, memory = 2317.67 (MB). Completing 70% with 135 violations. elapsed time = 00:02:23, memory = 2317.67 (MB). Completing 100% with 135 violations. elapsed time = 00:04:02, memory = 2317.67 (MB). [INFO DRT-0199] Number of violations = 135. Viol/Layer metal3 Metal Spacing 129 Short 6 [INFO DRT-0267] cpu time = 00:04:04, elapsed time = 00:04:02, memory = 2317.67 (MB), peak = 2353.76 (MB) Total wire length = 3724 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1888 um. Total wire length on LAYER metal4 = 1297 um. Total wire length on LAYER metal5 = 433 um. Total wire length on LAYER metal6 = 105 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4790. Up-via summary (total 4790): --------------- active 0 metal1 1756 metal2 1756 metal3 1032 metal4 204 metal5 42 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4790 [INFO DRT-0195] Start 53rd optimization iteration. Completing 10% with 135 violations. elapsed time = 00:00:00, memory = 2317.67 (MB). Completing 20% with 135 violations. elapsed time = 00:00:00, memory = 2317.67 (MB). Completing 30% with 135 violations. elapsed time = 00:00:00, memory = 2323.36 (MB). Completing 40% with 135 violations. elapsed time = 00:00:00, memory = 2323.36 (MB). Completing 50% with 132 violations. elapsed time = 00:00:01, memory = 2323.37 (MB). Completing 60% with 132 violations. elapsed time = 00:00:51, memory = 2323.61 (MB). Completing 70% with 130 violations. elapsed time = 00:00:54, memory = 2333.80 (MB). Completing 80% with 130 violations. elapsed time = 00:01:21, memory = 2323.61 (MB). Completing 100% with 117 violations. elapsed time = 00:03:08, memory = 2280.94 (MB). [INFO DRT-0199] Number of violations = 117. Viol/Layer metal3 Metal Spacing 115 Short 2 [INFO DRT-0267] cpu time = 00:03:15, elapsed time = 00:03:08, memory = 2280.94 (MB), peak = 2353.76 (MB) Total wire length = 3722 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1883 um. Total wire length on LAYER metal4 = 1291 um. Total wire length on LAYER metal5 = 435 um. Total wire length on LAYER metal6 = 111 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4787. Up-via summary (total 4787): --------------- active 0 metal1 1755 metal2 1755 metal3 1032 metal4 199 metal5 46 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4787 [INFO DRT-0195] Start 54th optimization iteration. Completing 10% with 117 violations. elapsed time = 00:00:00, memory = 2280.94 (MB). Completing 20% with 117 violations. elapsed time = 00:00:00, memory = 2280.94 (MB). Completing 30% with 117 violations. elapsed time = 00:00:01, memory = 2280.94 (MB). Completing 40% with 117 violations. elapsed time = 00:00:01, memory = 2280.94 (MB). Completing 50% with 117 violations. elapsed time = 00:00:02, memory = 2280.94 (MB). Completing 60% with 117 violations. elapsed time = 00:00:17, memory = 2280.94 (MB). Completing 70% with 117 violations. elapsed time = 00:00:27, memory = 2294.48 (MB). Completing 80% with 117 violations. elapsed time = 00:00:34, memory = 2294.48 (MB). Completing 100% with 117 violations. elapsed time = 00:02:48, memory = 2294.48 (MB). [INFO DRT-0199] Number of violations = 117. Viol/Layer metal3 Metal Spacing 115 Short 2 [INFO DRT-0267] cpu time = 00:03:02, elapsed time = 00:02:48, memory = 2294.48 (MB), peak = 2353.76 (MB) Total wire length = 3720 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1884 um. Total wire length on LAYER metal4 = 1288 um. Total wire length on LAYER metal5 = 436 um. Total wire length on LAYER metal6 = 110 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4782. Up-via summary (total 4782): --------------- active 0 metal1 1755 metal2 1755 metal3 1032 metal4 194 metal5 46 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4782 [INFO DRT-0195] Start 55th optimization iteration. Completing 10% with 117 violations. elapsed time = 00:00:00, memory = 2294.48 (MB). Completing 20% with 117 violations. elapsed time = 00:00:00, memory = 2294.48 (MB). Completing 30% with 117 violations. elapsed time = 00:00:00, memory = 2294.48 (MB). Completing 40% with 117 violations. elapsed time = 00:00:04, memory = 2294.48 (MB). Completing 50% with 113 violations. elapsed time = 00:00:07, memory = 2294.48 (MB). Completing 60% with 113 violations. elapsed time = 00:00:15, memory = 2294.48 (MB). Completing 70% with 112 violations. elapsed time = 00:00:23, memory = 2294.48 (MB). Completing 80% with 112 violations. elapsed time = 00:00:28, memory = 2294.48 (MB). Completing 100% with 112 violations. elapsed time = 00:02:36, memory = 2294.48 (MB). [INFO DRT-0199] Number of violations = 112. Viol/Layer metal3 Metal Spacing 108 Short 4 [INFO DRT-0267] cpu time = 00:02:50, elapsed time = 00:02:36, memory = 2294.48 (MB), peak = 2353.76 (MB) Total wire length = 3720 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1884 um. Total wire length on LAYER metal4 = 1287 um. Total wire length on LAYER metal5 = 438 um. Total wire length on LAYER metal6 = 110 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4782. Up-via summary (total 4782): --------------- active 0 metal1 1756 metal2 1756 metal3 1029 metal4 195 metal5 46 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4782 [INFO DRT-0195] Start 56th optimization iteration. Completing 10% with 112 violations. elapsed time = 00:00:00, memory = 2294.48 (MB). Completing 20% with 112 violations. elapsed time = 00:00:00, memory = 2294.48 (MB). Completing 30% with 112 violations. elapsed time = 00:00:00, memory = 2294.48 (MB). Completing 40% with 112 violations. elapsed time = 00:00:12, memory = 2294.48 (MB). Completing 50% with 112 violations. elapsed time = 00:00:12, memory = 2294.48 (MB). Completing 60% with 112 violations. elapsed time = 00:00:39, memory = 2294.48 (MB). Completing 70% with 112 violations. elapsed time = 00:00:39, memory = 2294.48 (MB). Completing 80% with 112 violations. elapsed time = 00:00:56, memory = 2294.48 (MB). Completing 100% with 112 violations. elapsed time = 00:03:40, memory = 2294.48 (MB). [INFO DRT-0199] Number of violations = 112. Viol/Layer metal3 Metal Spacing 108 Short 4 [INFO DRT-0267] cpu time = 00:03:42, elapsed time = 00:03:40, memory = 2294.48 (MB), peak = 2353.76 (MB) Total wire length = 3721 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1884 um. Total wire length on LAYER metal4 = 1287 um. Total wire length on LAYER metal5 = 438 um. Total wire length on LAYER metal6 = 110 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4782. Up-via summary (total 4782): --------------- active 0 metal1 1756 metal2 1756 metal3 1029 metal4 195 metal5 46 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4782 [INFO DRT-0195] Start 57th optimization iteration. Completing 10% with 112 violations. elapsed time = 00:00:00, memory = 2294.48 (MB). Completing 20% with 112 violations. elapsed time = 00:00:00, memory = 2294.48 (MB). Completing 30% with 112 violations. elapsed time = 00:00:00, memory = 2294.48 (MB). Completing 40% with 118 violations. elapsed time = 00:00:01, memory = 2294.48 (MB). Completing 50% with 118 violations. elapsed time = 00:00:01, memory = 2294.49 (MB). Completing 60% with 118 violations. elapsed time = 00:00:02, memory = 2294.49 (MB). Completing 70% with 142 violations. elapsed time = 00:00:03, memory = 2294.49 (MB). Completing 80% with 142 violations. elapsed time = 00:00:03, memory = 2294.49 (MB). Completing 90% with 195 violations. elapsed time = 00:00:05, memory = 2294.49 (MB). Completing 100% with 208 violations. elapsed time = 00:00:05, memory = 2294.49 (MB). [INFO DRT-0199] Number of violations = 208. Viol/Layer via2 metal3 Cut Spacing 1 0 Metal Spacing 0 132 Short 0 75 [INFO DRT-0267] cpu time = 00:00:16, elapsed time = 00:00:05, memory = 2294.49 (MB), peak = 2353.76 (MB) Total wire length = 3775 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1914 um. Total wire length on LAYER metal4 = 1290 um. Total wire length on LAYER metal5 = 464 um. Total wire length on LAYER metal6 = 105 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4806. Up-via summary (total 4806): --------------- active 0 metal1 1754 metal2 1754 metal3 1026 metal4 226 metal5 46 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4806 [INFO DRT-0195] Start 58th optimization iteration. Completing 20% with 208 violations. elapsed time = 00:05:29, memory = 2260.48 (MB). Completing 50% with 174 violations. elapsed time = 00:07:36, memory = 2293.30 (MB). Completing 70% with 168 violations. elapsed time = 00:09:32, memory = 2293.30 (MB). Completing 100% with 167 violations. elapsed time = 00:10:26, memory = 2295.00 (MB). [INFO DRT-0199] Number of violations = 167. Viol/Layer via2 metal3 metal4 Cut Spacing 1 0 0 Metal Spacing 0 151 1 Short 0 14 0 [INFO DRT-0267] cpu time = 00:10:28, elapsed time = 00:10:26, memory = 2295.00 (MB), peak = 2353.76 (MB) Total wire length = 3757 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1957 um. Total wire length on LAYER metal4 = 1314 um. Total wire length on LAYER metal5 = 389 um. Total wire length on LAYER metal6 = 96 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4753. Up-via summary (total 4753): --------------- active 0 metal1 1753 metal2 1753 metal3 1029 metal4 175 metal5 43 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4753 [INFO DRT-0195] Start 59th optimization iteration. Completing 20% with 167 violations. elapsed time = 00:01:55, memory = 2276.20 (MB). Completing 50% with 167 violations. elapsed time = 00:03:00, memory = 2276.20 (MB). Completing 70% with 163 violations. elapsed time = 00:06:21, memory = 2279.81 (MB). Completing 100% with 137 violations. elapsed time = 00:08:28, memory = 2263.01 (MB). [INFO DRT-0199] Number of violations = 137. Viol/Layer via2 metal3 Cut Spacing 1 0 Metal Spacing 0 132 Short 0 4 [INFO DRT-0267] cpu time = 00:08:30, elapsed time = 00:08:28, memory = 2263.01 (MB), peak = 2353.76 (MB) Total wire length = 3743 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1938 um. Total wire length on LAYER metal4 = 1316 um. Total wire length on LAYER metal5 = 396 um. Total wire length on LAYER metal6 = 91 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4753. Up-via summary (total 4753): --------------- active 0 metal1 1753 metal2 1753 metal3 1027 metal4 178 metal5 42 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4753 [INFO DRT-0195] Start 60th optimization iteration. Completing 20% with 137 violations. elapsed time = 00:00:39, memory = 2263.01 (MB). Completing 50% with 137 violations. elapsed time = 00:02:34, memory = 2263.33 (MB). Completing 70% with 133 violations. elapsed time = 00:04:03, memory = 2265.56 (MB). Completing 100% with 130 violations. elapsed time = 00:08:55, memory = 2298.43 (MB). [INFO DRT-0199] Number of violations = 130. Viol/Layer via2 metal3 Cut Spacing 1 0 Metal Spacing 0 125 Short 0 4 [INFO DRT-0267] cpu time = 00:08:56, elapsed time = 00:08:55, memory = 2298.43 (MB), peak = 2353.76 (MB) Total wire length = 3732 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1928 um. Total wire length on LAYER metal4 = 1314 um. Total wire length on LAYER metal5 = 398 um. Total wire length on LAYER metal6 = 90 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4752. Up-via summary (total 4752): --------------- active 0 metal1 1753 metal2 1753 metal3 1023 metal4 179 metal5 44 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4752 [INFO DRT-0195] Start 61st optimization iteration. Completing 10% with 130 violations. elapsed time = 00:00:00, memory = 2298.43 (MB). Completing 20% with 130 violations. elapsed time = 00:00:00, memory = 2298.43 (MB). Completing 30% with 130 violations. elapsed time = 00:00:00, memory = 2298.45 (MB). Completing 40% with 130 violations. elapsed time = 00:00:11, memory = 2298.45 (MB). Completing 50% with 127 violations. elapsed time = 00:00:14, memory = 2301.06 (MB). Completing 60% with 127 violations. elapsed time = 00:01:21, memory = 2301.13 (MB). Completing 70% with 123 violations. elapsed time = 00:01:31, memory = 2301.13 (MB). Completing 80% with 123 violations. elapsed time = 00:02:32, memory = 2301.13 (MB). Completing 100% with 121 violations. elapsed time = 00:07:03, memory = 2301.13 (MB). [INFO DRT-0199] Number of violations = 121. Viol/Layer via2 metal3 Cut Spacing 1 0 Metal Spacing 0 118 Short 0 2 [INFO DRT-0267] cpu time = 00:07:19, elapsed time = 00:07:03, memory = 2301.13 (MB), peak = 2353.76 (MB) Total wire length = 3731 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1919 um. Total wire length on LAYER metal4 = 1307 um. Total wire length on LAYER metal5 = 406 um. Total wire length on LAYER metal6 = 98 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4764. Up-via summary (total 4764): --------------- active 0 metal1 1753 metal2 1753 metal3 1024 metal4 187 metal5 47 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4764 [INFO DRT-0195] Start 62nd optimization iteration. Completing 10% with 121 violations. elapsed time = 00:00:00, memory = 2301.13 (MB). Completing 20% with 121 violations. elapsed time = 00:00:00, memory = 2301.13 (MB). Completing 30% with 121 violations. elapsed time = 00:00:02, memory = 2301.13 (MB). Completing 40% with 121 violations. elapsed time = 00:00:02, memory = 2301.13 (MB). Completing 50% with 118 violations. elapsed time = 00:00:05, memory = 2301.15 (MB). Completing 60% with 118 violations. elapsed time = 00:00:26, memory = 2301.15 (MB). Completing 70% with 114 violations. elapsed time = 00:00:48, memory = 2301.15 (MB). Completing 80% with 114 violations. elapsed time = 00:01:06, memory = 2301.15 (MB). Completing 100% with 111 violations. elapsed time = 00:05:34, memory = 2302.23 (MB). [INFO DRT-0199] Number of violations = 111. Viol/Layer via2 metal3 Cut Spacing 1 0 Metal Spacing 0 108 Short 0 2 [INFO DRT-0267] cpu time = 00:06:03, elapsed time = 00:05:34, memory = 2302.23 (MB), peak = 2353.76 (MB) Total wire length = 3729 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1917 um. Total wire length on LAYER metal4 = 1300 um. Total wire length on LAYER metal5 = 406 um. Total wire length on LAYER metal6 = 105 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4767. Up-via summary (total 4767): --------------- active 0 metal1 1754 metal2 1754 metal3 1024 metal4 187 metal5 48 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4767 [INFO DRT-0195] Start 63rd optimization iteration. Completing 10% with 111 violations. elapsed time = 00:00:00, memory = 2302.23 (MB). Completing 20% with 111 violations. elapsed time = 00:00:00, memory = 2308.62 (MB). Completing 30% with 111 violations. elapsed time = 00:00:03, memory = 2308.62 (MB). Completing 40% with 111 violations. elapsed time = 00:00:06, memory = 2308.62 (MB). Completing 50% with 105 violations. elapsed time = 00:00:17, memory = 2308.62 (MB). Completing 60% with 105 violations. elapsed time = 00:00:45, memory = 2308.62 (MB). Completing 70% with 103 violations. elapsed time = 00:01:05, memory = 2308.62 (MB). Completing 80% with 103 violations. elapsed time = 00:01:09, memory = 2308.62 (MB). Completing 100% with 103 violations. elapsed time = 00:04:36, memory = 2352.16 (MB). [INFO DRT-0199] Number of violations = 103. Viol/Layer via2 metal3 Cut Spacing 1 0 Metal Spacing 0 100 Short 0 2 [INFO DRT-0267] cpu time = 00:05:13, elapsed time = 00:04:36, memory = 2352.16 (MB), peak = 2379.52 (MB) Total wire length = 3735 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1922 um. Total wire length on LAYER metal4 = 1307 um. Total wire length on LAYER metal5 = 400 um. Total wire length on LAYER metal6 = 104 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4768. Up-via summary (total 4768): --------------- active 0 metal1 1754 metal2 1754 metal3 1029 metal4 183 metal5 48 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4768 [INFO DRT-0195] Start 64th optimization iteration. Completing 10% with 103 violations. elapsed time = 00:00:00, memory = 2352.16 (MB). Completing 20% with 103 violations. elapsed time = 00:00:00, memory = 2352.16 (MB). Completing 30% with 103 violations. elapsed time = 00:00:00, memory = 2352.16 (MB). Completing 40% with 103 violations. elapsed time = 00:00:19, memory = 2352.16 (MB). Completing 50% with 101 violations. elapsed time = 00:00:19, memory = 2352.16 (MB). Completing 60% with 101 violations. elapsed time = 00:01:41, memory = 2352.16 (MB). Completing 70% with 101 violations. elapsed time = 00:01:42, memory = 2352.48 (MB). Completing 80% with 101 violations. elapsed time = 00:02:17, memory = 2353.66 (MB). Completing 100% with 96 violations. elapsed time = 00:07:34, memory = 2353.66 (MB). [INFO DRT-0199] Number of violations = 96. Viol/Layer via2 metal3 Cut Spacing 1 0 Metal Spacing 0 93 Short 0 2 [INFO DRT-0267] cpu time = 00:07:38, elapsed time = 00:07:34, memory = 2353.66 (MB), peak = 2379.52 (MB) Total wire length = 3736 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1907 um. Total wire length on LAYER metal4 = 1292 um. Total wire length on LAYER metal5 = 424 um. Total wire length on LAYER metal6 = 112 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4759. Up-via summary (total 4759): --------------- active 0 metal1 1754 metal2 1754 metal3 1013 metal4 187 metal5 51 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4759 [INFO DRT-0198] Complete detail routing. Total wire length = 3736 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 0 um. Total wire length on LAYER metal3 = 1907 um. Total wire length on LAYER metal4 = 1292 um. Total wire length on LAYER metal5 = 424 um. Total wire length on LAYER metal6 = 112 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 4759. Up-via summary (total 4759): --------------- active 0 metal1 1754 metal2 1754 metal3 1013 metal4 187 metal5 51 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 4759 [INFO DRT-0267] cpu time = 02:17:08, elapsed time = 02:11:01, memory = 2353.66 (MB), peak = 2379.52 (MB) [INFO DRT-0180] Post processing. [INFO DRT-0501] Runtime: 7863.64s Took 7864 seconds: detailed_route -output_drc ./reports/nangate45/gcd/rt_min3/5_route_drc.rpt -output_maze ./results/nangate45/gcd/rt_min3/maze.log -droute_end_iter 64 -verbose 1 -drc_report_iter_step 5 [WARNING GRT-0246] No diode with LEF class CORE ANTENNACELL found. [INFO ANT-0002] Found 0 net violations. [INFO ANT-0001] Found 0 pin violations. [INFO ANT-0002] Found 0 net violations. [INFO ANT-0001] Found 0 pin violations. Design area 722 um^2 62% utilization. write_db ./results/nangate45/gcd/rt_min3/5_2_route.odb Elapsed time: 2:11:04.11[h:]min:sec. CPU time: user 8236.48 sys 1.56 (104%). Peak memory: 2436632KB. Log Ext Elapsed/s Peak Memory/MB sha1sum result [0:20) 5_2_route .odb 7864 2379 57e7fedb2c13a970c98b /OpenROAD-flow-scripts/flow/scripts/flow.sh 5_3_fillcell fillcell Running fillcell.tcl, stage 5_3_fillcell read_liberty /OpenROAD-flow-scripts/flow/platforms/nangate45/lib/NangateOpenCellLibrary_typical.lib read_db ./results/nangate45/gcd/rt_min3/5_2_route.odb read_sdc ./results/nangate45/gcd/rt_min3/5_1_grt.sdc source /OpenROAD-flow-scripts/flow/platforms/nangate45/setRC.tcl [WARNING STA-0450] virtual clock vclk_core_clock can not be propagated. filler_placement "FILLCELL_X1 FILLCELL_X2 FILLCELL_X4 FILLCELL_X8 FILLCELL_X16 FILLCELL_X32" [INFO DPL-0001] Placed 451 filler instances. Design area 722 um^2 62% utilization. write_db ./results/nangate45/gcd/rt_min3/5_3_fillcell.odb Elapsed time: 0:00.19[h:]min:sec. CPU time: user 0.17 sys 0.03 (101%). Peak memory: 117312KB. Log Ext Elapsed/s Peak Memory/MB sha1sum result [0:20) 5_3_fillcell .odb 0 114 32608e76f9ef0221ee4b cp ./results/nangate45/gcd/rt_min3/5_3_fillcell.odb ./results/nangate45/gcd/rt_min3/5_route.odb cp ./results/nangate45/gcd/rt_min3/5_1_grt.sdc ./results/nangate45/gcd/rt_min3/5_route.sdc /OpenROAD-flow-scripts/flow/scripts/flow.sh 6_1_fill density_fill Running density_fill.tcl, stage 6_1_fill read_liberty /OpenROAD-flow-scripts/flow/platforms/nangate45/lib/NangateOpenCellLibrary_typical.lib read_db ./results/nangate45/gcd/rt_min3/5_route.odb read_sdc ./results/nangate45/gcd/rt_min3/5_route.sdc source /OpenROAD-flow-scripts/flow/platforms/nangate45/setRC.tcl exec cp ./results/nangate45/gcd/rt_min3/5_route.odb ./results/nangate45/gcd/rt_min3/6_1_fill.odb Elapsed time: 0:00.20[h:]min:sec. CPU time: user 0.17 sys 0.03 (101%). Peak memory: 114572KB. Log Ext Elapsed/s Peak Memory/MB sha1sum result [0:20) 6_1_fill .odb 0 111 32608e76f9ef0221ee4b cp ./results/nangate45/gcd/rt_min3/5_route.sdc ./results/nangate45/gcd/rt_min3/6_1_fill.sdc /OpenROAD-flow-scripts/flow/scripts/flow.sh 6_report final_report Running final_report.tcl, stage 6_report read_liberty /OpenROAD-flow-scripts/flow/platforms/nangate45/lib/NangateOpenCellLibrary_typical.lib read_db ./results/nangate45/gcd/rt_min3/6_1_fill.odb read_sdc ./results/nangate45/gcd/rt_min3/6_1_fill.sdc source /OpenROAD-flow-scripts/flow/platforms/nangate45/setRC.tcl [WARNING STA-0450] virtual clock vclk_core_clock can not be propagated. write_db ./results/nangate45/gcd/rt_min3/6_final.odb Deleted 0 routing obstructions [INFO RCX-0431] Defined process_corner X with ext_model_index 0 [INFO RCX-0029] Defined extraction corner X [WARNING RCX-0514] The -ext_model_file option is deprecated. Use set_extraction_rules_file command instead. [INFO RCX-0435] Reading extraction model file /OpenROAD-flow-scripts/flow/platforms/nangate45/rcx_patterns.rules ... [INFO RCX-0436] RC segment generation gcd (max_merge_res 50.0) ... [INFO RCX-0040] Final 1720 rc segments [INFO RCX-0439] Coupling Cap extraction gcd ... [INFO RCX-0440] Coupling threshhold is 0.1000 fF, coupling capacitance less than 0.1000 fF will be grounded. [INFO RCX-0442] 52% of 3695 wires extracted [INFO RCX-0442] 100% of 3695 wires extracted [INFO RCX-0045] Extract 648 nets, 2349 rsegs, 2349 caps, 4808 ccs [INFO RCX-0443] 648 nets finished [INFO PSM-0040] All shapes on net VDD are connected. [INFO PSM-0073] Using bump pattern with x-pitch 140.0000um, y-pitch 140.0000um, and size 70.0000um with an reduction factor of 3x. ########## IR report ################# Net : VDD Corner : default Total power : 2.67e-03 W Supply voltage : 1.10e+00 V Worstcase voltage: 1.10e+00 V Average voltage : 1.10e+00 V Average IR drop : 1.81e-03 V Worstcase IR drop: 4.24e-03 V Percentage drop : 0.39 % ###################################### [INFO PSM-0040] All shapes on net VSS are connected. [INFO PSM-0073] Using bump pattern with x-pitch 140.0000um, y-pitch 140.0000um, and size 70.0000um with an reduction factor of 3x. ########## IR report ################# Net : VSS Corner : default Total power : 2.67e-03 W Supply voltage : 0.00e+00 V Worstcase voltage: 3.73e-03 V Average voltage : 1.84e-03 V Average IR drop : 1.84e-03 V Worstcase IR drop: 3.73e-03 V Percentage drop : 0.34 % ###################################### Cell type report: Count Area Fill cell 451 439.70 Tap cell 48 12.77 Clock buffer 6 7.45 Timing Repair Buffer 68 60.12 Inverter 87 51.87 Clock inverter 2 1.06 Sequential cell 35 158.27 Multi-Input combinational cell 382 430.65 Total 1079 1161.89 Report metrics stage 6, finish... ========================================================================== finish report_design_area -------------------------------------------------------------------------- Design area 722 um^2 62% utilization. [WARNING GUI-0076] QStandardPaths: XDG_RUNTIME_DIR not set, defaulting to '/tmp/runtime-root' [WARNING GUI-0066] Heat map "IR Drop" has not been populated with data. [WARNING GUI-0066] Heat map "Routing Congestion" has not been populated with data. Elapsed time: 0:01.10[h:]min:sec. CPU time: user 1.15 sys 0.18 (120%). Peak memory: 188012KB. Log Ext Elapsed/s Peak Memory/MB sha1sum result [0:20) 6_report 1 183 N/A cp ./results/nangate45/gcd/rt_min3/5_route.sdc ./results/nangate45/gcd/rt_min3/6_final.sdc cp /OpenROAD-flow-scripts/flow/platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef ./objects/nangate45/gcd/rt_min3/klayout_tech.lef /usr/bin/python3 /OpenROAD-flow-scripts/flow/util/generate_klayout_tech.py \ --template /OpenROAD-flow-scripts/flow/platforms/nangate45/FreePDK45.lyt \ --output ./objects/nangate45/gcd/rt_min3/klayout.lyt \ --lef-files ./objects/nangate45/gcd/rt_min3/klayout_tech.lef /OpenROAD-flow-scripts/flow/platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef \ --map-files /usr/bin/python3 /OpenROAD-flow-scripts/flow/scripts/run_command.py --log /OpenROAD-flow-scripts/flow/logs/nangate45/gcd/rt_min3/6_1_merge.log --tee -- \ /OpenROAD-flow-scripts/flow/scripts/klayout.sh -zz -rd design_name=gcd \ -rd in_def=./results/nangate45/gcd/rt_min3/6_final.def \ -rd in_files="/OpenROAD-flow-scripts/flow/platforms/nangate45/gds/NangateOpenCellLibrary.gds " \ -rd seal_file="" \ -rd out_file=./results/nangate45/gcd/rt_min3/6_1_merged.gds \ -rd tech_file=./objects/nangate45/gcd/rt_min3/klayout.lyt \ -rd layer_map= \ -r /OpenROAD-flow-scripts/flow/util/def2stream.py KLayout 0.30.7 Warning: DEF UNITS does not match reader DBU (DEF UNITS is 2000 and corresponds to a DBU of 0.0005, but reader DBU is set to 0.0001) (line=5, cell=, file=6_final.def) [INFO] Reporting cells prior to loading DEF ... /OpenROAD-flow-scripts/flow/platforms/nangate45/gds/NangateOpenCellLibrary.gds [INFO] GDS_ALLOW_EMPTY=fakeram.* [INFO] All LEF cells have matching GDS/OAS cells [INFO] No orphan cells in the final layout Elapsed time: 0:00.90[h:]min:sec. CPU time: user 0.82 sys 0.08 (99%). Peak memory: 435380KB. cp results/nangate45/gcd/rt_min3/6_1_merged.gds results/nangate45/gcd/rt_min3/6_final.gds ./logs/nangate45/gcd/rt_min3 Log Ext Elapsed/s Peak Memory/MB sha1sum result [0:20) 1_1_yosys_canonicalize .rtlil 0 41 0143866d45d6a9e39c47 1_2_yosys .v 0 44 756ad24f74de658d5044 1_2_yosys .sdc 21b872a6567721784485 1_synth .odb 0 110 5574db6bc0e99d58e06a 1_synth .sdc 7fe61694c034e1755ac1 2_1_floorplan .odb 0 129 756823344d91a4c3b0ef 2_1_floorplan .sdc 7fe61694c034e1755ac1 2_2_floorplan_macro .odb 0 109 756823344d91a4c3b0ef 2_3_floorplan_tapcell .odb 0 109 49259c794e061c9e9198 2_4_floorplan_pdn .odb 0 111 64fba4e3d4b83b73ae9d 3_1_place_gp_skip_io .odb 83 111 7cae8082a5762fcc875a 3_2_place_iop .odb 0 110 ea8758d8bcef7e75522f 3_3_place_gp .odb 156 281 7d18049b0761a28b050f 3_4_place_resized .odb 0 129 7d18049b0761a28b050f 3_5_place_dp .odb 0 115 f7690ce85663a17a768b 4_1_cts .odb 1 142 9bcbcd77cba5ee2aa168 5_1_grt .odb 7 287 da68a06692fbeb7ce6aa 5_1_grt .sdc 6dc41493824210708c18 5_2_route .odb 7864 2379 57e7fedb2c13a970c98b 5_3_fillcell .odb 0 114 32608e76f9ef0221ee4b 6_1_fill .odb 0 111 32608e76f9ef0221ee4b 6_1_fill .sdc 6dc41493824210708c18 6_1_merge 0 425 N/A 6_report 1 183 N/A Total 8112 2379