========================================================================== finish report_tns -------------------------------------------------------------------------- tns max -70.64 ========================================================================== finish report_wns -------------------------------------------------------------------------- wns max -0.15 ========================================================================== finish report_worst_slack -------------------------------------------------------------------------- worst slack max -0.15 ========================================================================== finish report_clock_min_period -------------------------------------------------------------------------- core_clock period_min = 1.35 fmax = 739.07 ========================================================================== finish report_clock_skew -------------------------------------------------------------------------- Clock core_clock 0.31 source latency frontend/s2_pc[5]$_SDFFE_PP0N_/CK ^ -0.27 target latency frontend/icache.data_arrays_0.data_arrays_0_0_ext.mem/clk ^ 0.00 CRPR -------------- 0.04 setup skew ========================================================================== finish report_checks -path_delay min -------------------------------------------------------------------------- Startpoint: core/div/neg_out$_SDFFCE_PN0P_ (rising edge-triggered flip-flop clocked by core_clock) Endpoint: core/div/state[4]$_DFF_P_ (rising edge-triggered flip-flop clocked by core_clock) Path Group: core_clock Path Type: min Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 clock core_clock (rise edge) 0.00 0.00 clock source latency 2 27.88 0.00 0.00 0.00 ^ clock (in) clock (net) 0.01 0.00 0.00 ^ clkbuf_regs_0_core_clock/A (CLKBUF_X3) 1 1.45 0.01 0.02 0.03 ^ clkbuf_regs_0_core_clock/Z (CLKBUF_X3) clock_regs (net) 0.01 0.00 0.03 ^ clkbuf_0_clock_regs/A (CLKBUF_X3) 4 43.46 0.03 0.06 0.09 ^ clkbuf_0_clock_regs/Z (CLKBUF_X3) clknet_0_clock_regs (net) 0.03 0.00 0.09 ^ clkbuf_2_2_0_clock_regs/A (CLKBUF_X3) 16 65.83 0.05 0.09 0.18 ^ clkbuf_2_2_0_clock_regs/Z (CLKBUF_X3) clknet_2_2_0_clock_regs (net) 0.05 0.00 0.18 ^ clkbuf_6_47_0_clock_regs/A (CLKBUF_X3) 6 27.49 0.02 0.06 0.25 ^ clkbuf_6_47_0_clock_regs/Z (CLKBUF_X3) clknet_6_47_0_clock_regs (net) 0.02 0.00 0.25 ^ clkbuf_leaf_122_clock_regs/A (CLKBUF_X3) 8 10.21 0.01 0.04 0.29 ^ clkbuf_leaf_122_clock_regs/Z (CLKBUF_X3) clknet_leaf_122_clock_regs (net) 0.01 0.00 0.29 ^ core/div/neg_out$_SDFFCE_PN0P_/CK (DFF_X1) 1 2.06 0.01 0.07 0.36 ^ core/div/neg_out$_SDFFCE_PN0P_/QN (DFF_X1) core/div/_0001_ (net) 0.01 0.00 0.36 ^ core/div/_3989_/A1 (NOR3_X1) 1 1.21 0.00 0.01 0.37 v core/div/_3989_/ZN (NOR3_X1) core/div/_0490_ (net) 0.00 0.00 0.37 v core/div/state[4]$_DFF_P_/D (DFF_X1) 0.37 data arrival time 0.00 0.00 clock core_clock (rise edge) 0.00 0.00 clock source latency 2 27.88 0.00 0.00 0.00 ^ clock (in) clock (net) 0.01 0.00 0.00 ^ clkbuf_regs_0_core_clock/A (CLKBUF_X3) 1 1.45 0.01 0.02 0.03 ^ clkbuf_regs_0_core_clock/Z (CLKBUF_X3) clock_regs (net) 0.01 0.00 0.03 ^ clkbuf_0_clock_regs/A (CLKBUF_X3) 4 43.46 0.03 0.06 0.09 ^ clkbuf_0_clock_regs/Z (CLKBUF_X3) clknet_0_clock_regs (net) 0.03 0.00 0.09 ^ clkbuf_2_2_0_clock_regs/A (CLKBUF_X3) 16 65.83 0.05 0.09 0.18 ^ clkbuf_2_2_0_clock_regs/Z (CLKBUF_X3) clknet_2_2_0_clock_regs (net) 0.05 0.00 0.18 ^ clkbuf_6_47_0_clock_regs/A (CLKBUF_X3) 6 27.49 0.02 0.06 0.25 ^ clkbuf_6_47_0_clock_regs/Z (CLKBUF_X3) clknet_6_47_0_clock_regs (net) 0.02 0.00 0.25 ^ clkbuf_leaf_122_clock_regs/A (CLKBUF_X3) 8 10.21 0.01 0.04 0.29 ^ clkbuf_leaf_122_clock_regs/Z (CLKBUF_X3) clknet_leaf_122_clock_regs (net) 0.01 0.00 0.29 ^ core/div/state[4]$_DFF_P_/CK (DFF_X1) 0.00 0.29 clock reconvergence pessimism 0.00 0.29 library hold time 0.29 data required time ----------------------------------------------------------------------------- 0.29 data required time -0.37 data arrival time ----------------------------------------------------------------------------- 0.07 slack (MET) ========================================================================== finish report_checks -path_delay max -------------------------------------------------------------------------- Startpoint: frontend/fq._T_1_0$_SDFF_PP0_ (rising edge-triggered flip-flop clocked by core_clock) Endpoint: frontend/fq._T_2_1_data[18]$_DFFE_PP_ (rising edge-triggered flip-flop clocked by core_clock) Path Group: core_clock Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 clock core_clock (rise edge) 0.00 0.00 clock source latency 2 27.88 0.00 0.00 0.00 ^ clock (in) clock (net) 0.01 0.00 0.00 ^ clkbuf_regs_0_core_clock/A (CLKBUF_X3) 1 1.45 0.01 0.02 0.03 ^ clkbuf_regs_0_core_clock/Z (CLKBUF_X3) clock_regs (net) 0.01 0.00 0.03 ^ clkbuf_0_clock_regs/A (CLKBUF_X3) 4 43.46 0.03 0.06 0.09 ^ clkbuf_0_clock_regs/Z (CLKBUF_X3) clknet_0_clock_regs (net) 0.03 0.00 0.09 ^ clkbuf_2_2_0_clock_regs/A (CLKBUF_X3) 16 65.83 0.05 0.09 0.18 ^ clkbuf_2_2_0_clock_regs/Z (CLKBUF_X3) clknet_2_2_0_clock_regs (net) 0.05 0.00 0.19 ^ clkbuf_6_35_0_clock_regs/A (CLKBUF_X3) 13 32.68 0.03 0.07 0.25 ^ clkbuf_6_35_0_clock_regs/Z (CLKBUF_X3) clknet_6_35_0_clock_regs (net) 0.03 0.00 0.25 ^ clkbuf_leaf_96_clock_regs/A (CLKBUF_X3) 9 11.08 0.01 0.04 0.30 ^ clkbuf_leaf_96_clock_regs/Z (CLKBUF_X3) clknet_leaf_96_clock_regs (net) 0.01 0.00 0.30 ^ frontend/fq._T_1_0$_SDFF_PP0_/CK (DFF_X2) 3 6.05 0.01 0.12 0.42 ^ frontend/fq._T_1_0$_SDFF_PP0_/Q (DFF_X2) frontend/fq._T_1_0 (net) 0.01 0.00 0.42 ^ frontend/_4384_/S (MUX2_X1) 2 14.77 0.04 0.07 0.49 ^ frontend/_4384_/Z (MUX2_X1) core_io_imem_resp_bits_pc[1] (net) 0.04 0.00 0.49 ^ core/_18832_/B (HA_X1) 3 9.71 0.02 0.06 0.55 ^ core/_18832_/CO (HA_X1) core/_00056_ (net) 0.02 0.00 0.55 ^ core/place4210/A (BUF_X4) 8 15.79 0.01 0.03 0.58 ^ core/place4210/Z (BUF_X4) core/net4209 (net) 0.01 0.00 0.58 ^ core/_10206_/S (MUX2_X1) 2 10.61 0.02 0.08 0.65 v core/_10206_/Z (MUX2_X1) core/_03494_ (net) 0.02 0.00 0.65 v core/_10207_/B1 (AOI21_X4) 5 22.03 0.04 0.05 0.70 ^ core/_10207_/ZN (AOI21_X4) core/_03495_ (net) 0.04 0.00 0.70 ^ core/place4014/A (BUF_X4) 2 9.17 0.01 0.03 0.73 ^ core/place4014/Z (BUF_X4) core/net4013 (net) 0.01 0.00 0.73 ^ core/_10294_/A (OAI211_X4) 4 9.91 0.02 0.03 0.76 v core/_10294_/ZN (OAI211_X4) core/_03582_ (net) 0.02 0.00 0.76 v core/_10330_/A1 (OR2_X4) 3 3.99 0.01 0.05 0.81 v core/_10330_/ZN (OR2_X4) core/_03618_ (net) 0.01 0.00 0.81 v core/_10977_/B1 (OAI33_X1) 1 2.00 0.06 0.07 0.88 ^ core/_10977_/ZN (OAI33_X1) core/_04263_ (net) 0.06 0.00 0.88 ^ rebuffer4848/A (BUF_X2) 2 11.45 0.02 0.04 0.92 ^ rebuffer4848/Z (BUF_X2) net4847 (net) 0.02 0.00 0.92 ^ rebuffer4861/A (BUF_X4) 1 9.84 0.01 0.02 0.94 ^ rebuffer4861/Z (BUF_X4) net4860 (net) 0.01 0.00 0.94 ^ clone4847/A (BUF_X8) 5 14.84 0.01 0.02 0.97 ^ clone4847/Z (BUF_X8) net4846 (net) 0.01 0.00 0.97 ^ core/place3397/A (BUF_X4) 2 3.22 0.01 0.02 0.98 ^ core/place3397/Z (BUF_X4) core/net3396 (net) 0.01 0.00 0.98 ^ core/_11231_/S (MUX2_X1) 1 6.63 0.01 0.07 1.05 v core/_11231_/Z (MUX2_X1) core/_04517_ (net) 0.01 0.00 1.05 v core/_11235_/A1 (OAI22_X4) 1 6.18 0.03 0.03 1.08 ^ core/_11235_/ZN (OAI22_X4) core/_04521_ (net) 0.03 0.00 1.08 ^ core/_11236_/A4 (NOR4_X4) 2 7.25 0.01 0.02 1.10 v core/_11236_/ZN (NOR4_X4) core/_04522_ (net) 0.01 0.00 1.10 v core/_11256_/A3 (NOR4_X4) 1 7.64 0.04 0.08 1.18 ^ core/_11256_/ZN (NOR4_X4) core/_04542_ (net) 0.04 0.00 1.18 ^ core/_11257_/C2 (OAI221_X2) 2 7.19 0.02 0.05 1.23 v core/_11257_/ZN (OAI221_X2) core/_04543_ (net) 0.02 0.00 1.23 v core/_18794_/A1 (NOR2_X2) 2 6.89 0.02 0.04 1.27 ^ core/_18794_/ZN (NOR2_X2) core/_03433_ (net) 0.02 0.00 1.27 ^ core/_18795_/A2 (NAND2_X2) 1 6.33 0.01 0.02 1.29 v core/_18795_/ZN (NAND2_X2) core/_03434_ (net) 0.01 0.00 1.29 v core/_18797_/A (AOI21_X4) 3 32.72 0.05 0.07 1.36 ^ core/_18797_/ZN (AOI21_X4) core_io_imem_resp_ready (net) 0.05 0.00 1.36 ^ frontend/_3989_/A (INV_X8) 4 24.99 0.01 0.02 1.38 v frontend/_3989_/ZN (INV_X8) frontend/_1474_ (net) 0.01 0.00 1.38 v frontend/_4065_/A3 (NAND3_X4) 1 6.40 0.01 0.02 1.40 ^ frontend/_4065_/ZN (NAND3_X4) frontend/_1519_ (net) 0.01 0.00 1.40 ^ frontend/_4067_/A (OAI21_X4) 1 6.10 0.01 0.02 1.42 v frontend/_4067_/ZN (OAI21_X4) frontend/_1521_ (net) 0.01 0.00 1.42 v frontend/_4068_/B1 (AOI22_X4) 4 18.65 0.04 0.06 1.48 ^ frontend/_4068_/ZN (AOI22_X4) frontend/_1522_ (net) 0.04 0.00 1.48 ^ frontend/rebuffer4856/A (BUF_X8) 6 58.93 0.02 0.04 1.52 ^ frontend/rebuffer4856/Z (BUF_X8) frontend/net4855 (net) 0.02 0.01 1.52 ^ clone5192/A (BUF_X8) 8 24.13 0.01 0.03 1.55 ^ clone5192/Z (BUF_X8) net5191 (net) 0.01 0.00 1.55 ^ frontend/_4097_/S (MUX2_X1) 1 2.02 0.01 0.06 1.61 v frontend/_4097_/Z (MUX2_X1) frontend/_0803_ (net) 0.01 0.00 1.61 v frontend/fq._T_2_1_data[18]$_DFFE_PP_/D (DFF_X1) 1.61 data arrival time 1.20 1.20 clock core_clock (rise edge) 0.00 1.20 clock source latency 2 27.88 0.00 0.00 1.20 ^ clock (in) clock (net) 0.01 0.00 1.20 ^ clkbuf_regs_0_core_clock/A (CLKBUF_X3) 1 1.45 0.01 0.02 1.23 ^ clkbuf_regs_0_core_clock/Z (CLKBUF_X3) clock_regs (net) 0.01 0.00 1.23 ^ clkbuf_0_clock_regs/A (CLKBUF_X3) 4 43.46 0.03 0.06 1.29 ^ clkbuf_0_clock_regs/Z (CLKBUF_X3) clknet_0_clock_regs (net) 0.03 0.00 1.29 ^ clkbuf_2_2_0_clock_regs/A (CLKBUF_X3) 16 65.83 0.05 0.09 1.38 ^ clkbuf_2_2_0_clock_regs/Z (CLKBUF_X3) clknet_2_2_0_clock_regs (net) 0.05 0.00 1.39 ^ clkbuf_6_34_0_clock_regs/A (CLKBUF_X3) 12 29.45 0.03 0.07 1.45 ^ clkbuf_6_34_0_clock_regs/Z (CLKBUF_X3) clknet_6_34_0_clock_regs (net) 0.03 0.00 1.45 ^ clkbuf_leaf_92_clock_regs/A (CLKBUF_X3) 9 11.27 0.01 0.04 1.49 ^ clkbuf_leaf_92_clock_regs/Z (CLKBUF_X3) clknet_leaf_92_clock_regs (net) 0.01 0.00 1.49 ^ frontend/fq._T_2_1_data[18]$_DFFE_PP_/CK (DFF_X1) 0.00 1.49 clock reconvergence pessimism -0.04 1.46 library setup time 1.46 data required time ----------------------------------------------------------------------------- 1.46 data required time -1.61 data arrival time ----------------------------------------------------------------------------- -0.15 slack (VIOLATED) ========================================================================== finish report_checks -unconstrained -------------------------------------------------------------------------- Startpoint: frontend/fq._T_1_0$_SDFF_PP0_ (rising edge-triggered flip-flop clocked by core_clock) Endpoint: frontend/fq._T_2_1_data[18]$_DFFE_PP_ (rising edge-triggered flip-flop clocked by core_clock) Path Group: core_clock Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 clock core_clock (rise edge) 0.00 0.00 clock source latency 2 27.88 0.00 0.00 0.00 ^ clock (in) clock (net) 0.01 0.00 0.00 ^ clkbuf_regs_0_core_clock/A (CLKBUF_X3) 1 1.45 0.01 0.02 0.03 ^ clkbuf_regs_0_core_clock/Z (CLKBUF_X3) clock_regs (net) 0.01 0.00 0.03 ^ clkbuf_0_clock_regs/A (CLKBUF_X3) 4 43.46 0.03 0.06 0.09 ^ clkbuf_0_clock_regs/Z (CLKBUF_X3) clknet_0_clock_regs (net) 0.03 0.00 0.09 ^ clkbuf_2_2_0_clock_regs/A (CLKBUF_X3) 16 65.83 0.05 0.09 0.18 ^ clkbuf_2_2_0_clock_regs/Z (CLKBUF_X3) clknet_2_2_0_clock_regs (net) 0.05 0.00 0.19 ^ clkbuf_6_35_0_clock_regs/A (CLKBUF_X3) 13 32.68 0.03 0.07 0.25 ^ clkbuf_6_35_0_clock_regs/Z (CLKBUF_X3) clknet_6_35_0_clock_regs (net) 0.03 0.00 0.25 ^ clkbuf_leaf_96_clock_regs/A (CLKBUF_X3) 9 11.08 0.01 0.04 0.30 ^ clkbuf_leaf_96_clock_regs/Z (CLKBUF_X3) clknet_leaf_96_clock_regs (net) 0.01 0.00 0.30 ^ frontend/fq._T_1_0$_SDFF_PP0_/CK (DFF_X2) 3 6.05 0.01 0.12 0.42 ^ frontend/fq._T_1_0$_SDFF_PP0_/Q (DFF_X2) frontend/fq._T_1_0 (net) 0.01 0.00 0.42 ^ frontend/_4384_/S (MUX2_X1) 2 14.77 0.04 0.07 0.49 ^ frontend/_4384_/Z (MUX2_X1) core_io_imem_resp_bits_pc[1] (net) 0.04 0.00 0.49 ^ core/_18832_/B (HA_X1) 3 9.71 0.02 0.06 0.55 ^ core/_18832_/CO (HA_X1) core/_00056_ (net) 0.02 0.00 0.55 ^ core/place4210/A (BUF_X4) 8 15.79 0.01 0.03 0.58 ^ core/place4210/Z (BUF_X4) core/net4209 (net) 0.01 0.00 0.58 ^ core/_10206_/S (MUX2_X1) 2 10.61 0.02 0.08 0.65 v core/_10206_/Z (MUX2_X1) core/_03494_ (net) 0.02 0.00 0.65 v core/_10207_/B1 (AOI21_X4) 5 22.03 0.04 0.05 0.70 ^ core/_10207_/ZN (AOI21_X4) core/_03495_ (net) 0.04 0.00 0.70 ^ core/place4014/A (BUF_X4) 2 9.17 0.01 0.03 0.73 ^ core/place4014/Z (BUF_X4) core/net4013 (net) 0.01 0.00 0.73 ^ core/_10294_/A (OAI211_X4) 4 9.91 0.02 0.03 0.76 v core/_10294_/ZN (OAI211_X4) core/_03582_ (net) 0.02 0.00 0.76 v core/_10330_/A1 (OR2_X4) 3 3.99 0.01 0.05 0.81 v core/_10330_/ZN (OR2_X4) core/_03618_ (net) 0.01 0.00 0.81 v core/_10977_/B1 (OAI33_X1) 1 2.00 0.06 0.07 0.88 ^ core/_10977_/ZN (OAI33_X1) core/_04263_ (net) 0.06 0.00 0.88 ^ rebuffer4848/A (BUF_X2) 2 11.45 0.02 0.04 0.92 ^ rebuffer4848/Z (BUF_X2) net4847 (net) 0.02 0.00 0.92 ^ rebuffer4861/A (BUF_X4) 1 9.84 0.01 0.02 0.94 ^ rebuffer4861/Z (BUF_X4) net4860 (net) 0.01 0.00 0.94 ^ clone4847/A (BUF_X8) 5 14.84 0.01 0.02 0.97 ^ clone4847/Z (BUF_X8) net4846 (net) 0.01 0.00 0.97 ^ core/place3397/A (BUF_X4) 2 3.22 0.01 0.02 0.98 ^ core/place3397/Z (BUF_X4) core/net3396 (net) 0.01 0.00 0.98 ^ core/_11231_/S (MUX2_X1) 1 6.63 0.01 0.07 1.05 v core/_11231_/Z (MUX2_X1) core/_04517_ (net) 0.01 0.00 1.05 v core/_11235_/A1 (OAI22_X4) 1 6.18 0.03 0.03 1.08 ^ core/_11235_/ZN (OAI22_X4) core/_04521_ (net) 0.03 0.00 1.08 ^ core/_11236_/A4 (NOR4_X4) 2 7.25 0.01 0.02 1.10 v core/_11236_/ZN (NOR4_X4) core/_04522_ (net) 0.01 0.00 1.10 v core/_11256_/A3 (NOR4_X4) 1 7.64 0.04 0.08 1.18 ^ core/_11256_/ZN (NOR4_X4) core/_04542_ (net) 0.04 0.00 1.18 ^ core/_11257_/C2 (OAI221_X2) 2 7.19 0.02 0.05 1.23 v core/_11257_/ZN (OAI221_X2) core/_04543_ (net) 0.02 0.00 1.23 v core/_18794_/A1 (NOR2_X2) 2 6.89 0.02 0.04 1.27 ^ core/_18794_/ZN (NOR2_X2) core/_03433_ (net) 0.02 0.00 1.27 ^ core/_18795_/A2 (NAND2_X2) 1 6.33 0.01 0.02 1.29 v core/_18795_/ZN (NAND2_X2) core/_03434_ (net) 0.01 0.00 1.29 v core/_18797_/A (AOI21_X4) 3 32.72 0.05 0.07 1.36 ^ core/_18797_/ZN (AOI21_X4) core_io_imem_resp_ready (net) 0.05 0.00 1.36 ^ frontend/_3989_/A (INV_X8) 4 24.99 0.01 0.02 1.38 v frontend/_3989_/ZN (INV_X8) frontend/_1474_ (net) 0.01 0.00 1.38 v frontend/_4065_/A3 (NAND3_X4) 1 6.40 0.01 0.02 1.40 ^ frontend/_4065_/ZN (NAND3_X4) frontend/_1519_ (net) 0.01 0.00 1.40 ^ frontend/_4067_/A (OAI21_X4) 1 6.10 0.01 0.02 1.42 v frontend/_4067_/ZN (OAI21_X4) frontend/_1521_ (net) 0.01 0.00 1.42 v frontend/_4068_/B1 (AOI22_X4) 4 18.65 0.04 0.06 1.48 ^ frontend/_4068_/ZN (AOI22_X4) frontend/_1522_ (net) 0.04 0.00 1.48 ^ frontend/rebuffer4856/A (BUF_X8) 6 58.93 0.02 0.04 1.52 ^ frontend/rebuffer4856/Z (BUF_X8) frontend/net4855 (net) 0.02 0.01 1.52 ^ clone5192/A (BUF_X8) 8 24.13 0.01 0.03 1.55 ^ clone5192/Z (BUF_X8) net5191 (net) 0.01 0.00 1.55 ^ frontend/_4097_/S (MUX2_X1) 1 2.02 0.01 0.06 1.61 v frontend/_4097_/Z (MUX2_X1) frontend/_0803_ (net) 0.01 0.00 1.61 v frontend/fq._T_2_1_data[18]$_DFFE_PP_/D (DFF_X1) 1.61 data arrival time 1.20 1.20 clock core_clock (rise edge) 0.00 1.20 clock source latency 2 27.88 0.00 0.00 1.20 ^ clock (in) clock (net) 0.01 0.00 1.20 ^ clkbuf_regs_0_core_clock/A (CLKBUF_X3) 1 1.45 0.01 0.02 1.23 ^ clkbuf_regs_0_core_clock/Z (CLKBUF_X3) clock_regs (net) 0.01 0.00 1.23 ^ clkbuf_0_clock_regs/A (CLKBUF_X3) 4 43.46 0.03 0.06 1.29 ^ clkbuf_0_clock_regs/Z (CLKBUF_X3) clknet_0_clock_regs (net) 0.03 0.00 1.29 ^ clkbuf_2_2_0_clock_regs/A (CLKBUF_X3) 16 65.83 0.05 0.09 1.38 ^ clkbuf_2_2_0_clock_regs/Z (CLKBUF_X3) clknet_2_2_0_clock_regs (net) 0.05 0.00 1.39 ^ clkbuf_6_34_0_clock_regs/A (CLKBUF_X3) 12 29.45 0.03 0.07 1.45 ^ clkbuf_6_34_0_clock_regs/Z (CLKBUF_X3) clknet_6_34_0_clock_regs (net) 0.03 0.00 1.45 ^ clkbuf_leaf_92_clock_regs/A (CLKBUF_X3) 9 11.27 0.01 0.04 1.49 ^ clkbuf_leaf_92_clock_regs/Z (CLKBUF_X3) clknet_leaf_92_clock_regs (net) 0.01 0.00 1.49 ^ frontend/fq._T_2_1_data[18]$_DFFE_PP_/CK (DFF_X1) 0.00 1.49 clock reconvergence pessimism -0.04 1.46 library setup time 1.46 data required time ----------------------------------------------------------------------------- 1.46 data required time -1.61 data arrival time ----------------------------------------------------------------------------- -0.15 slack (VIOLATED) ========================================================================== finish report_check_types -max_slew -max_cap -max_fanout -violators -------------------------------------------------------------------------- max capacitance Pin Limit Cap Slack ------------------------------------------------------------ core/csr/_06687_/ZN 52.11 53.81 -1.70 (VIOLATED) core/csr/_06506_/ZN 27.62 29.07 -1.45 (VIOLATED) ========================================================================== finish max_slew_check_slack -------------------------------------------------------------------------- 0.06622979044914246 ========================================================================== finish max_slew_check_limit -------------------------------------------------------------------------- 0.1985349953174591 ========================================================================== finish max_slew_check_slack_limit -------------------------------------------------------------------------- 0.3336 ========================================================================== finish max_fanout_check_slack -------------------------------------------------------------------------- 1.0000000150474662e+30 ========================================================================== finish max_fanout_check_limit -------------------------------------------------------------------------- 1.0000000150474662e+30 ========================================================================== finish max_capacitance_check_slack -------------------------------------------------------------------------- -1.7016112804412842 ========================================================================== finish max_capacitance_check_limit -------------------------------------------------------------------------- 52.10879898071289 ========================================================================== finish max_capacitance_check_slack_limit -------------------------------------------------------------------------- -0.0327 ========================================================================== finish max_slew_violation_count -------------------------------------------------------------------------- max slew violation count 0 ========================================================================== finish max_fanout_violation_count -------------------------------------------------------------------------- max fanout violation count 0 ========================================================================== finish max_cap_violation_count -------------------------------------------------------------------------- max cap violation count 2 ========================================================================== finish setup_violation_count -------------------------------------------------------------------------- setup violation count 800 ========================================================================== finish hold_violation_count -------------------------------------------------------------------------- hold violation count 0 ========================================================================== finish report_checks -path_delay max reg to reg -------------------------------------------------------------------------- Startpoint: frontend/fq._T_1_0$_SDFF_PP0_ (rising edge-triggered flip-flop clocked by core_clock) Endpoint: frontend/fq._T_2_1_data[18]$_DFFE_PP_ (rising edge-triggered flip-flop clocked by core_clock) Path Group: core_clock Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock core_clock (rise edge) 0.00 0.00 clock source latency 0.00 0.00 ^ clock (in) 0.03 0.03 ^ clkbuf_regs_0_core_clock/Z (CLKBUF_X3) 0.06 0.09 ^ clkbuf_0_clock_regs/Z (CLKBUF_X3) 0.09 0.18 ^ clkbuf_2_2_0_clock_regs/Z (CLKBUF_X3) 0.07 0.25 ^ clkbuf_6_35_0_clock_regs/Z (CLKBUF_X3) 0.04 0.30 ^ clkbuf_leaf_96_clock_regs/Z (CLKBUF_X3) 0.00 0.30 ^ frontend/fq._T_1_0$_SDFF_PP0_/CK (DFF_X2) 0.12 0.42 ^ frontend/fq._T_1_0$_SDFF_PP0_/Q (DFF_X2) 0.07 0.49 ^ frontend/_4384_/Z (MUX2_X1) 0.06 0.55 ^ core/_18832_/CO (HA_X1) 0.03 0.58 ^ core/place4210/Z (BUF_X4) 0.08 0.65 v core/_10206_/Z (MUX2_X1) 0.05 0.70 ^ core/_10207_/ZN (AOI21_X4) 0.03 0.73 ^ core/place4014/Z (BUF_X4) 0.03 0.76 v core/_10294_/ZN (OAI211_X4) 0.05 0.81 v core/_10330_/ZN (OR2_X4) 0.07 0.88 ^ core/_10977_/ZN (OAI33_X1) 0.04 0.92 ^ rebuffer4848/Z (BUF_X2) 0.03 0.94 ^ rebuffer4861/Z (BUF_X4) 0.02 0.97 ^ clone4847/Z (BUF_X8) 0.02 0.98 ^ core/place3397/Z (BUF_X4) 0.07 1.05 v core/_11231_/Z (MUX2_X1) 0.03 1.08 ^ core/_11235_/ZN (OAI22_X4) 0.02 1.10 v core/_11236_/ZN (NOR4_X4) 0.08 1.18 ^ core/_11256_/ZN (NOR4_X4) 0.05 1.23 v core/_11257_/ZN (OAI221_X2) 0.04 1.27 ^ core/_18794_/ZN (NOR2_X2) 0.02 1.29 v core/_18795_/ZN (NAND2_X2) 0.07 1.36 ^ core/_18797_/ZN (AOI21_X4) 0.02 1.38 v frontend/_3989_/ZN (INV_X8) 0.02 1.40 ^ frontend/_4065_/ZN (NAND3_X4) 0.02 1.42 v frontend/_4067_/ZN (OAI21_X4) 0.06 1.48 ^ frontend/_4068_/ZN (AOI22_X4) 0.04 1.52 ^ frontend/rebuffer4856/Z (BUF_X8) 0.03 1.55 ^ clone5192/Z (BUF_X8) 0.06 1.61 v frontend/_4097_/Z (MUX2_X1) 0.00 1.61 v frontend/fq._T_2_1_data[18]$_DFFE_PP_/D (DFF_X1) 1.61 data arrival time 1.20 1.20 clock core_clock (rise edge) 0.00 1.20 clock source latency 0.00 1.20 ^ clock (in) 0.03 1.23 ^ clkbuf_regs_0_core_clock/Z (CLKBUF_X3) 0.06 1.29 ^ clkbuf_0_clock_regs/Z (CLKBUF_X3) 0.09 1.38 ^ clkbuf_2_2_0_clock_regs/Z (CLKBUF_X3) 0.07 1.45 ^ clkbuf_6_34_0_clock_regs/Z (CLKBUF_X3) 0.04 1.49 ^ clkbuf_leaf_92_clock_regs/Z (CLKBUF_X3) 0.00 1.49 ^ frontend/fq._T_2_1_data[18]$_DFFE_PP_/CK (DFF_X1) 0.00 1.49 clock reconvergence pessimism -0.04 1.46 library setup time 1.46 data required time --------------------------------------------------------- 1.46 data required time -1.61 data arrival time --------------------------------------------------------- -0.15 slack (VIOLATED) ========================================================================== finish report_checks -path_delay min reg to reg -------------------------------------------------------------------------- Startpoint: core/div/neg_out$_SDFFCE_PN0P_ (rising edge-triggered flip-flop clocked by core_clock) Endpoint: core/div/state[4]$_DFF_P_ (rising edge-triggered flip-flop clocked by core_clock) Path Group: core_clock Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock core_clock (rise edge) 0.00 0.00 clock source latency 0.00 0.00 ^ clock (in) 0.03 0.03 ^ clkbuf_regs_0_core_clock/Z (CLKBUF_X3) 0.06 0.09 ^ clkbuf_0_clock_regs/Z (CLKBUF_X3) 0.09 0.18 ^ clkbuf_2_2_0_clock_regs/Z (CLKBUF_X3) 0.07 0.25 ^ clkbuf_6_47_0_clock_regs/Z (CLKBUF_X3) 0.04 0.29 ^ clkbuf_leaf_122_clock_regs/Z (CLKBUF_X3) 0.00 0.29 ^ core/div/neg_out$_SDFFCE_PN0P_/CK (DFF_X1) 0.07 0.36 ^ core/div/neg_out$_SDFFCE_PN0P_/QN (DFF_X1) 0.01 0.37 v core/div/_3989_/ZN (NOR3_X1) 0.00 0.37 v core/div/state[4]$_DFF_P_/D (DFF_X1) 0.37 data arrival time 0.00 0.00 clock core_clock (rise edge) 0.00 0.00 clock source latency 0.00 0.00 ^ clock (in) 0.03 0.03 ^ clkbuf_regs_0_core_clock/Z (CLKBUF_X3) 0.06 0.09 ^ clkbuf_0_clock_regs/Z (CLKBUF_X3) 0.09 0.18 ^ clkbuf_2_2_0_clock_regs/Z (CLKBUF_X3) 0.07 0.25 ^ clkbuf_6_47_0_clock_regs/Z (CLKBUF_X3) 0.04 0.29 ^ clkbuf_leaf_122_clock_regs/Z (CLKBUF_X3) 0.00 0.29 ^ core/div/state[4]$_DFF_P_/CK (DFF_X1) 0.00 0.29 clock reconvergence pessimism 0.00 0.29 library hold time 0.29 data required time --------------------------------------------------------- 0.29 data required time -0.37 data arrival time --------------------------------------------------------- 0.07 slack (MET) ========================================================================== finish critical path target clock latency max path -------------------------------------------------------------------------- 0 ========================================================================== finish critical path target clock latency min path -------------------------------------------------------------------------- 0 ========================================================================== finish critical path source clock latency min path -------------------------------------------------------------------------- 0 ========================================================================== finish critical path delay -------------------------------------------------------------------------- 1.6109 ========================================================================== finish critical path slack -------------------------------------------------------------------------- -0.1530 ========================================================================== finish slack div critical path delay -------------------------------------------------------------------------- -9.497796 ========================================================================== finish report_power -------------------------------------------------------------------------- Group Internal Switching Leakage Total Power Power Power Power (Watts) ---------------------------------------------------------------- Sequential 2.84e-02 3.71e-03 3.02e-04 3.24e-02 36.5% Combinational 1.80e-02 1.99e-02 7.40e-04 3.86e-02 43.5% Clock 6.90e-03 7.94e-03 2.86e-05 1.49e-02 16.8% Macro 2.69e-03 0.00e+00 1.63e-04 2.85e-03 3.2% Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0% ---------------------------------------------------------------- Total 5.59e-02 3.15e-02 1.23e-03 8.87e-02 100.0% 63.1% 35.5% 1.4%