mkdir -p results/nangate45/gcd/n45_u70/ echo 0.46 > results/nangate45/gcd/n45_u70/clock_period.txt /OpenROAD-flow-scripts/flow/scripts/synth.sh /OpenROAD-flow-scripts/flow/scripts/synth_canonicalize.tcl ./logs/nangate45/gcd/n45_u70/1_1_yosys_canonicalize.log Using ABC area script. Extracting clock period from SDC file: ./results/nangate45/gcd/n45_u70/clock_period.txt Setting clock period to 0.46 1. Executing Liberty frontend: /OpenROAD-flow-scripts/flow/platforms/nangate45/lib/NangateOpenCellLibrary_typical.lib 2. Executing Liberty frontend: /OpenROAD-flow-scripts/flow/platforms/nangate45/lib/NangateOpenCellLibrary_typical.lib 3. Executing Verilog-2005 frontend: /OpenROAD-flow-scripts/flow/designs/src/gcd/gcd.v 4. Executing Verilog-2005 frontend: /OpenROAD-flow-scripts/flow/platforms/nangate45/cells_clkgate.v 5. Executing HIERARCHY pass (managing design hierarchy). 6. Executing AST frontend in derive mode using pre-parsed AST for module `\gcd'. 6.1. Analyzing design hierarchy.. 6.2. Executing AST frontend in derive mode using pre-parsed AST for module `\GcdUnitDpathRTL_0x4d0fc71ead8d3d9e'. 6.3. Executing AST frontend in derive mode using pre-parsed AST for module `\GcdUnitCtrlRTL_0x4d0fc71ead8d3d9e'. 6.4. Analyzing design hierarchy.. 6.5. Executing AST frontend in derive mode using pre-parsed AST for module `\RegRst_0x9f365fdf6c8998a'. 6.6. Executing AST frontend in derive mode using pre-parsed AST for module `\RegEn_0x68db79c4ec1d6e5b'. 6.7. Executing AST frontend in derive mode using pre-parsed AST for module `\Subtractor_0x422b1f52edd46a85'. 6.8. Executing AST frontend in derive mode using pre-parsed AST for module `\Mux_0xdd6473406d1a99a'. 6.9. Executing AST frontend in derive mode using pre-parsed AST for module `\Mux_0x683fa1a418b072c9'. 6.10. Executing AST frontend in derive mode using pre-parsed AST for module `\ZeroComparator_0x422b1f52edd46a85'. 6.11. Executing AST frontend in derive mode using pre-parsed AST for module `\LtComparator_0x422b1f52edd46a85'. 6.12. Analyzing design hierarchy.. 6.13. Analyzing design hierarchy.. 7. Executing OPT_CLEAN pass (remove unused cells and wires). Warning: Ignoring module ZeroComparator_0x422b1f52edd46a85 because it contains processes (run 'proc' command first). Warning: Ignoring module Mux_0x683fa1a418b072c9 because it contains processes (run 'proc' command first). Warning: Ignoring module Mux_0xdd6473406d1a99a because it contains processes (run 'proc' command first). Warning: Ignoring module Subtractor_0x422b1f52edd46a85 because it contains processes (run 'proc' command first). Warning: Ignoring module RegEn_0x68db79c4ec1d6e5b because it contains processes (run 'proc' command first). Warning: Ignoring module RegRst_0x9f365fdf6c8998a because it contains processes (run 'proc' command first). Warning: Ignoring module GcdUnitCtrlRTL_0x4d0fc71ead8d3d9e because it contains processes (run 'proc' command first). Warning: Ignoring module LtComparator_0x422b1f52edd46a85 because it contains processes (run 'proc' command first). 8. Executing RTLIL backend. Warnings: 8 unique messages, 8 total End of script. Logfile hash: 01c11a00d2, time: 0.10s, user: 0.07s, system: 0.01s, MEM: 38.75 MB peak Yosys 0.64+post (git sha1 UNKNOWN-dirty, g++ 11.4.0-1ubuntu1~22.04.3 -fPIC -O3) Time spent: 81% 4x read_liberty (0 sec), 6% 4x read_verilog (0 sec), ... Elapsed time: 0:00.11[h:]min:sec. CPU time: user 0.08 sys 0.01 (88%). Peak memory: 43264KB. Log Ext Elapsed/s Peak Memory/MB sha1sum result [0:20) 1_1_yosys_canonicalize .rtlil 0 42 0143866d45d6a9e39c47 /OpenROAD-flow-scripts/flow/scripts/synth.sh /OpenROAD-flow-scripts/flow/scripts/synth.tcl ./logs/nangate45/gcd/n45_u70/1_2_yosys.log Using ABC area script. Extracting clock period from SDC file: ./results/nangate45/gcd/n45_u70/clock_period.txt Setting clock period to 0.46 1. Executing RTLIL frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. 2.2. Analyzing design hierarchy.. 3. Executing SYNTH pass. 3.1. Executing HIERARCHY pass (managing design hierarchy). 3.1.1. Analyzing design hierarchy.. 3.1.2. Analyzing design hierarchy.. 3.2. Executing PROC pass (convert processes to netlists). 3.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 3.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 3.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 3.2.4. Executing PROC_INIT pass (extract init attributes). 3.2.5. Executing PROC_ARST pass (detect async resets in processes). 3.2.6. Executing PROC_ROM pass (convert switches to ROMs). 3.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 3.2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 3.2.9. Executing PROC_DFF pass (convert process syncs to FFs). 3.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 3.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 3.2.12. Executing OPT_EXPR pass (perform const folding). 3.3. Executing FLATTEN pass (flatten design). 3.4. Executing OPT_EXPR pass (perform const folding). 3.5. Executing OPT_CLEAN pass (remove unused cells and wires). 3.6. Executing CHECK pass (checking for obvious problems). 3.7. Executing OPT pass (performing simple optimizations). 3.7.1. Executing OPT_EXPR pass (perform const folding). 3.7.2. Executing OPT_MERGE pass (detect identical cells). 3.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 3.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 3.7.5. Executing OPT_MERGE pass (detect identical cells). 3.7.6. Executing OPT_DFF pass (perform DFF optimizations). 3.7.7. Executing OPT_CLEAN pass (remove unused cells and wires). 3.7.8. Executing OPT_EXPR pass (perform const folding). 3.7.9. Rerunning OPT passes. (Maybe there is more to do..) 3.7.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 3.7.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 3.7.12. Executing OPT_MERGE pass (detect identical cells). 3.7.13. Executing OPT_DFF pass (perform DFF optimizations). 3.7.14. Executing OPT_CLEAN pass (remove unused cells and wires). 3.7.15. Executing OPT_EXPR pass (perform const folding). 3.7.16. Finished fast OPT passes. (There is nothing left to do.) 3.8. Executing FSM pass (extract and optimize FSM). 3.8.1. Executing FSM_DETECT pass (finding FSMs in design). 3.8.2. Executing FSM_EXTRACT pass (extracting FSM from design). 3.8.3. Executing FSM_OPT pass (simple optimizations of FSMs). 3.8.4. Executing OPT_CLEAN pass (remove unused cells and wires). 3.8.5. Executing FSM_OPT pass (simple optimizations of FSMs). 3.8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 3.8.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 3.8.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 3.9. Executing OPT pass (performing simple optimizations). 3.9.1. Executing OPT_EXPR pass (perform const folding). 3.9.2. Executing OPT_MERGE pass (detect identical cells). 3.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 3.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 3.9.5. Executing OPT_MERGE pass (detect identical cells). 3.9.6. Executing OPT_DFF pass (perform DFF optimizations). 3.9.7. Executing OPT_CLEAN pass (remove unused cells and wires). 3.9.8. Executing OPT_EXPR pass (perform const folding). 3.9.9. Rerunning OPT passes. (Maybe there is more to do..) 3.9.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 3.9.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 3.9.12. Executing OPT_MERGE pass (detect identical cells). 3.9.13. Executing OPT_DFF pass (perform DFF optimizations). 3.9.14. Executing OPT_CLEAN pass (remove unused cells and wires). 3.9.15. Executing OPT_EXPR pass (perform const folding). 3.9.16. Finished fast OPT passes. (There is nothing left to do.) 3.10. Executing WREDUCE pass (reducing word size of cells). 3.11. Executing PEEPOPT pass (run peephole optimizers). 3.12. Executing OPT_CLEAN pass (remove unused cells and wires). 3.13. Executing ALUMACC pass (create $alu and $macc cells). 3.14. Executing SHARE pass (SAT-based resource sharing). 3.15. Executing OPT pass (performing simple optimizations). 3.15.1. Executing OPT_EXPR pass (perform const folding). 3.15.2. Executing OPT_MERGE pass (detect identical cells). 3.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 3.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 3.15.5. Executing OPT_MERGE pass (detect identical cells). 3.15.6. Executing OPT_DFF pass (perform DFF optimizations). 3.15.7. Executing OPT_CLEAN pass (remove unused cells and wires). 3.15.8. Executing OPT_EXPR pass (perform const folding). 3.15.9. Rerunning OPT passes. (Maybe there is more to do..) 3.15.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 3.15.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 3.15.12. Executing OPT_MERGE pass (detect identical cells). 3.15.13. Executing OPT_DFF pass (perform DFF optimizations). 3.15.14. Executing OPT_CLEAN pass (remove unused cells and wires). 3.15.15. Executing OPT_EXPR pass (perform const folding). 3.15.16. Finished fast OPT passes. (There is nothing left to do.) 3.16. Executing MEMORY pass. 3.16.1. Executing OPT_MEM pass (optimize memories). 3.16.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). 3.16.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 3.16.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 3.16.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 3.16.6. Executing OPT_CLEAN pass (remove unused cells and wires). 3.16.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 3.16.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). 3.16.9. Executing OPT_CLEAN pass (remove unused cells and wires). 3.16.10. Executing MEMORY_COLLECT pass (generating $mem cells). 3.17. Executing OPT_CLEAN pass (remove unused cells and wires). 4. Executing SYNTH pass. 4.1. Executing OPT pass (performing simple optimizations). 4.1.1. Executing OPT_EXPR pass (perform const folding). 4.1.2. Executing OPT_MERGE pass (detect identical cells). 4.1.3. Executing OPT_DFF pass (perform DFF optimizations). 4.1.4. Executing OPT_CLEAN pass (remove unused cells and wires). 4.1.5. Finished fast OPT passes. 4.2. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 4.3. Executing OPT pass (performing simple optimizations). 4.3.1. Executing OPT_EXPR pass (perform const folding). 4.3.2. Executing OPT_MERGE pass (detect identical cells). 4.3.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 4.3.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 4.3.5. Executing OPT_MERGE pass (detect identical cells). 4.3.6. Executing OPT_SHARE pass. 4.3.7. Executing OPT_DFF pass (perform DFF optimizations). 4.3.8. Executing OPT_CLEAN pass (remove unused cells and wires). 4.3.9. Executing OPT_EXPR pass (perform const folding). 4.3.10. Finished fast OPT passes. (There is nothing left to do.) 4.4. Executing TECHMAP pass (map to technology primitives). 4.4.1. Executing Verilog-2005 frontend: /OpenROAD-flow-scripts/tools/install/yosys/bin/../share/yosys/techmap.v 4.4.2. Executing Verilog-2005 frontend: /OpenROAD-flow-scripts/flow/platforms/common/lcu_kogge_stone.v 4.4.3. Continuing TECHMAP pass. 4.5. Executing OPT pass (performing simple optimizations). 4.5.1. Executing OPT_EXPR pass (perform const folding). 4.5.2. Executing OPT_MERGE pass (detect identical cells). 4.5.3. Executing OPT_DFF pass (perform DFF optimizations). 4.5.4. Executing OPT_CLEAN pass (remove unused cells and wires). 4.5.5. Finished fast OPT passes. 4.6. Executing HIERARCHY pass (managing design hierarchy). 4.6.1. Analyzing design hierarchy.. 4.6.2. Analyzing design hierarchy.. 4.7. Printing statistics. 4.8. Executing CHECK pass (checking for obvious problems). 5. Executing OPT pass (performing simple optimizations). 5.1. Executing OPT_EXPR pass (perform const folding). 5.2. Executing OPT_MERGE pass (detect identical cells). 5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 5.5. Executing OPT_MERGE pass (detect identical cells). 5.6. Executing OPT_DFF pass (perform DFF optimizations). 5.7. Executing OPT_CLEAN pass (remove unused cells and wires). 5.8. Executing OPT_EXPR pass (perform const folding). 5.9. Rerunning OPT passes. (Maybe there is more to do..) 5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 5.12. Executing OPT_MERGE pass (detect identical cells). 5.13. Executing OPT_DFF pass (perform DFF optimizations). 5.14. Executing OPT_CLEAN pass (remove unused cells and wires). 5.15. Executing OPT_EXPR pass (perform const folding). 5.16. Finished fast OPT passes. (There is nothing left to do.) 6. Executing TECHMAP pass (map to technology primitives). 6.1. Executing Verilog-2005 frontend: /OpenROAD-flow-scripts/flow/platforms/nangate45/cells_latch.v 6.2. Continuing TECHMAP pass. 7. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file). 7.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 8. Executing OPT pass (performing simple optimizations). 8.1. Executing OPT_EXPR pass (perform const folding). 8.2. Executing OPT_MERGE pass (detect identical cells). 8.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 8.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 8.5. Executing OPT_MERGE pass (detect identical cells). 8.6. Executing OPT_DFF pass (perform DFF optimizations). 8.7. Executing OPT_CLEAN pass (remove unused cells and wires). 8.8. Executing OPT_EXPR pass (perform const folding). 8.9. Rerunning OPT passes. (Maybe there is more to do..) 8.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 8.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 8.12. Executing OPT_MERGE pass (detect identical cells). 8.13. Executing OPT_DFF pass (perform DFF optimizations). 8.14. Executing OPT_CLEAN pass (remove unused cells and wires). 8.15. Executing OPT_EXPR pass (perform const folding). 8.16. Finished fast OPT passes. (There is nothing left to do.) 9. Executing SETUNDEF pass (replace undef values with defined constants). abc -script /OpenROAD-flow-scripts/flow/scripts/abc_area.script -liberty /OpenROAD-flow-scripts/flow/platforms/nangate45/lib/NangateOpenCellLibrary_typical.lib -dont_use TAPCELL_X1 -dont_use FILLCELL_X1 -dont_use AOI211_X1 -dont_use OAI211_X1 -constr ./objects/nangate45/gcd/n45_u70/abc.constr -D 0.46 10. Executing ABC pass (technology mapping using ABC). 10.1. Extracting gate netlist of module `\gcd' to `/input.blif'.. 10.1.1. Executed ABC. 10.1.2. Re-integrating ABC results. 11. Executing SPLITNETS pass (splitting up multi-bit signals). 12. Executing OPT_CLEAN pass (remove unused cells and wires). 13. Executing HILOMAP pass (mapping to constant drivers). 14. Executing INSBUF pass (insert buffer cells for connected wires). 15. Executing CHECK pass (checking for obvious problems). 16. Printing statistics. 17. Executing CHECK pass (checking for obvious problems). 18. Executing Verilog backend. 18.1. Executing BMUXMAP pass. 18.2. Executing DEMUXMAP pass. exec cp /OpenROAD-flow-scripts/flow/designs/nangate45/gcd/constraint.sdc ./results/nangate45/gcd/n45_u70/1_synth.sdc End of script. Logfile hash: a3fb6e1030, time: 0.41s, user: 0.16s, system: 0.06s, MEM: 42.75 MB peak Yosys 0.64+post (git sha1 UNKNOWN-dirty, g++ 11.4.0-1ubuntu1~22.04.3 -fPIC -O3) Time spent: 43% 1x abc (0 sec), 9% 21x opt_clean (0 sec), ... Elapsed time: 0:00.41[h:]min:sec. CPU time: user 0.33 sys 0.08 (97%). Peak memory: 45568KB. Log Ext Elapsed/s Peak Memory/MB sha1sum result [0:20) 1_2_yosys .v 0 44 756ad24f74de658d5044 cp /OpenROAD-flow-scripts/flow/designs/nangate45/gcd/constraint.sdc ./results/nangate45/gcd/n45_u70/1_2_yosys.sdc OpenROAD 26Q3-173-gf5df0085c2 Features included (+) or not (-): +GPU +GUI +Python This program is licensed under the BSD-3 license. See the LICENSE file for details. Components of this program may be licensed under more restrictive licenses which must be honored. [INFO ORD-0030] Using 32 thread(s). mkdir -p ./objects/nangate45/gcd/n45_u70 /OpenROAD-flow-scripts/flow/scripts/flow.sh 1_synth synth_odb Running synth_odb.tcl, stage 1_synth read_liberty /OpenROAD-flow-scripts/flow/platforms/nangate45/lib/NangateOpenCellLibrary_typical.lib [INFO ODB-0227] LEF file: /OpenROAD-flow-scripts/flow/platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef, created 22 layers, 27 vias [INFO ODB-0227] LEF file: /OpenROAD-flow-scripts/flow/platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef, created 135 library cells link_design gcd read_sdc ./results/nangate45/gcd/n45_u70/1_2_yosys.sdc source /OpenROAD-flow-scripts/flow/platforms/nangate45/setRC.tcl eliminate_dead_logic Removed 0 unused instances and 0 unused nets. Design area 663 um^2 100% utilization. write_db ./results/nangate45/gcd/n45_u70/1_synth.odb write_sdc -no_timestamp ./results/nangate45/gcd/n45_u70/1_synth.sdc Elapsed time: 0:00.37[h:]min:sec. CPU time: user 0.23 sys 0.03 (69%). Peak memory: 115400KB. Log Ext Elapsed/s Peak Memory/MB sha1sum result [0:20) 1_synth .odb 0 112 5574db6bc0e99d58e06a 1_synth .sdc 7fe61694c034e1755ac1 /OpenROAD-flow-scripts/flow/scripts/flow.sh 2_1_floorplan floorplan Running floorplan.tcl, stage 2_1_floorplan read_liberty /OpenROAD-flow-scripts/flow/platforms/nangate45/lib/NangateOpenCellLibrary_typical.lib read_db ./results/nangate45/gcd/n45_u70/1_synth.odb read_sdc ./results/nangate45/gcd/n45_u70/1_synth.sdc source /OpenROAD-flow-scripts/flow/platforms/nangate45/setRC.tcl ========================================================================== Floorplan check_setup -------------------------------------------------------------------------- number instances in verilog is 521 [INFO IFP-0107] Defining die area using utilization: 70.00% and aspect ratio: 1. [WARNING IFP-0028] Core area lower left (1.000, 1.000) snapped to (1.140, 1.400). [INFO IFP-0001] Added 21 rows of 161 site FreePDK45_38x28_10R_NP_162NW_34O. [INFO IFP-0100] Die BBox: ( 0.000 0.000 ) ( 32.780 32.780 ) um [INFO IFP-0101] Core BBox: ( 1.140 1.400 ) ( 31.730 30.800 ) um [INFO IFP-0102] Core area: 899.346 um^2 [INFO IFP-0103] Total instances area: 663.138 um^2 [INFO IFP-0104] Effective utilization: 0.737 [INFO IFP-0105] Number of instances: 521 source /OpenROAD-flow-scripts/flow/platforms/nangate45/make_tracks.tcl source /OpenROAD-flow-scripts/flow/platforms/nangate45/fastroute.tcl Repair tie lo fanout... Repair tie hi fanout... repair_timing -setup_margin 0 -hold_margin 0 -repair_tns 100 -setup -skip_last_gasp -sequence unbuffer,sizeup,swap,vt_swap -verbose [WARNING EST-0027] no estimated parasitics. Using wire load models. [INFO RSZ-0100] Repair move sequence: UnbufferMove SizeUpMove SwapPinsMove [INFO RSZ-0098] No setup violations found [INFO RSZ-0505] Runtime: 0.03s Default units for flow time 1ns capacitance 1fF resistance 1kohm voltage 1v current 1mA power 1nW distance 1um Layer | Unit Resistance | Unit Capacitance | (kohm/um) | (fF/um) ------------------------------------------------ metal1 | 5.43e-03 | 7.42e-02 metal2 | 3.57e-03 | 8.34e-02 metal3 | 3.57e-03 | 1.04e-01 metal4 | 1.50e-03 | 1.19e-01 metal5 | 1.50e-03 | 1.09e-01 metal6 | 1.50e-03 | 1.14e-01 metal7 | 1.88e-04 | 1.17e-01 metal8 | 1.88e-04 | 9.45e-02 metal9 | 3.75e-05 | 1.06e-01 metal10 | 3.75e-05 | 7.37e-01 ------------------------------------------------ Layer | Via Resistance | (kohm) ---------------------------- via1 | 5.00e-03 via2 | 5.00e-03 via3 | 5.00e-03 via4 | 3.00e-03 via5 | 3.00e-03 via6 | 3.00e-03 via7 | 1.00e-03 via8 | 1.00e-03 via9 | 5.00e-04 ---------------------------- Report metrics stage 2, floorplan final... ========================================================================== floorplan final report_design_area -------------------------------------------------------------------------- Design area 663 um^2 74% utilization. write_db ./results/nangate45/gcd/n45_u70/2_1_floorplan.odb write_sdc -no_timestamp ./results/nangate45/gcd/n45_u70/2_1_floorplan.sdc Elapsed time: 0:00.50[h:]min:sec. CPU time: user 0.27 sys 0.06 (65%). Peak memory: 135352KB. Log Ext Elapsed/s Peak Memory/MB sha1sum result [0:20) 2_1_floorplan .odb 0 132 4240d65985da96c5decc 2_1_floorplan .sdc 7fe61694c034e1755ac1 /OpenROAD-flow-scripts/flow/scripts/flow.sh 2_2_floorplan_macro macro_place Running macro_place.tcl, stage 2_2_floorplan_macro read_liberty /OpenROAD-flow-scripts/flow/platforms/nangate45/lib/NangateOpenCellLibrary_typical.lib read_db ./results/nangate45/gcd/n45_u70/2_1_floorplan.odb read_sdc ./results/nangate45/gcd/n45_u70/2_1_floorplan.sdc source /OpenROAD-flow-scripts/flow/platforms/nangate45/setRC.tcl No macros found: Skipping macro_placement Design area 663 um^2 74% utilization. write_db ./results/nangate45/gcd/n45_u70/2_2_floorplan_macro.odb Elapsed time: 0:00.25[h:]min:sec. CPU time: user 0.21 sys 0.04 (97%). Peak memory: 113092KB. Log Ext Elapsed/s Peak Memory/MB sha1sum result [0:20) 2_2_floorplan_macro .odb 0 110 4240d65985da96c5decc /OpenROAD-flow-scripts/flow/scripts/flow.sh 2_3_floorplan_tapcell tapcell Running tapcell.tcl, stage 2_3_floorplan_tapcell read_liberty /OpenROAD-flow-scripts/flow/platforms/nangate45/lib/NangateOpenCellLibrary_typical.lib read_db ./results/nangate45/gcd/n45_u70/2_2_floorplan_macro.odb read_sdc ./results/nangate45/gcd/n45_u70/2_1_floorplan.sdc source /OpenROAD-flow-scripts/flow/platforms/nangate45/setRC.tcl [INFO TAP-0004] Inserted 42 endcaps. [INFO TAP-0005] Inserted 0 tapcells. Design area 674 um^2 75% utilization. write_db ./results/nangate45/gcd/n45_u70/2_3_floorplan_tapcell.odb Elapsed time: 0:00.33[h:]min:sec. CPU time: user 0.21 sys 0.03 (75%). Peak memory: 113336KB. Log Ext Elapsed/s Peak Memory/MB sha1sum result [0:20) 2_3_floorplan_tapcell .odb 0 110 146da835d710a360cd2e /OpenROAD-flow-scripts/flow/scripts/flow.sh 2_4_floorplan_pdn pdn Running pdn.tcl, stage 2_4_floorplan_pdn read_liberty /OpenROAD-flow-scripts/flow/platforms/nangate45/lib/NangateOpenCellLibrary_typical.lib read_db ./results/nangate45/gcd/n45_u70/2_3_floorplan_tapcell.odb read_sdc ./results/nangate45/gcd/n45_u70/2_1_floorplan.sdc source /OpenROAD-flow-scripts/flow/platforms/nangate45/setRC.tcl [INFO PDN-0001] Inserting grid: grid [INFO PDN-0500] Runtime: 0.00s Design area 674 um^2 75% utilization. write_db ./results/nangate45/gcd/n45_u70/2_4_floorplan_pdn.odb Elapsed time: 0:00.26[h:]min:sec. CPU time: user 0.22 sys 0.03 (96%). Peak memory: 115644KB. Log Ext Elapsed/s Peak Memory/MB sha1sum result [0:20) 2_4_floorplan_pdn .odb 0 112 ff5696052aa6d457e774 cp ./results/nangate45/gcd/n45_u70/2_4_floorplan_pdn.odb ./results/nangate45/gcd/n45_u70/2_floorplan.odb cp ./results/nangate45/gcd/n45_u70/2_1_floorplan.sdc ./results/nangate45/gcd/n45_u70/2_floorplan.sdc /OpenROAD-flow-scripts/flow/scripts/flow.sh 3_1_place_gp_skip_io global_place_skip_io Running global_place_skip_io.tcl, stage 3_1_place_gp_skip_io read_liberty /OpenROAD-flow-scripts/flow/platforms/nangate45/lib/NangateOpenCellLibrary_typical.lib read_db ./results/nangate45/gcd/n45_u70/2_floorplan.odb read_sdc ./results/nangate45/gcd/n45_u70/2_floorplan.sdc source /OpenROAD-flow-scripts/flow/platforms/nangate45/setRC.tcl [INFO GPL-0022] Initialize gpl and calculate uniform density. Placement density is 0.8900000190734864, computed from PLACE_DENSITY_LB_ADDON 0.20 and lower bound 0.8500000238418579 global_placement -skip_io -density 0.8900000190734864 -pad_left 0 -pad_right 0 [INFO GPL-0001] ---- Initialize GPL Main Data Structures [INFO GPL-0002] DBU: 2000 [INFO GPL-0003] SiteSize: ( 0.190 1.400 ) um [INFO GPL-0004] CoreBBox: ( 1.140 1.400 ) ( 31.730 30.800 ) um [INFO GPL-0036] Movable instances area: 663.138 um^2 [INFO GPL-0037] Total instances area: 674.310 um^2 [INFO GPL-0035] Pin density area adjust: 86.630 um^2 [INFO GPL-0032] ---- Initialize Region: Top-level [INFO GPL-0006] Number of instances: 563 [INFO GPL-0007] Movable instances: 521 [INFO GPL-0008] Fixed instances: 42 [INFO GPL-0009] Dummy instances: 0 [INFO GPL-0010] Number of nets: 592 [INFO GPL-0011] Number of pins: 1644 [INFO GPL-0012] Die BBox: ( 0.000 0.000 ) ( 32.780 32.780 ) um [INFO GPL-0013] Core BBox: ( 1.140 1.400 ) ( 31.730 30.800 ) um [INFO GPL-0016] Core area: 899.346 um^2 [INFO GPL-0014] Region name: top-level. [INFO GPL-0015] Region area: 899.346 um^2 [INFO GPL-0017] Fixed instances area: 11.172 um^2 [INFO GPL-0018] Movable instances area: 749.768 um^2 [INFO GPL-0019] Utilization: 84.417 % [INFO GPL-0020] Standard cells area: 749.768 um^2 [INFO GPL-0021] Large instances area: 0.000 um^2 [INFO GPL-0005] ---- Execute Conjugate Gradient Initial Placement. [INFO GPL-0051] Source of initial instance position counters: Odb location = 0 Core center = 521 Region center = 0 [INFO GPL-0033] ---- Initialize Nesterov Region: Top-level [INFO GPL-0023] Placement target density: 0.8900 [INFO GPL-0024] Movable insts average area: 1.439 um^2 [INFO GPL-0025] Ideal bin area: 1.617 um^2 [INFO GPL-0026] Ideal bin count: 556 [INFO GPL-0027] Total bin area: 899.346 um^2 [INFO GPL-0028] Bin count (X, Y): 16 , 16 [INFO GPL-0029] Bin size (W * H): 1.912 * 1.837 um [INFO GPL-0030] Number of bins: 256 [INFO GPL-0084] ---- Execute Nesterov Global Placement. [INFO GPL-0031] HPWL: Half-Perimeter Wirelength Iteration | Overflow | HPWL (um) | HPWL(%) | Penalty | Group --------------------------------------------------------------- 0 | 0.9828 | 3.146380e+02 | +0.00% | 4.24e-14 | 10 | 0.9730 | 2.289135e+02 | -27.25% | 6.90e-14 | 20 | 0.9723 | 2.274520e+02 | -0.64% | 1.12e-13 | 30 | 0.9723 | 2.272290e+02 | -0.10% | 1.83e-13 | 40 | 0.9723 | 2.273050e+02 | +0.03% | 2.98e-13 | 50 | 0.9723 | 2.273405e+02 | +0.02% | 4.86e-13 | 60 | 0.9722 | 2.273835e+02 | +0.02% | 7.91e-13 | 70 | 0.9722 | 2.274720e+02 | +0.04% | 1.29e-12 | 80 | 0.9721 | 2.276190e+02 | +0.06% | 2.10e-12 | 90 | 0.9719 | 2.279465e+02 | +0.14% | 3.42e-12 | 100 | 0.9717 | 2.285095e+02 | +0.25% | 5.57e-12 | 110 | 0.9712 | 2.298285e+02 | +0.58% | 9.07e-12 | 120 | 0.9700 | 2.328335e+02 | +1.31% | 1.48e-11 | 130 | 0.9662 | 2.446425e+02 | +5.07% | 2.41e-11 | 140 | 0.9589 | 3.242490e+02 | +32.54% | 3.92e-11 | 150 | 0.9252 | 4.687345e+02 | +44.56% | 6.39e-11 | 160 | 0.9040 | 5.850570e+02 | +24.82% | 1.04e-10 | 170 | 0.8637 | 7.596830e+02 | +29.85% | 1.69e-10 | 180 | 0.8491 | 8.543385e+02 | +12.46% | 2.76e-10 | 190 | 0.8055 | 1.014973e+03 | +18.80% | 4.50e-10 | 200 | 0.7715 | 1.119823e+03 | +10.33% | 7.32e-10 | 210 | 0.7266 | 1.261688e+03 | +12.67% | 1.19e-09 | 220 | 0.6801 | 1.401706e+03 | +11.10% | 1.94e-09 | 230 | 0.6348 | 1.518420e+03 | +8.33% | 3.16e-09 | 240 | 0.5849 | 1.654544e+03 | +8.96% | 5.15e-09 | 250 | 0.5359 | 1.781337e+03 | +7.66% | 8.40e-09 | 260 | 0.4814 | 1.888165e+03 | +6.00% | 1.37e-08 | 270 | 0.4275 | 1.983749e+03 | +5.06% | 2.23e-08 | 280 | 0.3726 | 2.070070e+03 | +4.35% | 3.63e-08 | 290 | 0.3156 | 2.114881e+03 | +2.16% | 5.68e-08 | 300 | 0.2738 | 2.151896e+03 | +1.75% | 8.36e-08 | 310 | 0.2422 | 2.204805e+03 | +2.46% | 1.23e-07 | 320 | 0.2100 | 2.229191e+03 | +1.11% | 1.82e-07 | 330 | 0.1797 | 2.243044e+03 | +0.62% | 2.67e-07 | 340 | 0.1530 | 2.256141e+03 | +0.58% | 3.94e-07 | 350 | 0.1332 | 2.266370e+03 | +0.45% | 5.80e-07 | 360 | 0.1137 | 2.274747e+03 | +0.37% | 8.55e-07 | 367 | 0.0998 | 2.276061e+03 | | 1.17e-06 | --------------------------------------------------------------- [INFO GPL-1001] Global placement finished at iteration 367 [INFO GPL-1002] Placed Cell Area 749.7678 [INFO GPL-1003] Available Free Area 888.1740 [INFO GPL-1004] Minimum Feasible Density 0.8500 (cell_area / free_area) [INFO GPL-1006] Suggested Target Densities: [INFO GPL-1007] - For 90% usage of free space: 0.9380 [INFO GPL-1008] - For 80% usage of free space: 1.0552 [INFO GPL-1014] Final placement area: 749.77 (+0.00%) Took 211 seconds: global_placement -skip_io -density 0.8900000190734864 -pad_left 0 -pad_right 0 Design area 674 um^2 75% utilization. write_db ./results/nangate45/gcd/n45_u70/3_1_place_gp_skip_io.odb Elapsed time: 3:33.64[h:]min:sec. CPU time: user 1036.10 sys 0.69 (485%). Peak memory: 115140KB. Log Ext Elapsed/s Peak Memory/MB sha1sum result [0:20) 3_1_place_gp_skip_io .odb 213 112 a2146838052c266263cb /OpenROAD-flow-scripts/flow/scripts/flow.sh 3_2_place_iop io_placement Running io_placement.tcl, stage 3_2_place_iop read_liberty /OpenROAD-flow-scripts/flow/platforms/nangate45/lib/NangateOpenCellLibrary_typical.lib read_db ./results/nangate45/gcd/n45_u70/3_1_place_gp_skip_io.odb read_sdc ./results/nangate45/gcd/n45_u70/2_floorplan.sdc source /OpenROAD-flow-scripts/flow/platforms/nangate45/setRC.tcl place_pins -hor_layers metal5 -ver_layers metal6 Found 0 macro blocks. Using 2 tracks default min distance between IO pins. [INFO PPL-0001] Number of available slots 220 [INFO PPL-0002] Number of I/O 54 [INFO PPL-0003] Number of I/O w/sink 54 [INFO PPL-0004] Number of I/O w/o sink 0 [INFO PPL-0005] Slots per section 200 [INFO PPL-0008] Successfully assigned pins to sections. [INFO PPL-0012] I/O nets HPWL: 522.44 um. Design area 674 um^2 75% utilization. write_db ./results/nangate45/gcd/n45_u70/3_2_place_iop.odb Elapsed time: 0:00.34[h:]min:sec. CPU time: user 0.24 sys 0.03 (77%). Peak memory: 114352KB. Log Ext Elapsed/s Peak Memory/MB sha1sum result [0:20) 3_2_place_iop .odb 0 111 1f672fe287f84b17c1ee /OpenROAD-flow-scripts/flow/scripts/flow.sh 3_3_place_gp global_place Running global_place.tcl, stage 3_3_place_gp read_liberty /OpenROAD-flow-scripts/flow/platforms/nangate45/lib/NangateOpenCellLibrary_typical.lib read_db ./results/nangate45/gcd/n45_u70/3_2_place_iop.odb read_sdc ./results/nangate45/gcd/n45_u70/2_floorplan.sdc source /OpenROAD-flow-scripts/flow/platforms/nangate45/setRC.tcl [INFO RSZ-0026] Removed 17 buffers. Perform port buffering... [INFO RSZ-0027] Inserted 35 BUF_X1 input buffers. [INFO RSZ-0028] Inserted 18 BUF_X1 output buffers. [INFO GPL-0022] Initialize gpl and calculate uniform density. Placement density is 0.8980000114440918, computed from PLACE_DENSITY_LB_ADDON 0.20 and lower bound 0.8600000143051147 global_placement -density 0.8980000114440918 -pad_left 0 -pad_right 0 -routability_driven -timing_driven -force_center_initial_place -min_phi_coef 0.95 -max_phi_coef 1.05 [INFO GPL-0001] ---- Initialize GPL Main Data Structures [INFO GPL-0002] DBU: 2000 [INFO GPL-0003] SiteSize: ( 0.190 1.400 ) um [INFO GPL-0004] CoreBBox: ( 1.140 1.400 ) ( 31.730 30.800 ) um [INFO GPL-0036] Movable instances area: 675.640 um^2 [INFO GPL-0037] Total instances area: 686.812 um^2 [INFO GPL-0035] Pin density area adjust: 85.983 um^2 [INFO GPL-0032] ---- Initialize Region: Top-level [INFO GPL-0006] Number of instances: 599 [INFO GPL-0007] Movable instances: 557 [INFO GPL-0008] Fixed instances: 42 [INFO GPL-0009] Dummy instances: 0 [INFO GPL-0010] Number of nets: 628 [INFO GPL-0011] Number of pins: 1770 [INFO GPL-0012] Die BBox: ( 0.000 0.000 ) ( 32.780 32.780 ) um [INFO GPL-0013] Core BBox: ( 1.140 1.400 ) ( 31.730 30.800 ) um [INFO GPL-0016] Core area: 899.346 um^2 [INFO GPL-0014] Region name: top-level. [INFO GPL-0015] Region area: 899.346 um^2 [INFO GPL-0017] Fixed instances area: 11.172 um^2 [INFO GPL-0018] Movable instances area: 761.623 um^2 [INFO GPL-0019] Utilization: 85.752 % [INFO GPL-0020] Standard cells area: 761.623 um^2 [INFO GPL-0021] Large instances area: 0.000 um^2 [INFO GPL-0005] ---- Execute Conjugate Gradient Initial Placement. [INFO GPL-0051] Source of initial instance position counters: Odb location = 0 Core center = 557 Region center = 0 [InitialPlace] Iter: 1 conjugate gradient residual: 0.00000010 HPWL: 7988430 [InitialPlace] Iter: 2 conjugate gradient residual: 0.00000010 HPWL: 5685497 [InitialPlace] Iter: 3 conjugate gradient residual: 0.00000009 HPWL: 5688112 [InitialPlace] Iter: 4 conjugate gradient residual: 0.00000010 HPWL: 5690951 [InitialPlace] Iter: 5 conjugate gradient residual: 0.00000010 HPWL: 5692986 [INFO GPL-0033] ---- Initialize Nesterov Region: Top-level [INFO GPL-0023] Placement target density: 0.8980 [INFO GPL-0024] Movable insts average area: 1.367 um^2 [INFO GPL-0025] Ideal bin area: 1.523 um^2 [INFO GPL-0026] Ideal bin count: 590 [INFO GPL-0027] Total bin area: 899.346 um^2 [INFO GPL-0028] Bin count (X, Y): 16 , 16 [INFO GPL-0029] Bin size (W * H): 1.912 * 1.837 um [INFO GPL-0030] Number of bins: 256 [INFO GPL-0084] ---- Execute Nesterov Global Placement. [INFO GPL-0031] HPWL: Half-Perimeter Wirelength Iteration | Overflow | HPWL (um) | HPWL(%) | Penalty | Group --------------------------------------------------------------- 0 | 0.8720 | 1.339886e+03 | +0.00% | 3.72e-14 | 10 | 0.7516 | 1.609516e+03 | +20.12% | 6.05e-14 | 20 | 0.7349 | 1.632260e+03 | +1.41% | 9.86e-14 | 30 | 0.7328 | 1.635481e+03 | +0.20% | 1.61e-13 | 40 | 0.7300 | 1.632911e+03 | -0.16% | 2.62e-13 | 50 | 0.7278 | 1.639067e+03 | +0.38% | 4.26e-13 | 60 | 0.7276 | 1.640361e+03 | +0.08% | 6.94e-13 | 70 | 0.7282 | 1.636722e+03 | -0.22% | 1.13e-12 | 80 | 0.7288 | 1.635186e+03 | -0.09% | 1.84e-12 | 90 | 0.7288 | 1.635361e+03 | +0.01% | 3.00e-12 | 100 | 0.7286 | 1.636102e+03 | +0.05% | 4.89e-12 | 110 | 0.7275 | 1.638128e+03 | +0.12% | 7.96e-12 | 120 | 0.7262 | 1.641145e+03 | +0.18% | 1.30e-11 | 130 | 0.7250 | 1.644439e+03 | +0.20% | 2.11e-11 | 140 | 0.7231 | 1.648911e+03 | +0.27% | 3.44e-11 | 150 | 0.7199 | 1.656398e+03 | +0.45% | 5.60e-11 | 160 | 0.7149 | 1.668114e+03 | +0.71% | 9.13e-11 | 170 | 0.7081 | 1.686072e+03 | +1.08% | 1.49e-10 | 180 | 0.6975 | 1.712273e+03 | +1.55% | 2.42e-10 | 190 | 0.6824 | 1.747798e+03 | +2.07% | 3.94e-10 | 200 | 0.6680 | 1.792794e+03 | +2.57% | 6.43e-10 | 210 | 0.6372 | 1.846859e+03 | +3.02% | 1.05e-09 | [INFO GPL-0100] Timing-driven iteration 1/2, virtual: false. [INFO GPL-0101] Iter: 212, overflow: 0.634, keep resizer changes at: 1, HPWL: 3703853 Iteration | Area | Resized | Buffers | Nets repaired | Remaining --------------------------------------------------------------------- 0 | +0.0% | 0 | 0 | 0 | 628 final | +0.0% | 0 | 0 | 0 | 0 --------------------------------------------------------------------- Iter | Area | Removed | Inserted | Pins | | Buffers | Buffers | Remaining ------------------------------------------------------- 0 | +0.0% | 0 | 0 | 592 59 | +0.0% | 0 | 0 | 533 118 | +0.2% | 0 | 2 | 474 177 | +1.3% | 0 | 6 | 415 236 | +1.4% | 0 | 7 | 356 295 | +1.6% | 0 | 9 | 297 354 | +1.8% | 0 | 10 | 238 413 | +2.2% | 0 | 14 | 179 472 | +2.6% | 0 | 17 | 120 531 | +2.6% | 0 | 17 | 61 590 | +2.7% | 0 | 18 | 2 final | +2.7% | 0 | 18 | 0 ------------------------------------------------------- [INFO GPL-0106] Timing-driven: worst slack 1.9423685e-11 [INFO GPL-0107] Timing-driven: repair_design delta area: 18.886 um^2 (+2.48%) [INFO GPL-0108] Timing-driven: repair_design, gpl delta gcells: 18 (+3.23%) [INFO GPL-0109] Timing-driven: repair_design, gcells created: 18, deleted: 0 [INFO GPL-0110] Timing-driven: new target density: 0.9192639 Iteration | Overflow | HPWL (um) | HPWL(%) | Penalty | Group --------------------------------------------------------------- 220 | 0.6116 | 2.012034e+03 | +8.94% | 1.70e-09 | [INFO GPL-0038] Routability snapshot saved at iter = 226 225 | 0.5979 | 2.008616e+03 | | | 230 | 0.5835 | 2.022263e+03 | +0.51% | 2.78e-09 | 240 | 0.5386 | 2.090376e+03 | +3.37% | 4.52e-09 | 250 | 0.4939 | 2.162512e+03 | +3.45% | 7.37e-09 | 260 | 0.4543 | 2.209202e+03 | +2.16% | 1.20e-08 | 270 | 0.4106 | 2.257614e+03 | +2.19% | 1.95e-08 | 280 | 0.3583 | 2.315492e+03 | +2.56% | 3.18e-08 | 290 | 0.3181 | 2.371534e+03 | +2.42% | 4.83e-08 | [INFO GPL-0040] Routability iteration: 1 [INFO GPL-0041] Total routing overflow: 0.0000 [INFO GPL-0042] Number of overflowed tiles: 0 (0.00%) [INFO GPL-0043] Average top 0.5% routing congestion: 0.7099 [INFO GPL-0044] Average top 1.0% routing congestion: 0.7025 [INFO GPL-0045] Average top 2.0% routing congestion: 0.6993 [INFO GPL-0046] Average top 5.0% routing congestion: 0.6928 [INFO GPL-0047] Routability iteration weighted routing congestion: 0.7062 [INFO GPL-0050] Weighted routing congestion is lower than target routing congestion(1.0100), end routability optimization. [INFO GPL-0090] Routability finished. Target routing congestion achieved succesfully. Iteration | Overflow | HPWL (um) | HPWL(%) | Penalty | Group --------------------------------------------------------------- 300 | 0.2817 | 2.416327e+03 | +1.89% | 7.12e-08 | 310 | 0.2435 | 2.454035e+03 | +1.56% | 1.05e-07 | 320 | 0.2111 | 2.484034e+03 | +1.22% | 1.55e-07 | 330 | 0.1972 | 2.516046e+03 | +1.29% | 2.28e-07 | [INFO GPL-0100] Timing-driven iteration 2/2, virtual: false. [INFO GPL-0101] Iter: 333, overflow: 0.193, keep resizer changes at: 1, HPWL: 5045889 Iteration | Area | Resized | Buffers | Nets repaired | Remaining --------------------------------------------------------------------- 0 | +0.0% | 0 | 0 | 0 | 646 final | +0.0% | 0 | 0 | 0 | 0 --------------------------------------------------------------------- Iter | Area | Removed | Inserted | Pins | | Buffers | Buffers | Remaining ------------------------------------------------------- 0 | +0.0% | 0 | 0 | 592 59 | +0.0% | 0 | 0 | 533 118 | -0.2% | 2 | 0 | 474 177 | -0.6% | 6 | 4 | 415 236 | -0.7% | 7 | 4 | 356 295 | -0.7% | 9 | 6 | 297 354 | -0.6% | 10 | 8 | 238 413 | -0.9% | 14 | 9 | 179 472 | -1.1% | 17 | 11 | 120 531 | -1.1% | 17 | 11 | 61 590 | -0.9% | 18 | 13 | 2 final | -0.9% | 18 | 13 | 0 ------------------------------------------------------- [INFO GPL-0106] Timing-driven: worst slack 1.6100926e-11 [INFO GPL-0107] Timing-driven: repair_design delta area: -6.650 um^2 (-0.85%) [INFO GPL-0108] Timing-driven: repair_design, gpl delta gcells: -5 (-0.87%) [INFO GPL-0109] Timing-driven: repair_design, gcells created: 13, deleted: 18 [INFO GPL-0110] Timing-driven: new target density: 0.91177666 Iteration | Overflow | HPWL (um) | HPWL(%) | Penalty | Group --------------------------------------------------------------- 340 | 0.1697 | 2.510861e+03 | -0.21% | 3.35e-07 | 350 | 0.1466 | 2.514347e+03 | +0.14% | 4.94e-07 | 360 | 0.1289 | 2.516113e+03 | +0.07% | 7.28e-07 | 370 | 0.1033 | 2.516269e+03 | +0.01% | 1.07e-06 | 373 | 0.0988 | 2.520110e+03 | | 1.25e-06 | --------------------------------------------------------------- [INFO GPL-1001] Global placement finished at iteration 373 [INFO GPL-1017] Routability mode iteration count: 70 [INFO GPL-1005] Routability final weighted congestion: 0.6994 [INFO GPL-1002] Placed Cell Area 773.8588 [INFO GPL-1003] Available Free Area 888.1740 [INFO GPL-1004] Minimum Feasible Density 0.8600 (cell_area / free_area) [INFO GPL-1006] Suggested Target Densities: [INFO GPL-1007] - For 90% usage of free space: 0.9681 [INFO GPL-1008] - For 80% usage of free space: 1.0891 [INFO GPL-1011] Original area (um^2): 761.62 [INFO GPL-1012] Total routability artificial inflation: 0.00 (+0.00%) [INFO GPL-1013] Total timing-driven delta area: 12.24 (+1.61%) [INFO GPL-1014] Final placement area: 773.86 (+1.61%) Took 302 seconds: global_placement -density 0.8980000114440918 -pad_left 0 -pad_right 0 -routability_driven -timing_driven -force_center_initial_place -min_phi_coef 0.95 -max_phi_coef 1.05 estimate_parasitics -placement Report metrics stage 3, global place... ========================================================================== global place report_design_area -------------------------------------------------------------------------- Design area 699 um^2 78% utilization. write_db ./results/nangate45/gcd/n45_u70/3_3_place_gp.odb Elapsed time: 5:04.54[h:]min:sec. CPU time: user 1154.30 sys 1.01 (379%). Peak memory: 289484KB. Log Ext Elapsed/s Peak Memory/MB sha1sum result [0:20) 3_3_place_gp .odb 304 282 0f92f88eb2a811a25adf /OpenROAD-flow-scripts/flow/scripts/flow.sh 3_4_place_resized resize Running resize.tcl, stage 3_4_place_resized read_liberty /OpenROAD-flow-scripts/flow/platforms/nangate45/lib/NangateOpenCellLibrary_typical.lib read_db ./results/nangate45/gcd/n45_u70/3_3_place_gp.odb read_sdc ./results/nangate45/gcd/n45_u70/2_floorplan.sdc source /OpenROAD-flow-scripts/flow/platforms/nangate45/setRC.tcl estimate_parasitics -placement Perform buffer insertion and gate resizing... repair_design -verbose Iteration | Area | Resized | Buffers | Nets repaired | Remaining --------------------------------------------------------------------- 0 | +0.0% | 0 | 0 | 0 | 641 10 | +0.0% | 0 | 0 | 0 | 631 20 | +0.0% | 0 | 0 | 0 | 621 30 | +0.0% | 0 | 0 | 0 | 611 40 | +0.0% | 0 | 0 | 0 | 601 50 | +0.0% | 0 | 0 | 0 | 591 60 | +0.0% | 0 | 0 | 0 | 581 70 | +0.0% | 0 | 0 | 0 | 571 80 | +0.0% | 0 | 0 | 0 | 561 90 | +0.0% | 0 | 0 | 0 | 551 100 | +0.0% | 0 | 0 | 0 | 541 110 | +0.0% | 0 | 0 | 0 | 531 120 | +0.0% | 0 | 0 | 0 | 521 130 | +0.0% | 0 | 0 | 0 | 511 140 | +0.0% | 0 | 0 | 0 | 501 150 | +0.0% | 0 | 0 | 0 | 491 160 | +0.0% | 0 | 0 | 0 | 481 170 | +0.0% | 0 | 0 | 0 | 471 180 | +0.0% | 0 | 0 | 0 | 461 190 | +0.0% | 0 | 0 | 0 | 451 200 | +0.0% | 0 | 0 | 0 | 441 210 | +0.0% | 0 | 0 | 0 | 431 220 | +0.0% | 0 | 0 | 0 | 421 230 | +0.0% | 0 | 0 | 0 | 411 240 | +0.0% | 0 | 0 | 0 | 401 250 | +0.0% | 0 | 0 | 0 | 391 260 | +0.0% | 0 | 0 | 0 | 381 270 | +0.0% | 0 | 0 | 0 | 371 280 | +0.0% | 0 | 0 | 0 | 361 290 | +0.0% | 0 | 0 | 0 | 351 300 | +0.0% | 0 | 0 | 0 | 341 310 | +0.0% | 0 | 0 | 0 | 331 320 | +0.0% | 0 | 0 | 0 | 321 330 | +0.0% | 0 | 0 | 0 | 311 340 | +0.0% | 0 | 0 | 0 | 301 350 | +0.0% | 0 | 0 | 0 | 291 360 | +0.0% | 0 | 0 | 0 | 281 370 | +0.0% | 0 | 0 | 0 | 271 380 | +0.0% | 0 | 0 | 0 | 261 390 | +0.0% | 0 | 0 | 0 | 251 400 | +0.0% | 0 | 0 | 0 | 241 410 | +0.0% | 0 | 0 | 0 | 231 420 | +0.0% | 0 | 0 | 0 | 221 430 | +0.0% | 0 | 0 | 0 | 211 440 | +0.0% | 0 | 0 | 0 | 201 450 | +0.0% | 0 | 0 | 0 | 191 460 | +0.0% | 0 | 0 | 0 | 181 470 | +0.0% | 0 | 0 | 0 | 171 480 | +0.0% | 0 | 0 | 0 | 161 490 | +0.0% | 0 | 0 | 0 | 151 500 | +0.0% | 0 | 0 | 0 | 141 510 | +0.0% | 0 | 0 | 0 | 131 520 | +0.0% | 0 | 0 | 0 | 121 530 | +0.0% | 0 | 0 | 0 | 111 540 | +0.0% | 0 | 0 | 0 | 101 550 | +0.0% | 0 | 0 | 0 | 91 560 | +0.0% | 0 | 0 | 0 | 81 570 | +0.0% | 0 | 0 | 0 | 71 580 | +0.0% | 0 | 0 | 0 | 61 590 | +0.0% | 0 | 0 | 0 | 51 600 | +0.0% | 0 | 0 | 0 | 41 610 | +0.0% | 0 | 0 | 0 | 31 620 | +0.0% | 0 | 0 | 0 | 21 630 | +0.0% | 0 | 0 | 0 | 11 640 | +0.0% | 0 | 0 | 0 | 1 final | +0.0% | 0 | 0 | 0 | 0 --------------------------------------------------------------------- [INFO RSZ-0504] Runtime: 0.09s Floating nets: Report metrics stage 3, resizer... ========================================================================== resizer report_design_area -------------------------------------------------------------------------- Design area 699 um^2 78% utilization. Instance count before 612, after 612 Pin count before 1742, after 1742 write_db ./results/nangate45/gcd/n45_u70/3_4_place_resized.odb Elapsed time: 0:00.65[h:]min:sec. CPU time: user 0.37 sys 0.07 (67%). Peak memory: 132752KB. Log Ext Elapsed/s Peak Memory/MB sha1sum result [0:20) 3_4_place_resized .odb 0 129 0f92f88eb2a811a25adf /OpenROAD-flow-scripts/flow/scripts/flow.sh 3_5_place_dp detail_place Running detail_place.tcl, stage 3_5_place_dp read_liberty /OpenROAD-flow-scripts/flow/platforms/nangate45/lib/NangateOpenCellLibrary_typical.lib read_db ./results/nangate45/gcd/n45_u70/3_4_place_resized.odb read_sdc ./results/nangate45/gcd/n45_u70/2_floorplan.sdc source /OpenROAD-flow-scripts/flow/platforms/nangate45/setRC.tcl detailed_placement [INFO DPL-0006] Core area: 899.35 um^2, Instances area: 699.05 um^2, Utilization: 77.7% [INFO DPL-0005] Diamond search max displacement: +/- 500 sites horizontally, +/- 100 rows vertically. [INFO DPL-1101] Legalizing using diamond search. Movements Summary --------------------------------------- Total cells: 570 Diamond Move Success: 570 (100.00%) Diamond Move Failure: 0 Rip-up and replace Success: 0 ( 0.00% of diamond failures) Rip-up and replace Failure: 0 Total Placement Failures: 0 --------------------------------------- [INFO DPL-0500] Runtime: 0.00s Placement Analysis --------------------------------- total displacement 612.4 u average displacement 1.0 u max displacement 3.1 u original HPWL 2546.4 u legalized HPWL 3094.6 u delta HPWL 22 % improve_placement -max_displacement "5 1" Detailed placement improvement. [INFO DPL-0401] Setting random seed to 1. [INFO DPL-0402] Setting maximum displacement 5 1 to 14000 2800 units. [INFO DPL-0320] Collected 96 fixed cells. [INFO DPL-0318] Collected 570 single height cells. [INFO DPL-0321] Collected 0 wide cells. [INFO DPL-0322] Image (2280, 2800) - (63460, 61600) [INFO DPL-0310] Assigned 570 cells into segments. Movement in X-direction is 0.000000, movement in Y-direction is 0.000000. [INFO DPL-0313] Found 0 cells in wrong regions. [INFO DPL-0315] Found 0 row alignment problems. [INFO DPL-0314] Found 0 site alignment problems. [INFO DPL-0311] Found 0 overlaps between adjacent cells. [INFO DPL-0312] Found 0 edge spacing violations and 0 padding violations. [INFO DPL-0303] Running algorithm for independent set matching. [INFO DPL-0300] Set matching objective is wirelength. [INFO DPL-0301] Pass 1 of matching; objective is 6.176065e+06. [INFO DPL-0302] End of matching; objective is 6.126280e+06, improvement is 0.81 percent. [INFO DPL-0303] Running algorithm for global swaps. [INFO DPL-0306] Pass 1 of global swaps; hpwl is 5.985345e+06. [INFO DPL-0306] Pass 2 of global swaps; hpwl is 5.946440e+06. [INFO DPL-0307] End of global swaps; objective is 5.946440e+06, improvement is 2.94 percent. [INFO DPL-0303] Running algorithm for vertical swaps. [INFO DPL-0308] Pass 1 of vertical swaps; hpwl is 5.913425e+06. [INFO DPL-0309] End of vertical swaps; objective is 5.913425e+06, improvement is 0.56 percent. [INFO DPL-0303] Running algorithm for reordering. [INFO DPL-0304] Pass 1 of reordering; objective is 5.802760e+06. [INFO DPL-0304] Pass 2 of reordering; objective is 5.783420e+06. [INFO DPL-0305] End of reordering; objective is 5.783420e+06, improvement is 2.20 percent. [INFO DPL-0303] Running algorithm for random improvement. [INFO DPL-0324] Random improver is using random generator. [INFO DPL-0325] Random improver is using hpwl objective. [INFO DPL-0326] Random improver cost string is (a). [INFO DPL-0332] End of pass, Generator random called 11400 times. [INFO DPL-0335] Generator random, Cumulative attempts 11400, swaps 3106, moves 1902 since last reset. [INFO DPL-0333] End of pass, Objective hpwl, Initial cost 5.783420e+06, Scratch cost 5.701340e+06, Incremental cost 5.701340e+06, Mismatch? N [INFO DPL-0338] End of pass, Total cost is 5.701340e+06. [INFO DPL-0327] Pass 1 of random improver; improvement in cost is 1.42 percent. [INFO DPL-0332] End of pass, Generator random called 11400 times. [INFO DPL-0335] Generator random, Cumulative attempts 22800, swaps 6093, moves 3890 since last reset. [INFO DPL-0333] End of pass, Objective hpwl, Initial cost 5.701340e+06, Scratch cost 5.675880e+06, Incremental cost 5.675880e+06, Mismatch? N [INFO DPL-0338] End of pass, Total cost is 5.675880e+06. [INFO DPL-0327] Pass 2 of random improver; improvement in cost is 0.45 percent. [INFO DPL-0328] End of random improver; improvement is 1.859453 percent. [INFO DPL-0380] Cell flipping. [INFO DPL-0382] Changed 0 cell orientations for row compatibility. [INFO DPL-0383] Performed 178 cell flips. [INFO DPL-0384] End of flipping; objective is 5.569910e+06, improvement is 1.87 percent. [INFO DPL-0313] Found 0 cells in wrong regions. [INFO DPL-0315] Found 0 row alignment problems. [INFO DPL-0314] Found 0 site alignment problems. [INFO DPL-0311] Found 0 overlaps between adjacent cells. [INFO DPL-0312] Found 0 edge spacing violations and 0 padding violations. Detailed Improvement Results ------------------------------------------ Original HPWL 3094.6 u ( 1700.5, 1394.1) Final HPWL 2791.9 u ( 1479.9, 1311.9) Delta HPWL -9.8 % ( -13.0, -5.9) optimize_mirroring [INFO DPL-0020] Mirrored 33 instances [INFO DPL-0021] HPWL before 2791.9 u [INFO DPL-0022] HPWL after 2790.2 u [INFO DPL-0023] HPWL delta -0.1 % [INFO FLW-0012] Placement violations . estimate_parasitics -placement Report metrics stage 3, detailed place... ========================================================================== detailed place report_design_area -------------------------------------------------------------------------- Design area 699 um^2 78% utilization. write_db ./results/nangate45/gcd/n45_u70/3_5_place_dp.odb Elapsed time: 0:00.69[h:]min:sec. CPU time: user 0.44 sys 0.05 (71%). Peak memory: 121008KB. Log Ext Elapsed/s Peak Memory/MB sha1sum result [0:20) 3_5_place_dp .odb 0 118 4443fd703efc1d4a11c2 cp ./results/nangate45/gcd/n45_u70/3_5_place_dp.odb ./results/nangate45/gcd/n45_u70/3_place.odb cp ./results/nangate45/gcd/n45_u70/2_floorplan.sdc ./results/nangate45/gcd/n45_u70/3_place.sdc /OpenROAD-flow-scripts/flow/scripts/flow.sh 4_1_cts cts Running cts.tcl, stage 4_1_cts read_liberty /OpenROAD-flow-scripts/flow/platforms/nangate45/lib/NangateOpenCellLibrary_typical.lib read_db ./results/nangate45/gcd/n45_u70/3_place.odb read_sdc ./results/nangate45/gcd/n45_u70/3_place.sdc source /OpenROAD-flow-scripts/flow/platforms/nangate45/setRC.tcl clock_tree_synthesis -sink_clustering_enable -repair_clock_nets [INFO CTS-0050] Root buffer is CLKBUF_X3. [INFO CTS-0051] Sink buffer is CLKBUF_X3. [INFO CTS-0052] The following clock buffers will be used for CTS: CLKBUF_X3 [INFO CTS-0049] Characterization buffer is CLKBUF_X3. [INFO CTS-0007] Net "clk" found for clock "core_clock". [INFO CTS-0010] Clock net "clk" has 35 sinks. [INFO CTS-0008] TritonCTS found 1 clock nets. [INFO CTS-0097] Characterization used 1 buffer(s) types. [INFO CTS-0201] 0 blockages from hard placement blockages and placed macros will be used. [INFO CTS-0027] Generating H-Tree topology for net clk. [INFO CTS-0028] Total number of sinks: 35. [INFO CTS-0090] Sinks will be clustered based on buffer max cap. [INFO CTS-0030] Number of static layers: 0. [INFO CTS-0020] Wire segment unit: 14000 dbu (7 um). [INFO CTS-0023] Original sink region: [(6650, 4030), (59090, 60030)]. [INFO CTS-0024] Normalized sink region: [(0.475, 0.287857), (4.22071, 4.28786)]. [INFO CTS-0025] Width: 3.7457. [INFO CTS-0026] Height: 4.0000. Level 1 Direction: Vertical Sinks per sub-region: 18 Sub-region size: 3.7457 X 2.0000 [INFO CTS-0034] Segment length (rounded): 1. Level 2 Direction: Horizontal Sinks per sub-region: 9 Sub-region size: 1.8729 X 2.0000 [INFO CTS-0034] Segment length (rounded): 1. [INFO CTS-0032] Stop criterion found. Max number of sinks is 15. [INFO CTS-0035] Number of sinks covered: 35. [INFO CTS-0018] Created 5 clock buffers. [INFO CTS-0012] Minimum number of buffers in the clock path: 2. [INFO CTS-0013] Maximum number of buffers in the clock path: 2. [INFO CTS-0015] Created 5 clock nets. [INFO CTS-0016] Fanout distribution for the current clock = 7:1, 8:1, 9:1, 11:1.. [INFO CTS-0017] Max level of the clock tree: 2. [INFO CTS-0098] Clock net "clk" [INFO CTS-0099] Sinks 38 [INFO CTS-0100] Leaf buffers 0 [INFO CTS-0101] Average sink wire length 49.02 um [INFO CTS-0102] Path depth 2 - 2 [INFO CTS-0207] Dummy loads inserted 3 [INFO CTS-0500] Runtime: 0.67s estimate_parasitics -placement detailed_placement [INFO DPL-0006] Core area: 899.35 um^2, Instances area: 707.83 um^2, Utilization: 78.7% [INFO DPL-0005] Diamond search max displacement: +/- 500 sites horizontally, +/- 100 rows vertically. [INFO DPL-1101] Legalizing using diamond search. Movements Summary --------------------------------------- Total cells: 578 Diamond Move Success: 578 (100.00%) Diamond Move Failure: 0 Rip-up and replace Success: 0 ( 0.00% of diamond failures) Rip-up and replace Failure: 0 Total Placement Failures: 0 --------------------------------------- [INFO DPL-0500] Runtime: 0.00s Placement Analysis --------------------------------- total displacement 63.9 u average displacement 0.1 u max displacement 4.2 u original HPWL 2879.8 u legalized HPWL 3002.0 u delta HPWL 4 % estimate_parasitics -placement repair_timing -setup_margin 0 -hold_margin 0 -repair_tns 100 -verbose [INFO RSZ-0100] Repair move sequence: UnbufferMove SizeUpMove SwapPinsMove BufferMove CloneMove SplitLoadMove [INFO RSZ-0098] No setup violations found [INFO RSZ-0505] Runtime: 0.03s [INFO RSZ-0033] No hold violations found. [INFO RSZ-0506] Runtime: 0.01s Repair timing output passed lec test detailed_placement [INFO DPL-0006] Core area: 899.35 um^2, Instances area: 707.83 um^2, Utilization: 78.7% [INFO DPL-0005] Diamond search max displacement: +/- 500 sites horizontally, +/- 100 rows vertically. [INFO DPL-1101] Legalizing using diamond search. Movements Summary --------------------------------------- Total cells: 578 Diamond Move Success: 578 (100.00%) Diamond Move Failure: 0 Rip-up and replace Success: 0 ( 0.00% of diamond failures) Rip-up and replace Failure: 0 Total Placement Failures: 0 --------------------------------------- [INFO DPL-0500] Runtime: 0.00s Placement Analysis --------------------------------- total displacement 0.0 u average displacement 0.0 u max displacement 0.0 u original HPWL 3002.0 u legalized HPWL 3002.0 u delta HPWL 0 % Report metrics stage 4, cts final... ========================================================================== cts final report_design_area -------------------------------------------------------------------------- Design area 708 um^2 79% utilization. write_db ./results/nangate45/gcd/n45_u70/4_1_cts.odb write_sdc -no_timestamp ./results/nangate45/gcd/n45_u70/4_cts.sdc Elapsed time: 0:01.41[h:]min:sec. CPU time: user 1.13 sys 0.10 (86%). Peak memory: 146528KB. Log Ext Elapsed/s Peak Memory/MB sha1sum result [0:20) 4_1_cts .odb 1 143 978b27124ac6d38f39b1 cp ./results/nangate45/gcd/n45_u70/4_1_cts.odb ./results/nangate45/gcd/n45_u70/4_cts.odb /OpenROAD-flow-scripts/flow/scripts/flow.sh 5_1_grt global_route Running global_route.tcl, stage 5_1_grt read_liberty /OpenROAD-flow-scripts/flow/platforms/nangate45/lib/NangateOpenCellLibrary_typical.lib read_db ./results/nangate45/gcd/n45_u70/4_cts.odb read_sdc ./results/nangate45/gcd/n45_u70/4_cts.sdc source /OpenROAD-flow-scripts/flow/platforms/nangate45/setRC.tcl pin_access [INFO DRT-0149] Reading tech and libs. Units: 2000 Number of layers: 21 Number of macros: 135 Number of vias: 33 Number of viarulegen: 19 [INFO DRT-0150] Reading design. Design: gcd Die area: ( 0 0 ) ( 65560 65560 ) Number of track patterns: 20 Number of DEF vias: 0 Number of components: 620 Number of terminals: 54 Number of snets: 2 Number of nets: 646 [INFO DRT-0167] List of default vias: Layer via2 default via: via2_5 Layer via3 default via: via3_2 Layer via4 default via: via4_0 Layer via5 default via: via5_0 Layer via6 default via: via6_0 Layer via7 default via: via7_0 Layer via8 default via: via8_0 Layer via9 default via: via9_0 [INFO DRT-0162] Library cell analysis. [INFO DRT-0163] Instance analysis. [INFO DRT-0164] Number of unique instances = 59. [INFO DRT-0168] Init region query. [INFO DRT-0024] Complete active. [INFO DRT-0024] Complete Fr_VIA. [INFO DRT-0024] Complete metal1. [INFO DRT-0024] Complete via1. [INFO DRT-0024] Complete metal2. [INFO DRT-0024] Complete via2. [INFO DRT-0024] Complete metal3. [INFO DRT-0024] Complete via3. [INFO DRT-0024] Complete metal4. [INFO DRT-0024] Complete via4. [INFO DRT-0024] Complete metal5. [INFO DRT-0024] Complete via5. [INFO DRT-0024] Complete metal6. [INFO DRT-0024] Complete via6. [INFO DRT-0024] Complete metal7. [INFO DRT-0024] Complete via7. [INFO DRT-0024] Complete metal8. [INFO DRT-0024] Complete via8. [INFO DRT-0024] Complete metal9. [INFO DRT-0024] Complete via9. [INFO DRT-0024] Complete metal10. [INFO DRT-0033] active shape region query size = 0. [INFO DRT-0033] FR_VIA shape region query size = 0. [INFO DRT-0033] metal1 shape region query size = 8218. [INFO DRT-0033] via1 shape region query size = 99. [INFO DRT-0033] metal2 shape region query size = 66. [INFO DRT-0033] via2 shape region query size = 99. [INFO DRT-0033] metal3 shape region query size = 66. [INFO DRT-0033] via3 shape region query size = 99. [INFO DRT-0033] metal4 shape region query size = 40. [INFO DRT-0033] via4 shape region query size = 40. [INFO DRT-0033] metal5 shape region query size = 33. [INFO DRT-0033] via5 shape region query size = 40. [INFO DRT-0033] metal6 shape region query size = 37. [INFO DRT-0033] via6 shape region query size = 16. [INFO DRT-0033] metal7 shape region query size = 6. [INFO DRT-0033] via7 shape region query size = 0. [INFO DRT-0033] metal8 shape region query size = 0. [INFO DRT-0033] via8 shape region query size = 0. [INFO DRT-0033] metal9 shape region query size = 0. [INFO DRT-0033] via9 shape region query size = 0. [INFO DRT-0033] metal10 shape region query size = 0. [INFO DRT-0165] Start pin access. [INFO DRT-0078] Complete 296 pins. [INFO DRT-0081] Complete 59 unique inst patterns. [INFO DRT-0084] Complete 217 groups. #scanned instances = 620 #unique instances = 59 #stdCellGenAp = 1403 #stdCellValidPlanarAp = 0 #stdCellValidViaAp = 1022 #stdCellPinNoAp = 0 #stdCellPinCnt = 1755 #instTermValidViaApCnt = 0 #macroGenAp = 0 #macroValidPlanarAp = 0 #macroValidViaAp = 0 #macroNoAp = 0 [INFO DRT-0166] Complete pin access. [INFO DRT-0267] cpu time = 00:00:07, elapsed time = 00:00:02, memory = 117.60 (MB), peak = 114.20 (MB) global_route -congestion_report_file ./reports/nangate45/gcd/n45_u70/congestion.rpt -congestion_iterations 30 -congestion_report_iter_step 5 -verbose [INFO GRT-0020] Min routing layer: metal2 [INFO GRT-0021] Max routing layer: metal10 [INFO GRT-0022] Global adjustment: 0% [INFO GRT-0023] Grid origin: (0, 0) [INFO GRT-0088] Layer metal1 Track-Pitch = 0.1400 line-2-Via Pitch: 0.1350 [INFO GRT-0088] Layer metal2 Track-Pitch = 0.1900 line-2-Via Pitch: 0.1400 [INFO GRT-0088] Layer metal3 Track-Pitch = 0.1400 line-2-Via Pitch: 0.1400 [INFO GRT-0088] Layer metal4 Track-Pitch = 0.2800 line-2-Via Pitch: 0.2800 [INFO GRT-0088] Layer metal5 Track-Pitch = 0.2800 line-2-Via Pitch: 0.2800 [INFO GRT-0088] Layer metal6 Track-Pitch = 0.2800 line-2-Via Pitch: 0.2800 [INFO GRT-0088] Layer metal7 Track-Pitch = 0.8000 line-2-Via Pitch: 0.8000 [INFO GRT-0088] Layer metal8 Track-Pitch = 0.8000 line-2-Via Pitch: 0.8000 [INFO GRT-0088] Layer metal9 Track-Pitch = 1.6000 line-2-Via Pitch: 1.6000 [INFO GRT-0088] Layer metal10 Track-Pitch = 1.6000 line-2-Via Pitch: 1.6000 [INFO GRT-0003] Macros: 0 [INFO GRT-0004] Blockages: 0 [INFO GRT-0019] Found 6 clock nets. [INFO GRT-0001] Minimum degree: 2 [INFO GRT-0002] Maximum degree: 27 [INFO GRT-0053] Routing resources analysis: Routing Original Derated Resource Layer Direction Resources Resources Reduction (%) --------------------------------------------------------------- metal1 Horizontal 0 0 0.00% metal2 Vertical 1630 770 52.76% metal3 Horizontal 2317 1135 51.01% metal4 Vertical 1110 770 30.63% metal5 Horizontal 1159 821 29.16% metal6 Vertical 1160 820 29.31% metal7 Horizontal 355 244 31.27% metal8 Vertical 400 280 30.00% metal9 Horizontal 200 120 40.00% metal10 Vertical 200 120 40.00% --------------------------------------------------------------- [INFO GRT-0197] Via related to pin nodes: 2708 [INFO GRT-0198] Via related Steiner nodes: 26 [INFO GRT-0199] Via filling finished. [INFO GRT-0111] Final number of vias: 3270 [INFO GRT-0112] Final usage 3D: 11048 [INFO GRT-0096] Final congestion report: Layer Resource Demand Usage (%) Max H / Max V / Total Congestion --------------------------------------------------------------------------------------- metal1 0 0 0.00% 0 / 0 / 0 metal2 770 470 61.04% 0 / 0 / 0 metal3 1135 589 51.89% 0 / 0 / 0 metal4 770 119 15.45% 0 / 0 / 0 metal5 821 48 5.85% 0 / 0 / 0 metal6 820 12 1.46% 0 / 0 / 0 metal7 244 0 0.00% 0 / 0 / 0 metal8 280 0 0.00% 0 / 0 / 0 metal9 120 0 0.00% 0 / 0 / 0 metal10 120 0 0.00% 0 / 0 / 0 --------------------------------------------------------------------------------------- Total 5080 1238 24.37% 0 / 0 / 0 [INFO GRT-0018] Total wirelength: 6056 um [INFO GRT-0014] Routed nets: 627 [INFO GRT-0303] Global routing runtime = 00:00:00 [WARNING STA-0450] virtual clock vclk_core_clock can not be propagated. estimate_parasitics -global_routing Perform buffer insertion and gate resizing... repair_design -verbose Iteration | Area | Resized | Buffers | Nets repaired | Remaining --------------------------------------------------------------------- 0 | +0.0% | 0 | 0 | 0 | 649 10 | +0.0% | 0 | 0 | 0 | 639 20 | +0.0% | 0 | 0 | 0 | 629 30 | +0.0% | 0 | 0 | 0 | 619 40 | +0.0% | 0 | 0 | 0 | 609 50 | +0.0% | 0 | 0 | 0 | 599 60 | +0.0% | 0 | 0 | 0 | 589 70 | +0.0% | 0 | 0 | 0 | 579 80 | +0.0% | 0 | 0 | 0 | 569 90 | +0.0% | 0 | 0 | 0 | 559 100 | +0.0% | 0 | 0 | 0 | 549 110 | +0.0% | 0 | 0 | 0 | 539 120 | +0.0% | 0 | 0 | 0 | 529 130 | +0.0% | 0 | 0 | 0 | 519 140 | +0.0% | 0 | 0 | 0 | 509 150 | +0.0% | 0 | 0 | 0 | 499 160 | +0.0% | 0 | 0 | 0 | 489 170 | +0.0% | 0 | 0 | 0 | 479 180 | +0.0% | 0 | 0 | 0 | 469 190 | +0.0% | 0 | 0 | 0 | 459 200 | +0.0% | 0 | 0 | 0 | 449 210 | +0.0% | 0 | 0 | 0 | 439 220 | +0.0% | 0 | 0 | 0 | 429 230 | +0.0% | 0 | 0 | 0 | 419 240 | +0.0% | 0 | 0 | 0 | 409 250 | +0.0% | 0 | 0 | 0 | 399 260 | +0.0% | 0 | 0 | 0 | 389 270 | +0.0% | 0 | 0 | 0 | 379 280 | +0.0% | 0 | 0 | 0 | 369 290 | +0.0% | 0 | 0 | 0 | 359 300 | +0.0% | 0 | 0 | 0 | 349 310 | +0.0% | 0 | 0 | 0 | 339 320 | +0.0% | 0 | 0 | 0 | 329 330 | +0.0% | 0 | 0 | 0 | 319 340 | +0.0% | 0 | 0 | 0 | 309 350 | +0.0% | 0 | 0 | 0 | 299 360 | +0.0% | 0 | 0 | 0 | 289 370 | +0.0% | 0 | 0 | 0 | 279 380 | +0.0% | 0 | 0 | 0 | 269 390 | +0.0% | 0 | 0 | 0 | 259 400 | +0.0% | 0 | 0 | 0 | 249 410 | +0.0% | 0 | 0 | 0 | 239 420 | +0.0% | 0 | 0 | 0 | 229 430 | +0.0% | 0 | 0 | 0 | 219 440 | +0.0% | 0 | 0 | 0 | 209 450 | +0.0% | 0 | 0 | 0 | 199 460 | +0.0% | 0 | 0 | 0 | 189 470 | +0.0% | 0 | 0 | 0 | 179 480 | +0.0% | 0 | 0 | 0 | 169 490 | +0.0% | 0 | 0 | 0 | 159 500 | +0.0% | 0 | 0 | 0 | 149 510 | +0.0% | 0 | 0 | 0 | 139 520 | +0.0% | 0 | 0 | 0 | 129 530 | +0.0% | 0 | 0 | 0 | 119 [WARNING RSZ-0104] Net _495_ only has one pin. Check if it is intended to be dangling. [WARNING RSZ-0104] Net _494_ only has one pin. Check if it is intended to be dangling. [WARNING RSZ-0104] Net _493_ only has one pin. Check if it is intended to be dangling. [WARNING RSZ-0104] Net _492_ only has one pin. Check if it is intended to be dangling. 540 | +0.0% | 0 | 0 | 0 | 109 [WARNING RSZ-0104] Net _491_ only has one pin. Check if it is intended to be dangling. [WARNING RSZ-0104] Net _490_ only has one pin. Check if it is intended to be dangling. [WARNING RSZ-0104] Net _489_ only has one pin. Check if it is intended to be dangling. [WARNING RSZ-0104] Net _488_ only has one pin. Check if it is intended to be dangling. [WARNING RSZ-0104] Net _487_ only has one pin. Check if it is intended to be dangling. 550 | +0.0% | 0 | 0 | 0 | 99 [WARNING RSZ-0104] Net _485_ only has one pin. Check if it is intended to be dangling. [WARNING RSZ-0104] Net _500_ only has one pin. Check if it is intended to be dangling. [WARNING RSZ-0104] Net _499_ only has one pin. Check if it is intended to be dangling. [WARNING RSZ-0104] Net _498_ only has one pin. Check if it is intended to be dangling. [WARNING RSZ-0104] Net _497_ only has one pin. Check if it is intended to be dangling. 560 | +0.0% | 0 | 0 | 0 | 89 [WARNING RSZ-0104] Net _496_ only has one pin. Check if it is intended to be dangling. [WARNING RSZ-0104] Net _503_ only has one pin. Check if it is intended to be dangling. [WARNING RSZ-0104] Net _486_ only has one pin. Check if it is intended to be dangling. [WARNING RSZ-0104] Net _502_ only has one pin. Check if it is intended to be dangling. [WARNING RSZ-0104] Net _501_ only has one pin. Check if it is intended to be dangling. 570 | +0.0% | 0 | 0 | 0 | 79 580 | +0.0% | 0 | 0 | 0 | 69 590 | +0.0% | 0 | 0 | 0 | 59 600 | +0.0% | 0 | 0 | 0 | 49 610 | +0.0% | 0 | 0 | 0 | 39 620 | +0.0% | 0 | 0 | 0 | 29 630 | +0.0% | 0 | 0 | 0 | 19 640 | +0.0% | 0 | 0 | 0 | 9 final | +0.0% | 0 | 0 | 0 | 0 --------------------------------------------------------------------- [INFO RSZ-0504] Runtime: 3.41s global_route -start_incremental detailed_placement [INFO DPL-0006] Core area: 899.35 um^2, Instances area: 707.83 um^2, Utilization: 78.7% [INFO DPL-0005] Diamond search max displacement: +/- 500 sites horizontally, +/- 100 rows vertically. [INFO DPL-1101] Legalizing using diamond search. Movements Summary --------------------------------------- Total cells: 578 Diamond Move Success: 578 (100.00%) Diamond Move Failure: 0 Rip-up and replace Success: 0 ( 0.00% of diamond failures) Rip-up and replace Failure: 0 Total Placement Failures: 0 --------------------------------------- [INFO DPL-0500] Runtime: 0.00s Placement Analysis --------------------------------- total displacement 0.0 u average displacement 0.0 u max displacement 0.0 u original HPWL 3002.0 u legalized HPWL 3002.0 u delta HPWL 0 % global_route -end_incremental -congestion_report_file ./reports/nangate45/gcd/n45_u70/congestion_post_repair_design.rpt Repair setup and hold violations... estimate_parasitics -global_routing repair_timing -setup_margin 0 -hold_margin 0 -repair_tns 100 -verbose [INFO RSZ-0100] Repair move sequence: UnbufferMove SizeUpMove SwapPinsMove BufferMove CloneMove SplitLoadMove [INFO RSZ-0094] Found 2 endpoints with setup violations. [INFO RSZ-0099] Repairing 2 out of 2 (100.00%) violating endpoints... Iter | Removed | Resized | Inserted | Cloned | Pin | Area | WNS | StTNS | EnTNS | Viol | Worst | Buffers | Gates | Buffers | Gates | Swaps | | | | | Endpts | St/EnPt ------------------------------------------------------------------------------------------------------------------------------ 0* | 0 | 0 | 0 | 0 | 0 | +0.0% | -0.009 | -0.0 | -0.0 | 2 | resp_msg[14] 2* | 0 | 1 | 0 | 0 | 0 | +0.1% | -0.003 | -0.0 | -0.0 | 2 | resp_msg[13] 5* | 0 | 3 | 0 | 0 | 0 | +0.2% | 0.002 | 0.0 | 0.0 | 2 | resp_msg[13] 5* | 0 | 3 | 0 | 0 | 0 | +0.2% | 0.002 | 0.0 | 0.0 | 2 | resp_msg[13] final | 0 | 3 | 0 | 0 | 0 | +0.2% | 0.002 | 0.0 | 0.0 | 0 | resp_msg[13] ------------------------------------------------------------------------------------------------------------------------------ [INFO RSZ-0051] Resized 3 instances: 3 up, 0 up match, 0 down, 0 VT [INFO RSZ-0505] Runtime: 1.45s [INFO RSZ-0033] No hold violations found. [INFO RSZ-0506] Runtime: 0.17s global_route -start_incremental detailed_placement [INFO DPL-0006] Core area: 899.35 um^2, Instances area: 709.42 um^2, Utilization: 78.9% [INFO DPL-0005] Diamond search max displacement: +/- 500 sites horizontally, +/- 100 rows vertically. [INFO DPL-1101] Legalizing using diamond search. Movements Summary --------------------------------------- Total cells: 578 Diamond Move Success: 578 (100.00%) Diamond Move Failure: 0 Rip-up and replace Success: 0 ( 0.00% of diamond failures) Rip-up and replace Failure: 0 Total Placement Failures: 0 --------------------------------------- [INFO DPL-0500] Runtime: 0.01s Placement Analysis --------------------------------- total displacement 5.7 u average displacement 0.0 u max displacement 1.8 u original HPWL 3002.9 u legalized HPWL 3010.2 u delta HPWL 0 % check_placement -verbose global_route -end_incremental -congestion_report_file ./reports/nangate45/gcd/n45_u70/congestion_post_repair_timing.rpt estimate_parasitics -global_routing global_route -start_incremental global_route -end_incremental -congestion_report_file ./reports/nangate45/gcd/n45_u70/congestion_post_recover_power.rpt Repair antennas... [WARNING GRT-0246] No diode with LEF class CORE ANTENNACELL found. [INFO ANT-0002] Found 0 net violations. [INFO ANT-0001] Found 0 pin violations. Estimate parasitics... estimate_parasitics -global_routing Report metrics stage 5, global route... ========================================================================== global route report_design_area -------------------------------------------------------------------------- Design area 709 um^2 79% utilization. [INFO FLW-0007] clock core_clock period 0.460000 [WARNING FLW-0010] more than one clock found. Skipping sdc update. [INFO FLW-0011] Path endpoint path count 75 write_db ./results/nangate45/gcd/n45_u70/5_1_grt.odb write_sdc -no_timestamp ./results/nangate45/gcd/n45_u70/5_1_grt.sdc Elapsed time: 0:09.72[h:]min:sec. CPU time: user 27.65 sys 0.15 (286%). Peak memory: 294448KB. Log Ext Elapsed/s Peak Memory/MB sha1sum result [0:20) 5_1_grt .odb 9 287 f4d77edd6f6a4bb9d9be 5_1_grt .sdc 6dc41493824210708c18 /OpenROAD-flow-scripts/flow/scripts/flow.sh 5_2_route detail_route Running detail_route.tcl, stage 5_2_route read_liberty /OpenROAD-flow-scripts/flow/platforms/nangate45/lib/NangateOpenCellLibrary_typical.lib read_db ./results/nangate45/gcd/n45_u70/5_1_grt.odb read_sdc ./results/nangate45/gcd/n45_u70/5_1_grt.sdc source /OpenROAD-flow-scripts/flow/platforms/nangate45/setRC.tcl [WARNING STA-0450] virtual clock vclk_core_clock can not be propagated. detailed_route -output_drc ./reports/nangate45/gcd/n45_u70/5_route_drc.rpt -output_maze ./results/nangate45/gcd/n45_u70/maze.log -droute_end_iter 64 -verbose 1 -drc_report_iter_step 5 [INFO DRT-0149] Reading tech and libs. Units: 2000 Number of layers: 21 Number of macros: 135 Number of vias: 33 Number of viarulegen: 19 [INFO DRT-0150] Reading design. Design: gcd Die area: ( 0 0 ) ( 65560 65560 ) Number of track patterns: 20 Number of DEF vias: 0 Number of components: 620 Number of terminals: 54 Number of snets: 2 Number of nets: 646 [INFO DRT-0167] List of default vias: Layer via2 default via: via2_5 Layer via3 default via: via3_2 Layer via4 default via: via4_0 Layer via5 default via: via5_0 Layer via6 default via: via6_0 Layer via7 default via: via7_0 Layer via8 default via: via8_0 Layer via9 default via: via9_0 [INFO DRT-0162] Library cell analysis. [INFO DRT-0163] Instance analysis. [INFO DRT-0164] Number of unique instances = 59. [INFO DRT-0168] Init region query. [INFO DRT-0024] Complete active. [INFO DRT-0024] Complete Fr_VIA. [INFO DRT-0024] Complete metal1. [INFO DRT-0024] Complete via1. [INFO DRT-0024] Complete metal2. [INFO DRT-0024] Complete via2. [INFO DRT-0024] Complete metal3. [INFO DRT-0024] Complete via3. [INFO DRT-0024] Complete metal4. [INFO DRT-0024] Complete via4. [INFO DRT-0024] Complete metal5. [INFO DRT-0024] Complete via5. [INFO DRT-0024] Complete metal6. [INFO DRT-0024] Complete via6. [INFO DRT-0024] Complete metal7. [INFO DRT-0024] Complete via7. [INFO DRT-0024] Complete metal8. [INFO DRT-0024] Complete via8. [INFO DRT-0024] Complete metal9. [INFO DRT-0024] Complete via9. [INFO DRT-0024] Complete metal10. [INFO DRT-0033] active shape region query size = 0. [INFO DRT-0033] FR_VIA shape region query size = 0. [INFO DRT-0033] metal1 shape region query size = 8236. [INFO DRT-0033] via1 shape region query size = 99. [INFO DRT-0033] metal2 shape region query size = 66. [INFO DRT-0033] via2 shape region query size = 99. [INFO DRT-0033] metal3 shape region query size = 66. [INFO DRT-0033] via3 shape region query size = 99. [INFO DRT-0033] metal4 shape region query size = 40. [INFO DRT-0033] via4 shape region query size = 40. [INFO DRT-0033] metal5 shape region query size = 33. [INFO DRT-0033] via5 shape region query size = 40. [INFO DRT-0033] metal6 shape region query size = 37. [INFO DRT-0033] via6 shape region query size = 16. [INFO DRT-0033] metal7 shape region query size = 6. [INFO DRT-0033] via7 shape region query size = 0. [INFO DRT-0033] metal8 shape region query size = 0. [INFO DRT-0033] via8 shape region query size = 0. [INFO DRT-0033] metal9 shape region query size = 0. [INFO DRT-0033] via9 shape region query size = 0. [INFO DRT-0033] metal10 shape region query size = 0. [INFO DRT-0165] Start pin access. [INFO DRT-0078] Complete 296 pins. [INFO DRT-0081] Complete 59 unique inst patterns. [INFO DRT-0084] Complete 216 groups. #scanned instances = 620 #unique instances = 59 #stdCellGenAp = 1403 #stdCellValidPlanarAp = 0 #stdCellValidViaAp = 1022 #stdCellPinNoAp = 0 #stdCellPinCnt = 1755 #instTermValidViaApCnt = 0 #macroGenAp = 0 #macroValidPlanarAp = 0 #macroValidViaAp = 0 #macroNoAp = 0 [INFO DRT-0166] Complete pin access. [INFO DRT-0267] cpu time = 00:00:06, elapsed time = 00:00:02, memory = 259.25 (MB), peak = 257.67 (MB) [INFO DRT-0157] Number of guides: 3792 [INFO DRT-0169] Post process guides. [INFO DRT-0176] GCELLGRID X 0 DO 11 STEP 5700 ; [INFO DRT-0177] GCELLGRID Y 0 DO 11 STEP 5700 ; [INFO DRT-0028] Complete active. [INFO DRT-0028] Complete Fr_VIA. [INFO DRT-0028] Complete metal1. [INFO DRT-0028] Complete via1. [INFO DRT-0028] Complete metal2. [INFO DRT-0028] Complete via2. [INFO DRT-0028] Complete metal3. [INFO DRT-0028] Complete via3. [INFO DRT-0028] Complete metal4. [INFO DRT-0028] Complete via4. [INFO DRT-0028] Complete metal5. [INFO DRT-0028] Complete via5. [INFO DRT-0028] Complete metal6. [INFO DRT-0028] Complete via6. [INFO DRT-0028] Complete metal7. [INFO DRT-0028] Complete via7. [INFO DRT-0028] Complete metal8. [INFO DRT-0028] Complete via8. [INFO DRT-0028] Complete metal9. [INFO DRT-0028] Complete via9. [INFO DRT-0028] Complete metal10. [INFO DRT-0178] Init guide query. [INFO DRT-0035] Complete active (guide). [INFO DRT-0035] Complete Fr_VIA (guide). [INFO DRT-0035] Complete metal1 (guide). [INFO DRT-0035] Complete via1 (guide). [INFO DRT-0035] Complete metal2 (guide). [INFO DRT-0035] Complete via2 (guide). [INFO DRT-0035] Complete metal3 (guide). [INFO DRT-0035] Complete via3 (guide). [INFO DRT-0035] Complete metal4 (guide). [INFO DRT-0035] Complete via4 (guide). [INFO DRT-0035] Complete metal5 (guide). [INFO DRT-0035] Complete via5 (guide). [INFO DRT-0035] Complete metal6 (guide). [INFO DRT-0035] Complete via6 (guide). [INFO DRT-0035] Complete metal7 (guide). [INFO DRT-0035] Complete via7 (guide). [INFO DRT-0035] Complete metal8 (guide). [INFO DRT-0035] Complete via8 (guide). [INFO DRT-0035] Complete metal9 (guide). [INFO DRT-0035] Complete via9 (guide). [INFO DRT-0035] Complete metal10 (guide). [INFO DRT-0036] active guide region query size = 0. [INFO DRT-0036] FR_VIA guide region query size = 0. [INFO DRT-0036] metal1 guide region query size = 1329. [INFO DRT-0036] via1 guide region query size = 0. [INFO DRT-0036] metal2 guide region query size = 1002. [INFO DRT-0036] via2 guide region query size = 0. [INFO DRT-0036] metal3 guide region query size = 511. [INFO DRT-0036] via3 guide region query size = 0. [INFO DRT-0036] metal4 guide region query size = 100. [INFO DRT-0036] via4 guide region query size = 0. [INFO DRT-0036] metal5 guide region query size = 61. [INFO DRT-0036] via5 guide region query size = 0. [INFO DRT-0036] metal6 guide region query size = 29. [INFO DRT-0036] via6 guide region query size = 0. [INFO DRT-0036] metal7 guide region query size = 0. [INFO DRT-0036] via7 guide region query size = 0. [INFO DRT-0036] metal8 guide region query size = 0. [INFO DRT-0036] via8 guide region query size = 0. [INFO DRT-0036] metal9 guide region query size = 0. [INFO DRT-0036] via9 guide region query size = 0. [INFO DRT-0036] metal10 guide region query size = 0. [INFO DRT-0179] Init gr pin query. [INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 260.32 (MB), peak = 258.67 (MB) [INFO DRT-0245] skipped writing guide updates to database. [INFO DRT-0181] Start track assignment. [INFO DRT-0184] Done with 1131 vertical wires in 1 frboxes and 1901 horizontal wires in 1 frboxes. [INFO DRT-0186] Done with 334 vertical wires in 1 frboxes and 357 horizontal wires in 1 frboxes. [INFO DRT-0182] Complete track assignment. [INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 270.05 (MB), peak = 268.48 (MB) [INFO DRT-0187] Start routing data preparation. [INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 270.05 (MB), peak = 268.48 (MB) [INFO DRT-0194] Start detail routing. [INFO DRT-0195] Start 0th optimization iteration. Completing 20% with 0 violations. elapsed time = 00:00:02, memory = 283.66 (MB). Completing 50% with 13 violations. elapsed time = 00:00:03, memory = 302.66 (MB). Completing 70% with 17 violations. elapsed time = 00:00:04, memory = 321.23 (MB). Completing 100% with 30 violations. elapsed time = 00:00:04, memory = 333.52 (MB). [INFO DRT-0199] Number of violations = 39. Viol/Layer metal2 metal3 Metal Spacing 5 0 Recheck 4 5 Short 25 0 [INFO DRT-0267] cpu time = 00:00:06, elapsed time = 00:00:05, memory = 887.84 (MB), peak = 885.32 (MB) Total wire length = 3488 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 1452 um. Total wire length on LAYER metal3 = 1678 um. Total wire length on LAYER metal4 = 239 um. Total wire length on LAYER metal5 = 85 um. Total wire length on LAYER metal6 = 32 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 3329. Up-via summary (total 3329): --------------- active 0 metal1 1749 metal2 1362 metal3 120 metal4 69 metal5 29 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 3329 [INFO DRT-0195] Start 1st optimization iteration. Completing 20% with 39 violations. elapsed time = 00:00:00, memory = 904.42 (MB). Completing 50% with 37 violations. elapsed time = 00:00:02, memory = 935.17 (MB). Completing 70% with 28 violations. elapsed time = 00:00:03, memory = 936.81 (MB). Completing 100% with 22 violations. elapsed time = 00:00:04, memory = 963.07 (MB). [INFO DRT-0199] Number of violations = 22. Viol/Layer via1 metal2 Cut Spacing 1 0 Metal Spacing 0 4 Short 0 17 [INFO DRT-0267] cpu time = 00:00:06, elapsed time = 00:00:04, memory = 964.18 (MB), peak = 961.82 (MB) Total wire length = 3449 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 1439 um. Total wire length on LAYER metal3 = 1653 um. Total wire length on LAYER metal4 = 238 um. Total wire length on LAYER metal5 = 84 um. Total wire length on LAYER metal6 = 34 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 3289. Up-via summary (total 3289): --------------- active 0 metal1 1750 metal2 1329 metal3 114 metal4 67 metal5 29 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 3289 [INFO DRT-0195] Start 2nd optimization iteration. Completing 10% with 22 violations. elapsed time = 00:00:00, memory = 964.18 (MB). Completing 20% with 22 violations. elapsed time = 00:00:00, memory = 964.18 (MB). Completing 30% with 22 violations. elapsed time = 00:00:00, memory = 964.18 (MB). Completing 40% with 22 violations. elapsed time = 00:00:00, memory = 964.18 (MB). Completing 50% with 22 violations. elapsed time = 00:00:00, memory = 964.18 (MB). Completing 60% with 22 violations. elapsed time = 00:00:00, memory = 964.18 (MB). Completing 70% with 22 violations. elapsed time = 00:00:00, memory = 980.33 (MB). Completing 80% with 22 violations. elapsed time = 00:00:00, memory = 980.33 (MB). Completing 100% with 16 violations. elapsed time = 00:00:04, memory = 1008.20 (MB). [INFO DRT-0199] Number of violations = 16. Viol/Layer metal2 Metal Spacing 4 Short 12 [INFO DRT-0267] cpu time = 00:00:06, elapsed time = 00:00:05, memory = 1008.20 (MB), peak = 1025.32 (MB) Total wire length = 3442 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 1425 um. Total wire length on LAYER metal3 = 1665 um. Total wire length on LAYER metal4 = 230 um. Total wire length on LAYER metal5 = 83 um. Total wire length on LAYER metal6 = 36 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 3291. Up-via summary (total 3291): --------------- active 0 metal1 1745 metal2 1331 metal3 119 metal4 67 metal5 29 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 3291 [INFO DRT-0195] Start 3rd guides tiles iteration. Completing 10% with 16 violations. elapsed time = 00:00:00, memory = 1021.29 (MB). Completing 20% with 16 violations. elapsed time = 00:00:00, memory = 1022.22 (MB). Completing 30% with 16 violations. elapsed time = 00:00:00, memory = 1023.32 (MB). Completing 40% with 5 violations. elapsed time = 00:00:00, memory = 1023.33 (MB). Completing 50% with 5 violations. elapsed time = 00:00:00, memory = 1034.73 (MB). Completing 60% with 5 violations. elapsed time = 00:00:00, memory = 1042.59 (MB). Completing 70% with 1 violations. elapsed time = 00:00:01, memory = 1042.59 (MB). Completing 80% with 1 violations. elapsed time = 00:00:01, memory = 1042.59 (MB). Completing 90% with 1 violations. elapsed time = 00:00:01, memory = 1042.59 (MB). Completing 100% with 0 violations. elapsed time = 00:00:01, memory = 1042.59 (MB). [INFO DRT-0199] Number of violations = 0. [INFO DRT-0267] cpu time = 00:00:03, elapsed time = 00:00:01, memory = 1042.59 (MB), peak = 1040.19 (MB) Total wire length = 3448 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 1403 um. Total wire length on LAYER metal3 = 1678 um. Total wire length on LAYER metal4 = 252 um. Total wire length on LAYER metal5 = 76 um. Total wire length on LAYER metal6 = 36 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 3318. Up-via summary (total 3318): --------------- active 0 metal1 1745 metal2 1343 metal3 137 metal4 64 metal5 29 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 3318 [INFO DRT-0198] Complete detail routing. Total wire length = 3448 um. Total wire length on LAYER metal1 = 0 um. Total wire length on LAYER metal2 = 1403 um. Total wire length on LAYER metal3 = 1678 um. Total wire length on LAYER metal4 = 252 um. Total wire length on LAYER metal5 = 76 um. Total wire length on LAYER metal6 = 36 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 3318. Up-via summary (total 3318): --------------- active 0 metal1 1745 metal2 1343 metal3 137 metal4 64 metal5 29 metal6 0 metal7 0 metal8 0 metal9 0 --------------- 3318 [INFO DRT-0267] cpu time = 00:00:23, elapsed time = 00:00:17, memory = 1042.66 (MB), peak = 1040.19 (MB) [INFO DRT-0180] Post processing. [INFO DRT-0501] Runtime: 19.93s Took 20 seconds: detailed_route -output_drc ./reports/nangate45/gcd/n45_u70/5_route_drc.rpt -output_maze ./results/nangate45/gcd/n45_u70/maze.log -droute_end_iter 64 -verbose 1 -drc_report_iter_step 5 [WARNING GRT-0246] No diode with LEF class CORE ANTENNACELL found. [INFO ANT-0002] Found 0 net violations. [INFO ANT-0001] Found 0 pin violations. [INFO ANT-0002] Found 0 net violations. [INFO ANT-0001] Found 0 pin violations. Design area 709 um^2 79% utilization. write_db ./results/nangate45/gcd/n45_u70/5_2_route.odb Elapsed time: 0:20.77[h:]min:sec. CPU time: user 32.10 sys 0.38 (156%). Peak memory: 1065156KB. Log Ext Elapsed/s Peak Memory/MB sha1sum result [0:20) 5_2_route .odb 20 1040 2be121e7462cbf875242 /OpenROAD-flow-scripts/flow/scripts/flow.sh 5_3_fillcell fillcell Running fillcell.tcl, stage 5_3_fillcell read_liberty /OpenROAD-flow-scripts/flow/platforms/nangate45/lib/NangateOpenCellLibrary_typical.lib read_db ./results/nangate45/gcd/n45_u70/5_2_route.odb read_sdc ./results/nangate45/gcd/n45_u70/5_1_grt.sdc source /OpenROAD-flow-scripts/flow/platforms/nangate45/setRC.tcl [WARNING STA-0450] virtual clock vclk_core_clock can not be propagated. filler_placement "FILLCELL_X1 FILLCELL_X2 FILLCELL_X4 FILLCELL_X8 FILLCELL_X16 FILLCELL_X32" [INFO DPL-0001] Placed 298 filler instances. Design area 709 um^2 79% utilization. write_db ./results/nangate45/gcd/n45_u70/5_3_fillcell.odb Elapsed time: 0:00.31[h:]min:sec. CPU time: user 0.25 sys 0.03 (91%). Peak memory: 116400KB. Log Ext Elapsed/s Peak Memory/MB sha1sum result [0:20) 5_3_fillcell .odb 0 113 333500aedd05ce713b21 cp ./results/nangate45/gcd/n45_u70/5_3_fillcell.odb ./results/nangate45/gcd/n45_u70/5_route.odb cp ./results/nangate45/gcd/n45_u70/5_1_grt.sdc ./results/nangate45/gcd/n45_u70/5_route.sdc /OpenROAD-flow-scripts/flow/scripts/flow.sh 6_1_fill density_fill Running density_fill.tcl, stage 6_1_fill read_liberty /OpenROAD-flow-scripts/flow/platforms/nangate45/lib/NangateOpenCellLibrary_typical.lib read_db ./results/nangate45/gcd/n45_u70/5_route.odb read_sdc ./results/nangate45/gcd/n45_u70/5_route.sdc source /OpenROAD-flow-scripts/flow/platforms/nangate45/setRC.tcl exec cp ./results/nangate45/gcd/n45_u70/5_route.odb ./results/nangate45/gcd/n45_u70/6_1_fill.odb Elapsed time: 0:00.34[h:]min:sec. CPU time: user 0.24 sys 0.04 (81%). Peak memory: 113844KB. Log Ext Elapsed/s Peak Memory/MB sha1sum result [0:20) 6_1_fill .odb 0 111 333500aedd05ce713b21 cp ./results/nangate45/gcd/n45_u70/5_route.sdc ./results/nangate45/gcd/n45_u70/6_1_fill.sdc /OpenROAD-flow-scripts/flow/scripts/flow.sh 6_report final_report Running final_report.tcl, stage 6_report read_liberty /OpenROAD-flow-scripts/flow/platforms/nangate45/lib/NangateOpenCellLibrary_typical.lib read_db ./results/nangate45/gcd/n45_u70/6_1_fill.odb read_sdc ./results/nangate45/gcd/n45_u70/6_1_fill.sdc source /OpenROAD-flow-scripts/flow/platforms/nangate45/setRC.tcl [WARNING STA-0450] virtual clock vclk_core_clock can not be propagated. write_db ./results/nangate45/gcd/n45_u70/6_final.odb Deleted 0 routing obstructions [INFO RCX-0431] Defined process_corner X with ext_model_index 0 [INFO RCX-0029] Defined extraction corner X [WARNING RCX-0514] The -ext_model_file option is deprecated. Use set_extraction_rules_file command instead. [INFO RCX-0435] Reading extraction model file /OpenROAD-flow-scripts/flow/platforms/nangate45/rcx_patterns.rules ... [INFO RCX-0436] RC segment generation gcd (max_merge_res 50.0) ... [INFO RCX-0040] Final 1725 rc segments [INFO RCX-0439] Coupling Cap extraction gcd ... [INFO RCX-0440] Coupling threshhold is 0.1000 fF, coupling capacitance less than 0.1000 fF will be grounded. [INFO RCX-0442] 48% of 3070 wires extracted [INFO RCX-0442] 100% of 3070 wires extracted [INFO RCX-0045] Extract 646 nets, 2352 rsegs, 2352 caps, 4367 ccs [INFO RCX-0443] 646 nets finished [INFO PSM-0040] All shapes on net VDD are connected. [INFO PSM-0073] Using bump pattern with x-pitch 140.0000um, y-pitch 140.0000um, and size 70.0000um with an reduction factor of 3x. ########## IR report ################# Net : VDD Corner : default Total power : 2.60e-03 W Supply voltage : 1.10e+00 V Worstcase voltage: 1.09e+00 V Average voltage : 1.10e+00 V Average IR drop : 1.88e-03 V Worstcase IR drop: 5.89e-03 V Percentage drop : 0.54 % ###################################### [INFO PSM-0040] All shapes on net VSS are connected. [INFO PSM-0073] Using bump pattern with x-pitch 140.0000um, y-pitch 140.0000um, and size 70.0000um with an reduction factor of 3x. ########## IR report ################# Net : VSS Corner : default Total power : 2.60e-03 W Supply voltage : 0.00e+00 V Worstcase voltage: 4.25e-03 V Average voltage : 2.67e-03 V Average IR drop : 2.67e-03 V Worstcase IR drop: 4.25e-03 V Percentage drop : 0.39 % ###################################### Cell type report: Count Area Fill cell 298 189.92 Tap cell 42 11.17 Clock buffer 5 6.65 Timing Repair Buffer 66 54.53 Inverter 87 51.87 Clock inverter 3 2.13 Sequential cell 35 158.27 Multi-Input combinational cell 382 424.80 Total 918 899.35 Report metrics stage 6, finish... ========================================================================== finish report_design_area -------------------------------------------------------------------------- Design area 709 um^2 79% utilization. [WARNING GUI-0076] QStandardPaths: XDG_RUNTIME_DIR not set, defaulting to '/tmp/runtime-root' [WARNING GUI-0066] Heat map "IR Drop" has not been populated with data. [WARNING GUI-0066] Heat map "Routing Congestion" has not been populated with data. Elapsed time: 0:01.98[h:]min:sec. CPU time: user 1.49 sys 0.11 (80%). Peak memory: 183568KB. Log Ext Elapsed/s Peak Memory/MB sha1sum result [0:20) 6_report 1 179 N/A cp ./results/nangate45/gcd/n45_u70/5_route.sdc ./results/nangate45/gcd/n45_u70/6_final.sdc cp /OpenROAD-flow-scripts/flow/platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef ./objects/nangate45/gcd/n45_u70/klayout_tech.lef /usr/bin/python3 /OpenROAD-flow-scripts/flow/util/generate_klayout_tech.py \ --template /OpenROAD-flow-scripts/flow/platforms/nangate45/FreePDK45.lyt \ --output ./objects/nangate45/gcd/n45_u70/klayout.lyt \ --lef-files ./objects/nangate45/gcd/n45_u70/klayout_tech.lef /OpenROAD-flow-scripts/flow/platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef \ --map-files /usr/bin/python3 /OpenROAD-flow-scripts/flow/scripts/run_command.py --log /OpenROAD-flow-scripts/flow/logs/nangate45/gcd/n45_u70/6_1_merge.log --tee -- \ /OpenROAD-flow-scripts/flow/scripts/klayout.sh -zz -rd design_name=gcd \ -rd in_def=./results/nangate45/gcd/n45_u70/6_final.def \ -rd in_files="/OpenROAD-flow-scripts/flow/platforms/nangate45/gds/NangateOpenCellLibrary.gds " \ -rd seal_file="" \ -rd out_file=./results/nangate45/gcd/n45_u70/6_1_merged.gds \ -rd tech_file=./objects/nangate45/gcd/n45_u70/klayout.lyt \ -rd layer_map= \ -r /OpenROAD-flow-scripts/flow/util/def2stream.py KLayout 0.30.7 Warning: DEF UNITS does not match reader DBU (DEF UNITS is 2000 and corresponds to a DBU of 0.0005, but reader DBU is set to 0.0001) (line=5, cell=, file=6_final.def) [INFO] Reporting cells prior to loading DEF ... /OpenROAD-flow-scripts/flow/platforms/nangate45/gds/NangateOpenCellLibrary.gds [INFO] GDS_ALLOW_EMPTY=fakeram.* [INFO] All LEF cells have matching GDS/OAS cells [INFO] No orphan cells in the final layout Elapsed time: 0:01.30[h:]min:sec. CPU time: user 1.17 sys 0.11 (98%). Peak memory: 434512KB. cp results/nangate45/gcd/n45_u70/6_1_merged.gds results/nangate45/gcd/n45_u70/6_final.gds ./logs/nangate45/gcd/n45_u70 Log Ext Elapsed/s Peak Memory/MB sha1sum result [0:20) 1_1_yosys_canonicalize .rtlil 0 42 0143866d45d6a9e39c47 1_2_yosys .v 0 44 756ad24f74de658d5044 1_2_yosys .sdc 21b872a6567721784485 1_synth .odb 0 112 5574db6bc0e99d58e06a 1_synth .sdc 7fe61694c034e1755ac1 2_1_floorplan .odb 0 132 4240d65985da96c5decc 2_1_floorplan .sdc 7fe61694c034e1755ac1 2_2_floorplan_macro .odb 0 110 4240d65985da96c5decc 2_3_floorplan_tapcell .odb 0 110 146da835d710a360cd2e 2_4_floorplan_pdn .odb 0 112 ff5696052aa6d457e774 3_1_place_gp_skip_io .odb 213 112 a2146838052c266263cb 3_2_place_iop .odb 0 111 1f672fe287f84b17c1ee 3_3_place_gp .odb 304 282 0f92f88eb2a811a25adf 3_4_place_resized .odb 0 129 0f92f88eb2a811a25adf 3_5_place_dp .odb 0 118 4443fd703efc1d4a11c2 4_1_cts .odb 1 143 978b27124ac6d38f39b1 5_1_grt .odb 9 287 f4d77edd6f6a4bb9d9be 5_1_grt .sdc 6dc41493824210708c18 5_2_route .odb 20 1040 2be121e7462cbf875242 5_3_fillcell .odb 0 113 333500aedd05ce713b21 6_1_fill .odb 0 111 333500aedd05ce713b21 6_1_fill .sdc 6dc41493824210708c18 6_1_merge 1 424 N/A 6_report 1 179 N/A Total 549 1040