========================================================================== finish report_tns -------------------------------------------------------------------------- tns max -44.23 ========================================================================== finish report_wns -------------------------------------------------------------------------- wns max -0.12 ========================================================================== finish report_worst_slack -------------------------------------------------------------------------- worst slack max -0.12 ========================================================================== finish report_clock_min_period -------------------------------------------------------------------------- clk period_min = 1.12 fmax = 894.27 vclk_clk period_min = 0.00 fmax = inf ========================================================================== finish report_clock_skew -------------------------------------------------------------------------- Clock clk 0.29 source latency fdct_zigzag.dct_mod.dct_block_2.dct_unit_1.coef[24]$_DFFE_PP_/CK ^ -0.32 target latency fdct_zigzag.dct_mod.dct_block_2.dct_unit_1.macu.mult_res[17]$_DFFE_PP_/CK ^ 0.00 CRPR -------------- -0.03 setup skew Clock vclk_clk No launch/capture paths found. ========================================================================== finish report_checks -path_delay min -------------------------------------------------------------------------- Startpoint: rst (input port clocked by vclk_clk) Endpoint: rle.rz4.deno$_DFFE_PN0P_ (removal check against rising-edge clock clk) Path Group: asynchronous Path Type: min Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 0.00 clock vclk_clk (rise edge) 0.29 0.29 clock network delay (ideal) 0.20 0.49 ^ input external delay 1 1.11 0.00 0.00 0.49 ^ rst (in) rst (net) 0.00 0.00 0.49 ^ hold12143/A (CLKBUF_X1) 1 0.91 0.01 0.02 0.51 ^ hold12143/Z (CLKBUF_X1) net12142 (net) 0.01 0.00 0.51 ^ hold11885/A (CLKBUF_X1) 1 1.59 0.01 0.03 0.54 ^ hold11885/Z (CLKBUF_X1) net11884 (net) 0.01 0.00 0.54 ^ input20/A (CLKBUF_X3) 14 56.55 0.04 0.06 0.60 ^ input20/Z (CLKBUF_X3) net19 (net) 0.04 0.01 0.60 ^ rle.rz4.deno$_DFFE_PN0P_/RN (DFFR_X1) 0.60 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock source latency 1 38.16 0.00 0.00 0.00 ^ clk (in) clk (net) 0.01 0.01 0.01 ^ clkbuf_0_clk/A (CLKBUF_X3) 4 46.34 0.04 0.06 0.07 ^ clkbuf_0_clk/Z (CLKBUF_X3) clknet_0_clk (net) 0.04 0.00 0.08 ^ clkbuf_2_2_0_clk/A (CLKBUF_X3) 16 82.02 0.06 0.10 0.18 ^ clkbuf_2_2_0_clk/Z (CLKBUF_X3) clknet_2_2_0_clk (net) 0.06 0.01 0.19 ^ clkbuf_6_46_0_clk/A (CLKBUF_X3) 17 39.49 0.03 0.08 0.26 ^ clkbuf_6_46_0_clk/Z (CLKBUF_X3) clknet_6_46_0_clk (net) 0.03 0.00 0.26 ^ clkbuf_leaf_495_clk/A (CLKBUF_X3) 9 10.55 0.01 0.04 0.31 ^ clkbuf_leaf_495_clk/Z (CLKBUF_X3) clknet_leaf_495_clk (net) 0.01 0.00 0.31 ^ rle.rz4.deno$_DFFE_PN0P_/CK (DFFR_X1) 0.00 0.31 clock reconvergence pessimism 0.23 0.54 library removal time 0.54 data required time ----------------------------------------------------------------------------- 0.54 data required time -0.60 data arrival time ----------------------------------------------------------------------------- 0.06 slack (MET) Startpoint: dqnr_doe$_DFFE_PP_ (rising edge-triggered flip-flop clocked by clk) Endpoint: rle.ddstrb$_DFF_PN0_ (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock source latency 1 38.16 0.00 0.00 0.00 ^ clk (in) clk (net) 0.01 0.01 0.01 ^ clkbuf_0_clk/A (CLKBUF_X3) 4 46.34 0.04 0.06 0.07 ^ clkbuf_0_clk/Z (CLKBUF_X3) clknet_0_clk (net) 0.04 0.00 0.08 ^ clkbuf_2_2_0_clk/A (CLKBUF_X3) 16 82.02 0.06 0.10 0.18 ^ clkbuf_2_2_0_clk/Z (CLKBUF_X3) clknet_2_2_0_clk (net) 0.06 0.01 0.19 ^ clkbuf_6_40_0_clk/A (CLKBUF_X3) 14 38.55 0.03 0.08 0.26 ^ clkbuf_6_40_0_clk/Z (CLKBUF_X3) clknet_6_40_0_clk (net) 0.03 0.00 0.26 ^ clkbuf_leaf_539_clk/A (CLKBUF_X3) 7 8.01 0.01 0.04 0.31 ^ clkbuf_leaf_539_clk/Z (CLKBUF_X3) clknet_leaf_539_clk (net) 0.01 0.00 0.31 ^ dqnr_doe$_DFFE_PP_/CK (DFF_X1) 2 2.93 0.01 0.09 0.39 v dqnr_doe$_DFFE_PP_/Q (DFF_X1) dc_diff_doe (net) 0.01 0.00 0.39 v rle.ddstrb$_DFF_PN0_/D (DFFR_X1) 0.39 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock source latency 1 38.16 0.00 0.00 0.00 ^ clk (in) clk (net) 0.01 0.01 0.01 ^ clkbuf_0_clk/A (CLKBUF_X3) 4 46.34 0.04 0.06 0.07 ^ clkbuf_0_clk/Z (CLKBUF_X3) clknet_0_clk (net) 0.04 0.00 0.08 ^ clkbuf_2_2_0_clk/A (CLKBUF_X3) 16 82.02 0.06 0.10 0.18 ^ clkbuf_2_2_0_clk/Z (CLKBUF_X3) clknet_2_2_0_clk (net) 0.06 0.01 0.19 ^ clkbuf_6_40_0_clk/A (CLKBUF_X3) 14 38.55 0.03 0.08 0.26 ^ clkbuf_6_40_0_clk/Z (CLKBUF_X3) clknet_6_40_0_clk (net) 0.03 0.00 0.26 ^ clkbuf_leaf_539_clk/A (CLKBUF_X3) 7 8.01 0.01 0.04 0.31 ^ clkbuf_leaf_539_clk/Z (CLKBUF_X3) clknet_leaf_539_clk (net) 0.01 0.00 0.31 ^ rle.ddstrb$_DFF_PN0_/CK (DFFR_X1) 0.00 0.31 clock reconvergence pessimism 0.00 0.31 library hold time 0.31 data required time ----------------------------------------------------------------------------- 0.31 data required time -0.39 data arrival time ----------------------------------------------------------------------------- 0.08 slack (MET) Startpoint: rle.rz4.sizeo[2]$_DFFE_PP_ (rising edge-triggered flip-flop clocked by clk) Endpoint: size[2] (output port clocked by vclk_clk) Path Group: vclk_clk Path Type: min Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock source latency 1 38.16 0.00 0.00 0.00 ^ clk (in) clk (net) 0.01 0.01 0.01 ^ clkbuf_0_clk/A (CLKBUF_X3) 4 46.34 0.04 0.06 0.07 ^ clkbuf_0_clk/Z (CLKBUF_X3) clknet_0_clk (net) 0.04 0.00 0.08 ^ clkbuf_2_2_0_clk/A (CLKBUF_X3) 16 82.02 0.06 0.10 0.18 ^ clkbuf_2_2_0_clk/Z (CLKBUF_X3) clknet_2_2_0_clk (net) 0.06 0.01 0.19 ^ clkbuf_6_47_0_clk/A (CLKBUF_X3) 17 37.49 0.03 0.07 0.26 ^ clkbuf_6_47_0_clk/Z (CLKBUF_X3) clknet_6_47_0_clk (net) 0.03 0.00 0.26 ^ clkbuf_leaf_474_clk/A (CLKBUF_X3) 8 9.37 0.01 0.04 0.31 ^ clkbuf_leaf_474_clk/Z (CLKBUF_X3) clknet_leaf_474_clk (net) 0.01 0.00 0.31 ^ rle.rz4.sizeo[2]$_DFFE_PP_/CK (DFF_X1) 2 1.95 0.01 0.08 0.39 v rle.rz4.sizeo[2]$_DFFE_PP_/Q (DFF_X1) net44 (net) 0.01 0.00 0.39 v output45/A (BUF_X1) 1 0.27 0.00 0.02 0.41 v output45/Z (BUF_X1) size[2] (net) 0.00 0.00 0.41 v size[2] (out) 0.41 data arrival time 0.00 0.00 0.00 clock vclk_clk (rise edge) 0.29 0.29 clock network delay (ideal) 0.00 0.29 clock reconvergence pessimism -0.20 0.09 output external delay 0.09 data required time ----------------------------------------------------------------------------- 0.09 data required time -0.41 data arrival time ----------------------------------------------------------------------------- 0.32 slack (MET) ========================================================================== finish report_checks -path_delay max -------------------------------------------------------------------------- Startpoint: rst (input port clocked by vclk_clk) Endpoint: qnr.dep[6]$_DFFE_PN0P_ (recovery check against rising-edge clock clk) Path Group: asynchronous Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 0.00 clock vclk_clk (rise edge) 0.29 0.29 clock network delay (ideal) 0.20 0.49 ^ input external delay 1 1.11 0.00 0.00 0.49 ^ rst (in) rst (net) 0.00 0.00 0.49 ^ hold12143/A (CLKBUF_X1) 1 0.91 0.01 0.02 0.51 ^ hold12143/Z (CLKBUF_X1) net12142 (net) 0.01 0.00 0.51 ^ hold11885/A (CLKBUF_X1) 1 1.59 0.01 0.03 0.54 ^ hold11885/Z (CLKBUF_X1) net11884 (net) 0.01 0.00 0.54 ^ input20/A (CLKBUF_X3) 14 56.55 0.04 0.06 0.60 ^ input20/Z (CLKBUF_X3) net19 (net) 0.04 0.00 0.60 ^ place11479/A (BUF_X1) 14 32.66 0.07 0.10 0.70 ^ place11479/Z (BUF_X1) net11478 (net) 0.07 0.01 0.71 ^ place11478/A (BUF_X2) 26 54.87 0.06 0.09 0.80 ^ place11478/Z (BUF_X2) net11477 (net) 0.06 0.01 0.80 ^ qnr.dep[6]$_DFFE_PN0P_/RN (DFFR_X1) 0.80 data arrival time 1.00 1.00 clock clk (rise edge) 0.00 1.00 clock source latency 1 38.16 0.00 0.00 1.00 ^ clk (in) clk (net) 0.01 0.01 1.01 ^ clkbuf_0_clk/A (CLKBUF_X3) 4 46.34 0.04 0.06 1.07 ^ clkbuf_0_clk/Z (CLKBUF_X3) clknet_0_clk (net) 0.04 0.00 1.08 ^ clkbuf_2_2_0_clk/A (CLKBUF_X3) 16 82.02 0.06 0.10 1.18 ^ clkbuf_2_2_0_clk/Z (CLKBUF_X3) clknet_2_2_0_clk (net) 0.06 0.01 1.19 ^ clkbuf_6_40_0_clk/A (CLKBUF_X3) 14 38.55 0.03 0.08 1.26 ^ clkbuf_6_40_0_clk/Z (CLKBUF_X3) clknet_6_40_0_clk (net) 0.03 0.00 1.26 ^ clkbuf_leaf_540_clk/A (CLKBUF_X3) 7 8.90 0.01 0.04 1.31 ^ clkbuf_leaf_540_clk/Z (CLKBUF_X3) clknet_leaf_540_clk (net) 0.01 0.00 1.31 ^ qnr.dep[6]$_DFFE_PN0P_/CK (DFFR_X1) 0.00 1.31 clock reconvergence pessimism 0.05 1.36 library recovery time 1.36 data required time ----------------------------------------------------------------------------- 1.36 data required time -0.80 data arrival time ----------------------------------------------------------------------------- 0.55 slack (MET) Startpoint: fdct_zigzag.dct_mod.ddin[4]$_DFFE_PN0P_ (rising edge-triggered flip-flop clocked by clk) Endpoint: fdct_zigzag.dct_mod.dct_block_4.dct_unit_1.macu.mult_res[16]$_DFFE_PP_ (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock source latency 1 38.16 0.00 0.00 0.00 ^ clk (in) clk (net) 0.01 0.01 0.01 ^ clkbuf_0_clk/A (CLKBUF_X3) 4 46.34 0.04 0.06 0.07 ^ clkbuf_0_clk/Z (CLKBUF_X3) clknet_0_clk (net) 0.04 0.00 0.08 ^ clkbuf_2_0_0_clk/A (CLKBUF_X3) 16 74.58 0.06 0.09 0.17 ^ clkbuf_2_0_0_clk/Z (CLKBUF_X3) clknet_2_0_0_clk (net) 0.06 0.00 0.18 ^ clkbuf_6_14_0_clk/A (CLKBUF_X3) 10 35.10 0.03 0.07 0.25 ^ clkbuf_6_14_0_clk/Z (CLKBUF_X3) clknet_6_14_0_clk (net) 0.03 0.00 0.25 ^ clkbuf_leaf_646_clk/A (CLKBUF_X3) 4 12.87 0.01 0.05 0.30 ^ clkbuf_leaf_646_clk/Z (CLKBUF_X3) clknet_leaf_646_clk (net) 0.01 0.00 0.30 ^ fdct_zigzag.dct_mod.ddin[4]$_DFFE_PN0P_/CK (DFFR_X2) 2 11.10 0.01 0.11 0.40 v fdct_zigzag.dct_mod.ddin[4]$_DFFE_PN0P_/Q (DFFR_X2) fdct_zigzag.dct_mod.dct_block_0.dct_unit_0.ddin[4] (net) 0.01 0.00 0.40 v rebuffer12003/A (BUF_X8) 2 23.19 0.01 0.03 0.43 v rebuffer12003/Z (BUF_X8) net12002 (net) 0.01 0.00 0.43 v place11032/A (BUF_X8) 5 42.96 0.01 0.03 0.46 v place11032/Z (BUF_X8) net11031 (net) 0.02 0.01 0.47 v place11025/A (BUF_X8) 25 71.73 0.01 0.03 0.50 v place11025/Z (BUF_X8) net11024 (net) 0.03 0.02 0.52 v place11022/A (BUF_X1) 2 3.20 0.01 0.04 0.56 v place11022/Z (BUF_X1) net11021 (net) 0.01 0.00 0.56 v _066238_/A1 (NAND2_X1) 1 3.40 0.01 0.02 0.58 ^ _066238_/ZN (NAND2_X1) _014498_ (net) 0.01 0.00 0.58 ^ _066239_/A (INV_X2) 3 9.23 0.01 0.01 0.59 v _066239_/ZN (INV_X2) _002941_ (net) 0.01 0.00 0.59 v place9826/A (BUF_X1) 2 4.47 0.01 0.03 0.63 v place9826/Z (BUF_X1) net9825 (net) 0.01 0.00 0.63 v place9825/A (BUF_X1) 1 6.15 0.01 0.03 0.66 v place9825/Z (BUF_X1) net9824 (net) 0.01 0.00 0.66 v _111390_/B (FA_X1) 1 6.53 0.02 0.09 0.75 v _111390_/CO (FA_X1) _061799_ (net) 0.02 0.00 0.75 v _111828_/A (FA_X1) 1 2.85 0.01 0.12 0.87 ^ _111828_/S (FA_X1) _059792_ (net) 0.01 0.00 0.87 ^ _110463_/CI (FA_X1) 1 3.62 0.02 0.09 0.96 v _110463_/S (FA_X1) _059794_ (net) 0.02 0.00 0.96 v _110723_/B (FA_X1) 1 3.54 0.01 0.13 1.09 ^ _110723_/S (FA_X1) _060380_ (net) 0.01 0.00 1.09 ^ _112636_/B (HA_X1) 3 6.63 0.04 0.07 1.16 ^ _112636_/S (HA_X1) _003658_ (net) 0.04 0.00 1.16 ^ _092017_/A2 (NAND3_X1) 1 1.61 0.01 0.03 1.19 v _092017_/ZN (NAND3_X1) _035837_ (net) 0.01 0.00 1.19 v _092018_/A2 (NAND2_X1) 3 7.70 0.02 0.03 1.22 ^ _092018_/ZN (NAND2_X1) _035838_ (net) 0.02 0.00 1.22 ^ _092020_/B1 (AOI21_X2) 2 4.18 0.01 0.02 1.24 v _092020_/ZN (AOI21_X2) _035840_ (net) 0.01 0.00 1.24 v _092022_/B1 (OAI21_X2) 3 5.18 0.02 0.03 1.27 ^ _092022_/ZN (OAI21_X2) _035842_ (net) 0.02 0.00 1.27 ^ _092023_/A (INV_X1) 1 1.59 0.01 0.01 1.28 v _092023_/ZN (INV_X1) _035843_ (net) 0.01 0.00 1.28 v _092025_/B1 (OAI21_X1) 2 2.82 0.02 0.03 1.31 ^ _092025_/ZN (OAI21_X1) _035845_ (net) 0.02 0.00 1.31 ^ _092026_/A1 (OR2_X1) 1 1.66 0.01 0.03 1.34 ^ _092026_/ZN (OR2_X1) _035846_ (net) 0.01 0.00 1.34 ^ _092028_/A1 (NAND3_X1) 1 1.61 0.02 0.02 1.36 v _092028_/ZN (NAND3_X1) _035848_ (net) 0.02 0.00 1.36 v _092030_/A (OAI21_X1) 1 1.25 0.02 0.02 1.38 ^ _092030_/ZN (OAI21_X1) _011510_ (net) 0.02 0.00 1.38 ^ fdct_zigzag.dct_mod.dct_block_4.dct_unit_1.macu.mult_res[16]$_DFFE_PP_/D (DFF_X1) 1.38 data arrival time 1.00 1.00 clock clk (rise edge) 0.00 1.00 clock source latency 1 38.16 0.00 0.00 1.00 ^ clk (in) clk (net) 0.01 0.01 1.01 ^ clkbuf_0_clk/A (CLKBUF_X3) 4 46.34 0.04 0.06 1.07 ^ clkbuf_0_clk/Z (CLKBUF_X3) clknet_0_clk (net) 0.04 0.00 1.08 ^ clkbuf_2_1_0_clk/A (CLKBUF_X3) 16 74.66 0.06 0.10 1.17 ^ clkbuf_2_1_0_clk/Z (CLKBUF_X3) clknet_2_1_0_clk (net) 0.06 0.00 1.18 ^ clkbuf_6_19_0_clk/A (CLKBUF_X3) 9 29.89 0.03 0.07 1.25 ^ clkbuf_6_19_0_clk/Z (CLKBUF_X3) clknet_6_19_0_clk (net) 0.03 0.00 1.25 ^ clkbuf_leaf_143_clk/A (CLKBUF_X3) 6 13.52 0.01 0.04 1.29 ^ clkbuf_leaf_143_clk/Z (CLKBUF_X3) clknet_leaf_143_clk (net) 0.01 0.00 1.29 ^ fdct_zigzag.dct_mod.dct_block_4.dct_unit_1.macu.mult_res[16]$_DFFE_PP_/CK (DFF_X1) 0.00 1.29 clock reconvergence pessimism -0.03 1.26 library setup time 1.26 data required time ----------------------------------------------------------------------------- 1.26 data required time -1.38 data arrival time ----------------------------------------------------------------------------- -0.12 slack (VIOLATED) Startpoint: qnr.qnt_cnt[3]$_DFFE_PN0P_ (rising edge-triggered flip-flop clocked by clk) Endpoint: qnt_cnt[3] (output port clocked by vclk_clk) Path Group: vclk_clk Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock source latency 1 38.16 0.00 0.00 0.00 ^ clk (in) clk (net) 0.01 0.01 0.01 ^ clkbuf_0_clk/A (CLKBUF_X3) 4 46.34 0.04 0.06 0.07 ^ clkbuf_0_clk/Z (CLKBUF_X3) clknet_0_clk (net) 0.04 0.00 0.08 ^ clkbuf_2_2_0_clk/A (CLKBUF_X3) 16 82.02 0.06 0.10 0.18 ^ clkbuf_2_2_0_clk/Z (CLKBUF_X3) clknet_2_2_0_clk (net) 0.06 0.01 0.19 ^ clkbuf_6_46_0_clk/A (CLKBUF_X3) 17 39.49 0.03 0.08 0.26 ^ clkbuf_6_46_0_clk/Z (CLKBUF_X3) clknet_6_46_0_clk (net) 0.03 0.00 0.26 ^ clkbuf_leaf_492_clk/A (CLKBUF_X3) 7 10.79 0.01 0.05 0.31 ^ clkbuf_leaf_492_clk/Z (CLKBUF_X3) clknet_leaf_492_clk (net) 0.01 0.00 0.31 ^ qnr.qnt_cnt[3]$_DFFE_PN0P_/CK (DFFR_X1) 6 10.62 0.03 0.12 0.43 ^ qnr.qnt_cnt[3]$_DFFE_PN0P_/Q (DFFR_X1) net35 (net) 0.03 0.00 0.43 ^ output36/A (BUF_X1) 1 0.68 0.01 0.02 0.46 ^ output36/Z (BUF_X1) qnt_cnt[3] (net) 0.01 0.00 0.46 ^ qnt_cnt[3] (out) 0.46 data arrival time 0.00 1.00 1.00 clock vclk_clk (rise edge) 0.29 1.29 clock network delay (ideal) 0.00 1.29 clock reconvergence pessimism -0.20 1.09 output external delay 1.09 data required time ----------------------------------------------------------------------------- 1.09 data required time -0.46 data arrival time ----------------------------------------------------------------------------- 0.63 slack (MET) ========================================================================== finish report_checks -unconstrained -------------------------------------------------------------------------- Startpoint: rst (input port clocked by vclk_clk) Endpoint: qnr.dep[6]$_DFFE_PN0P_ (recovery check against rising-edge clock clk) Path Group: asynchronous Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 0.00 clock vclk_clk (rise edge) 0.29 0.29 clock network delay (ideal) 0.20 0.49 ^ input external delay 1 1.11 0.00 0.00 0.49 ^ rst (in) rst (net) 0.00 0.00 0.49 ^ hold12143/A (CLKBUF_X1) 1 0.91 0.01 0.02 0.51 ^ hold12143/Z (CLKBUF_X1) net12142 (net) 0.01 0.00 0.51 ^ hold11885/A (CLKBUF_X1) 1 1.59 0.01 0.03 0.54 ^ hold11885/Z (CLKBUF_X1) net11884 (net) 0.01 0.00 0.54 ^ input20/A (CLKBUF_X3) 14 56.55 0.04 0.06 0.60 ^ input20/Z (CLKBUF_X3) net19 (net) 0.04 0.00 0.60 ^ place11479/A (BUF_X1) 14 32.66 0.07 0.10 0.70 ^ place11479/Z (BUF_X1) net11478 (net) 0.07 0.01 0.71 ^ place11478/A (BUF_X2) 26 54.87 0.06 0.09 0.80 ^ place11478/Z (BUF_X2) net11477 (net) 0.06 0.01 0.80 ^ qnr.dep[6]$_DFFE_PN0P_/RN (DFFR_X1) 0.80 data arrival time 1.00 1.00 clock clk (rise edge) 0.00 1.00 clock source latency 1 38.16 0.00 0.00 1.00 ^ clk (in) clk (net) 0.01 0.01 1.01 ^ clkbuf_0_clk/A (CLKBUF_X3) 4 46.34 0.04 0.06 1.07 ^ clkbuf_0_clk/Z (CLKBUF_X3) clknet_0_clk (net) 0.04 0.00 1.08 ^ clkbuf_2_2_0_clk/A (CLKBUF_X3) 16 82.02 0.06 0.10 1.18 ^ clkbuf_2_2_0_clk/Z (CLKBUF_X3) clknet_2_2_0_clk (net) 0.06 0.01 1.19 ^ clkbuf_6_40_0_clk/A (CLKBUF_X3) 14 38.55 0.03 0.08 1.26 ^ clkbuf_6_40_0_clk/Z (CLKBUF_X3) clknet_6_40_0_clk (net) 0.03 0.00 1.26 ^ clkbuf_leaf_540_clk/A (CLKBUF_X3) 7 8.90 0.01 0.04 1.31 ^ clkbuf_leaf_540_clk/Z (CLKBUF_X3) clknet_leaf_540_clk (net) 0.01 0.00 1.31 ^ qnr.dep[6]$_DFFE_PN0P_/CK (DFFR_X1) 0.00 1.31 clock reconvergence pessimism 0.05 1.36 library recovery time 1.36 data required time ----------------------------------------------------------------------------- 1.36 data required time -0.80 data arrival time ----------------------------------------------------------------------------- 0.55 slack (MET) Startpoint: fdct_zigzag.dct_mod.ddin[4]$_DFFE_PN0P_ (rising edge-triggered flip-flop clocked by clk) Endpoint: fdct_zigzag.dct_mod.dct_block_4.dct_unit_1.macu.mult_res[16]$_DFFE_PP_ (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock source latency 1 38.16 0.00 0.00 0.00 ^ clk (in) clk (net) 0.01 0.01 0.01 ^ clkbuf_0_clk/A (CLKBUF_X3) 4 46.34 0.04 0.06 0.07 ^ clkbuf_0_clk/Z (CLKBUF_X3) clknet_0_clk (net) 0.04 0.00 0.08 ^ clkbuf_2_0_0_clk/A (CLKBUF_X3) 16 74.58 0.06 0.09 0.17 ^ clkbuf_2_0_0_clk/Z (CLKBUF_X3) clknet_2_0_0_clk (net) 0.06 0.00 0.18 ^ clkbuf_6_14_0_clk/A (CLKBUF_X3) 10 35.10 0.03 0.07 0.25 ^ clkbuf_6_14_0_clk/Z (CLKBUF_X3) clknet_6_14_0_clk (net) 0.03 0.00 0.25 ^ clkbuf_leaf_646_clk/A (CLKBUF_X3) 4 12.87 0.01 0.05 0.30 ^ clkbuf_leaf_646_clk/Z (CLKBUF_X3) clknet_leaf_646_clk (net) 0.01 0.00 0.30 ^ fdct_zigzag.dct_mod.ddin[4]$_DFFE_PN0P_/CK (DFFR_X2) 2 11.10 0.01 0.11 0.40 v fdct_zigzag.dct_mod.ddin[4]$_DFFE_PN0P_/Q (DFFR_X2) fdct_zigzag.dct_mod.dct_block_0.dct_unit_0.ddin[4] (net) 0.01 0.00 0.40 v rebuffer12003/A (BUF_X8) 2 23.19 0.01 0.03 0.43 v rebuffer12003/Z (BUF_X8) net12002 (net) 0.01 0.00 0.43 v place11032/A (BUF_X8) 5 42.96 0.01 0.03 0.46 v place11032/Z (BUF_X8) net11031 (net) 0.02 0.01 0.47 v place11025/A (BUF_X8) 25 71.73 0.01 0.03 0.50 v place11025/Z (BUF_X8) net11024 (net) 0.03 0.02 0.52 v place11022/A (BUF_X1) 2 3.20 0.01 0.04 0.56 v place11022/Z (BUF_X1) net11021 (net) 0.01 0.00 0.56 v _066238_/A1 (NAND2_X1) 1 3.40 0.01 0.02 0.58 ^ _066238_/ZN (NAND2_X1) _014498_ (net) 0.01 0.00 0.58 ^ _066239_/A (INV_X2) 3 9.23 0.01 0.01 0.59 v _066239_/ZN (INV_X2) _002941_ (net) 0.01 0.00 0.59 v place9826/A (BUF_X1) 2 4.47 0.01 0.03 0.63 v place9826/Z (BUF_X1) net9825 (net) 0.01 0.00 0.63 v place9825/A (BUF_X1) 1 6.15 0.01 0.03 0.66 v place9825/Z (BUF_X1) net9824 (net) 0.01 0.00 0.66 v _111390_/B (FA_X1) 1 6.53 0.02 0.09 0.75 v _111390_/CO (FA_X1) _061799_ (net) 0.02 0.00 0.75 v _111828_/A (FA_X1) 1 2.85 0.01 0.12 0.87 ^ _111828_/S (FA_X1) _059792_ (net) 0.01 0.00 0.87 ^ _110463_/CI (FA_X1) 1 3.62 0.02 0.09 0.96 v _110463_/S (FA_X1) _059794_ (net) 0.02 0.00 0.96 v _110723_/B (FA_X1) 1 3.54 0.01 0.13 1.09 ^ _110723_/S (FA_X1) _060380_ (net) 0.01 0.00 1.09 ^ _112636_/B (HA_X1) 3 6.63 0.04 0.07 1.16 ^ _112636_/S (HA_X1) _003658_ (net) 0.04 0.00 1.16 ^ _092017_/A2 (NAND3_X1) 1 1.61 0.01 0.03 1.19 v _092017_/ZN (NAND3_X1) _035837_ (net) 0.01 0.00 1.19 v _092018_/A2 (NAND2_X1) 3 7.70 0.02 0.03 1.22 ^ _092018_/ZN (NAND2_X1) _035838_ (net) 0.02 0.00 1.22 ^ _092020_/B1 (AOI21_X2) 2 4.18 0.01 0.02 1.24 v _092020_/ZN (AOI21_X2) _035840_ (net) 0.01 0.00 1.24 v _092022_/B1 (OAI21_X2) 3 5.18 0.02 0.03 1.27 ^ _092022_/ZN (OAI21_X2) _035842_ (net) 0.02 0.00 1.27 ^ _092023_/A (INV_X1) 1 1.59 0.01 0.01 1.28 v _092023_/ZN (INV_X1) _035843_ (net) 0.01 0.00 1.28 v _092025_/B1 (OAI21_X1) 2 2.82 0.02 0.03 1.31 ^ _092025_/ZN (OAI21_X1) _035845_ (net) 0.02 0.00 1.31 ^ _092026_/A1 (OR2_X1) 1 1.66 0.01 0.03 1.34 ^ _092026_/ZN (OR2_X1) _035846_ (net) 0.01 0.00 1.34 ^ _092028_/A1 (NAND3_X1) 1 1.61 0.02 0.02 1.36 v _092028_/ZN (NAND3_X1) _035848_ (net) 0.02 0.00 1.36 v _092030_/A (OAI21_X1) 1 1.25 0.02 0.02 1.38 ^ _092030_/ZN (OAI21_X1) _011510_ (net) 0.02 0.00 1.38 ^ fdct_zigzag.dct_mod.dct_block_4.dct_unit_1.macu.mult_res[16]$_DFFE_PP_/D (DFF_X1) 1.38 data arrival time 1.00 1.00 clock clk (rise edge) 0.00 1.00 clock source latency 1 38.16 0.00 0.00 1.00 ^ clk (in) clk (net) 0.01 0.01 1.01 ^ clkbuf_0_clk/A (CLKBUF_X3) 4 46.34 0.04 0.06 1.07 ^ clkbuf_0_clk/Z (CLKBUF_X3) clknet_0_clk (net) 0.04 0.00 1.08 ^ clkbuf_2_1_0_clk/A (CLKBUF_X3) 16 74.66 0.06 0.10 1.17 ^ clkbuf_2_1_0_clk/Z (CLKBUF_X3) clknet_2_1_0_clk (net) 0.06 0.00 1.18 ^ clkbuf_6_19_0_clk/A (CLKBUF_X3) 9 29.89 0.03 0.07 1.25 ^ clkbuf_6_19_0_clk/Z (CLKBUF_X3) clknet_6_19_0_clk (net) 0.03 0.00 1.25 ^ clkbuf_leaf_143_clk/A (CLKBUF_X3) 6 13.52 0.01 0.04 1.29 ^ clkbuf_leaf_143_clk/Z (CLKBUF_X3) clknet_leaf_143_clk (net) 0.01 0.00 1.29 ^ fdct_zigzag.dct_mod.dct_block_4.dct_unit_1.macu.mult_res[16]$_DFFE_PP_/CK (DFF_X1) 0.00 1.29 clock reconvergence pessimism -0.03 1.26 library setup time 1.26 data required time ----------------------------------------------------------------------------- 1.26 data required time -1.38 data arrival time ----------------------------------------------------------------------------- -0.12 slack (VIOLATED) Startpoint: qnr.qnt_cnt[3]$_DFFE_PN0P_ (rising edge-triggered flip-flop clocked by clk) Endpoint: qnt_cnt[3] (output port clocked by vclk_clk) Path Group: vclk_clk Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock source latency 1 38.16 0.00 0.00 0.00 ^ clk (in) clk (net) 0.01 0.01 0.01 ^ clkbuf_0_clk/A (CLKBUF_X3) 4 46.34 0.04 0.06 0.07 ^ clkbuf_0_clk/Z (CLKBUF_X3) clknet_0_clk (net) 0.04 0.00 0.08 ^ clkbuf_2_2_0_clk/A (CLKBUF_X3) 16 82.02 0.06 0.10 0.18 ^ clkbuf_2_2_0_clk/Z (CLKBUF_X3) clknet_2_2_0_clk (net) 0.06 0.01 0.19 ^ clkbuf_6_46_0_clk/A (CLKBUF_X3) 17 39.49 0.03 0.08 0.26 ^ clkbuf_6_46_0_clk/Z (CLKBUF_X3) clknet_6_46_0_clk (net) 0.03 0.00 0.26 ^ clkbuf_leaf_492_clk/A (CLKBUF_X3) 7 10.79 0.01 0.05 0.31 ^ clkbuf_leaf_492_clk/Z (CLKBUF_X3) clknet_leaf_492_clk (net) 0.01 0.00 0.31 ^ qnr.qnt_cnt[3]$_DFFE_PN0P_/CK (DFFR_X1) 6 10.62 0.03 0.12 0.43 ^ qnr.qnt_cnt[3]$_DFFE_PN0P_/Q (DFFR_X1) net35 (net) 0.03 0.00 0.43 ^ output36/A (BUF_X1) 1 0.68 0.01 0.02 0.46 ^ output36/Z (BUF_X1) qnt_cnt[3] (net) 0.01 0.00 0.46 ^ qnt_cnt[3] (out) 0.46 data arrival time 0.00 1.00 1.00 clock vclk_clk (rise edge) 0.29 1.29 clock network delay (ideal) 0.00 1.29 clock reconvergence pessimism -0.20 1.09 output external delay 1.09 data required time ----------------------------------------------------------------------------- 1.09 data required time -0.46 data arrival time ----------------------------------------------------------------------------- 0.63 slack (MET) ========================================================================== finish report_check_types -max_slew -max_cap -max_fanout -violators -------------------------------------------------------------------------- ========================================================================== finish max_slew_check_slack -------------------------------------------------------------------------- 0.09316877275705338 ========================================================================== finish max_slew_check_limit -------------------------------------------------------------------------- 0.1985349953174591 ========================================================================== finish max_slew_check_slack_limit -------------------------------------------------------------------------- 0.4693 ========================================================================== finish max_fanout_check_slack -------------------------------------------------------------------------- 1.0000000150474662e+30 ========================================================================== finish max_fanout_check_limit -------------------------------------------------------------------------- 1.0000000150474662e+30 ========================================================================== finish max_capacitance_check_slack -------------------------------------------------------------------------- 3.6840476989746094 ========================================================================== finish max_capacitance_check_limit -------------------------------------------------------------------------- 16.021699905395508 ========================================================================== finish max_capacitance_check_slack_limit -------------------------------------------------------------------------- 0.2299 ========================================================================== finish max_slew_violation_count -------------------------------------------------------------------------- max slew violation count 0 ========================================================================== finish max_fanout_violation_count -------------------------------------------------------------------------- max fanout violation count 0 ========================================================================== finish max_cap_violation_count -------------------------------------------------------------------------- max cap violation count 0 ========================================================================== finish setup_violation_count -------------------------------------------------------------------------- setup violation count 664 ========================================================================== finish hold_violation_count -------------------------------------------------------------------------- hold violation count 0 ========================================================================== finish report_checks -path_delay max reg to reg -------------------------------------------------------------------------- Startpoint: fdct_zigzag.dct_mod.ddin[4]$_DFFE_PN0P_ (rising edge-triggered flip-flop clocked by clk) Endpoint: fdct_zigzag.dct_mod.dct_block_4.dct_unit_1.macu.mult_res[16]$_DFFE_PP_ (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock source latency 0.00 0.00 ^ clk (in) 0.07 0.07 ^ clkbuf_0_clk/Z (CLKBUF_X3) 0.10 0.17 ^ clkbuf_2_0_0_clk/Z (CLKBUF_X3) 0.07 0.25 ^ clkbuf_6_14_0_clk/Z (CLKBUF_X3) 0.05 0.30 ^ clkbuf_leaf_646_clk/Z (CLKBUF_X3) 0.00 0.30 ^ fdct_zigzag.dct_mod.ddin[4]$_DFFE_PN0P_/CK (DFFR_X2) 0.11 0.40 v fdct_zigzag.dct_mod.ddin[4]$_DFFE_PN0P_/Q (DFFR_X2) 0.03 0.43 v rebuffer12003/Z (BUF_X8) 0.03 0.46 v place11032/Z (BUF_X8) 0.04 0.50 v place11025/Z (BUF_X8) 0.06 0.56 v place11022/Z (BUF_X1) 0.02 0.58 ^ _066238_/ZN (NAND2_X1) 0.01 0.59 v _066239_/ZN (INV_X2) 0.03 0.63 v place9826/Z (BUF_X1) 0.03 0.66 v place9825/Z (BUF_X1) 0.09 0.75 v _111390_/CO (FA_X1) 0.12 0.87 ^ _111828_/S (FA_X1) 0.09 0.96 v _110463_/S (FA_X1) 0.13 1.09 ^ _110723_/S (FA_X1) 0.07 1.16 ^ _112636_/S (HA_X1) 0.03 1.19 v _092017_/ZN (NAND3_X1) 0.03 1.22 ^ _092018_/ZN (NAND2_X1) 0.02 1.24 v _092020_/ZN (AOI21_X2) 0.03 1.27 ^ _092022_/ZN (OAI21_X2) 0.01 1.28 v _092023_/ZN (INV_X1) 0.03 1.31 ^ _092025_/ZN (OAI21_X1) 0.03 1.34 ^ _092026_/ZN (OR2_X1) 0.02 1.36 v _092028_/ZN (NAND3_X1) 0.02 1.38 ^ _092030_/ZN (OAI21_X1) 0.00 1.38 ^ fdct_zigzag.dct_mod.dct_block_4.dct_unit_1.macu.mult_res[16]$_DFFE_PP_/D (DFF_X1) 1.38 data arrival time 1.00 1.00 clock clk (rise edge) 0.00 1.00 clock source latency 0.00 1.00 ^ clk (in) 0.07 1.07 ^ clkbuf_0_clk/Z (CLKBUF_X3) 0.10 1.17 ^ clkbuf_2_1_0_clk/Z (CLKBUF_X3) 0.07 1.25 ^ clkbuf_6_19_0_clk/Z (CLKBUF_X3) 0.05 1.29 ^ clkbuf_leaf_143_clk/Z (CLKBUF_X3) 0.00 1.29 ^ fdct_zigzag.dct_mod.dct_block_4.dct_unit_1.macu.mult_res[16]$_DFFE_PP_/CK (DFF_X1) 0.00 1.29 clock reconvergence pessimism -0.03 1.26 library setup time 1.26 data required time --------------------------------------------------------- 1.26 data required time -1.38 data arrival time --------------------------------------------------------- -0.12 slack (VIOLATED) ========================================================================== finish report_checks -path_delay min reg to reg -------------------------------------------------------------------------- Startpoint: dqnr_doe$_DFFE_PP_ (rising edge-triggered flip-flop clocked by clk) Endpoint: rle.ddstrb$_DFF_PN0_ (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock source latency 0.00 0.00 ^ clk (in) 0.07 0.07 ^ clkbuf_0_clk/Z (CLKBUF_X3) 0.11 0.18 ^ clkbuf_2_2_0_clk/Z (CLKBUF_X3) 0.08 0.26 ^ clkbuf_6_40_0_clk/Z (CLKBUF_X3) 0.04 0.31 ^ clkbuf_leaf_539_clk/Z (CLKBUF_X3) 0.00 0.31 ^ dqnr_doe$_DFFE_PP_/CK (DFF_X1) 0.09 0.39 v dqnr_doe$_DFFE_PP_/Q (DFF_X1) 0.00 0.39 v rle.ddstrb$_DFF_PN0_/D (DFFR_X1) 0.39 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock source latency 0.00 0.00 ^ clk (in) 0.07 0.07 ^ clkbuf_0_clk/Z (CLKBUF_X3) 0.11 0.18 ^ clkbuf_2_2_0_clk/Z (CLKBUF_X3) 0.08 0.26 ^ clkbuf_6_40_0_clk/Z (CLKBUF_X3) 0.04 0.31 ^ clkbuf_leaf_539_clk/Z (CLKBUF_X3) 0.00 0.31 ^ rle.ddstrb$_DFF_PN0_/CK (DFFR_X1) 0.00 0.31 clock reconvergence pessimism 0.00 0.31 library hold time 0.31 data required time --------------------------------------------------------- 0.31 data required time -0.39 data arrival time --------------------------------------------------------- 0.08 slack (MET) ========================================================================== finish critical path target clock latency max path -------------------------------------------------------------------------- 0.3061 ========================================================================== finish critical path target clock latency min path -------------------------------------------------------------------------- 0.3099 ========================================================================== finish critical path source clock latency min path -------------------------------------------------------------------------- 0.2900 ========================================================================== finish critical path delay -------------------------------------------------------------------------- 1.3784 ========================================================================== finish critical path slack -------------------------------------------------------------------------- -0.1182 ========================================================================== finish slack div critical path delay -------------------------------------------------------------------------- -8.575160 ========================================================================== finish report_power -------------------------------------------------------------------------- Group Internal Switching Leakage Total Power Power Power Power (Watts) ---------------------------------------------------------------- Sequential 5.46e-02 1.54e-02 3.47e-04 7.03e-02 12.0% Combinational 2.61e-01 2.34e-01 1.60e-03 4.96e-01 84.3% Clock 1.02e-02 1.15e-02 3.59e-05 2.18e-02 3.7% Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0% Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0% ---------------------------------------------------------------- Total 3.25e-01 2.61e-01 1.98e-03 5.88e-01 100.0% 55.3% 44.3% 0.3%