========================================================================== finish report_tns -------------------------------------------------------------------------- tns max 0.00 ========================================================================== finish report_wns -------------------------------------------------------------------------- wns max 0.00 ========================================================================== finish report_worst_slack -------------------------------------------------------------------------- worst slack max 0.01 ========================================================================== finish report_clock_min_period -------------------------------------------------------------------------- core_clock period_min = 2.19 fmax = 456.42 vclk_core_clock period_min = 1.88 fmax = 533.09 ========================================================================== finish report_clock_skew -------------------------------------------------------------------------- Clock core_clock 0.26 source latency gen_regfile_ff.register_file_i.rf_reg[865]$_DFFE_PN0P_/CK ^ -0.30 target latency if_stage_i.gen_prefetch_buffer.prefetch_buffer_i.fetch_addr_q[25]$_DFFE_PP_/CK ^ 0.00 CRPR -------------- -0.04 setup skew Clock vclk_core_clock No launch/capture paths found. ========================================================================== finish report_checks -path_delay min -------------------------------------------------------------------------- Startpoint: rst_ni (input port clocked by vclk_core_clock) Endpoint: gen_regfile_ff.register_file_i.rf_reg[144]$_DFFE_PN0P_ (removal check against rising-edge clock core_clock) Path Group: asynchronous Path Type: min Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 0.00 clock vclk_core_clock (rise edge) 0.28 0.28 clock network delay (ideal) 0.44 0.72 ^ input external delay 1 7.29 0.00 0.00 0.72 ^ rst_ni (in) rst_ni (net) 0.00 0.00 0.73 ^ input155/A (CLKBUF_X3) 18 77.01 0.05 0.06 0.79 ^ input155/Z (CLKBUF_X3) net154 (net) 0.07 0.04 0.83 ^ gen_regfile_ff.register_file_i.rf_reg[144]$_DFFE_PN0P_/RN (DFFR_X1) 0.83 data arrival time 0.00 0.00 clock core_clock (rise edge) 0.00 0.00 clock source latency 2 20.45 0.00 0.00 0.00 ^ clk_i (in) clk_i (net) 0.00 0.00 0.00 ^ delaybuf_0_core_clock/A (CLKBUF_X3) 1 4.23 0.01 0.03 0.03 ^ delaybuf_0_core_clock/Z (CLKBUF_X3) delaynet_0_core_clock (net) 0.01 0.00 0.03 ^ delaybuf_1_core_clock/A (CLKBUF_X3) 1 5.00 0.01 0.03 0.06 ^ delaybuf_1_core_clock/Z (CLKBUF_X3) delaynet_1_core_clock (net) 0.01 0.00 0.06 ^ clkbuf_regs_0_core_clock/A (CLKBUF_X3) 1 1.74 0.01 0.03 0.08 ^ clkbuf_regs_0_core_clock/Z (CLKBUF_X3) clk_i_regs (net) 0.01 0.00 0.08 ^ clkbuf_0_clk_i_regs/A (CLKBUF_X3) 16 62.73 0.05 0.08 0.16 ^ clkbuf_0_clk_i_regs/Z (CLKBUF_X3) clknet_0_clk_i_regs (net) 0.05 0.00 0.16 ^ clkbuf_4_7_0_clk_i_regs/A (CLKBUF_X3) 10 27.37 0.02 0.06 0.23 ^ clkbuf_4_7_0_clk_i_regs/Z (CLKBUF_X3) clknet_4_7_0_clk_i_regs (net) 0.02 0.00 0.23 ^ clkbuf_leaf_96_clk_i_regs/A (CLKBUF_X3) 8 10.86 0.01 0.04 0.27 ^ clkbuf_leaf_96_clk_i_regs/Z (CLKBUF_X3) clknet_leaf_96_clk_i_regs (net) 0.01 0.00 0.27 ^ gen_regfile_ff.register_file_i.rf_reg[144]$_DFFE_PN0P_/CK (DFFR_X1) 0.00 0.27 clock reconvergence pessimism 0.27 0.54 library removal time 0.54 data required time ----------------------------------------------------------------------------- 0.54 data required time -0.83 data arrival time ----------------------------------------------------------------------------- 0.29 slack (MET) Startpoint: core_clock_gate_i.en_latch$_DLATCH_N_ (negative level-sensitive latch clocked by core_clock) Endpoint: _27049_ (rising clock gating-check end-point clocked by core_clock) Path Group: gated clock Path Type: min Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 1.10 1.10 clock core_clock (fall edge) 0.00 1.10 clock source latency 2 20.11 0.00 0.00 1.10 v clk_i (in) clk_i (net) 0.00 0.00 1.10 v delaybuf_0_core_clock/A (CLKBUF_X3) 1 4.06 0.01 0.03 1.13 v delaybuf_0_core_clock/Z (CLKBUF_X3) delaynet_0_core_clock (net) 0.01 0.00 1.13 v delaybuf_1_core_clock/A (CLKBUF_X3) 1 4.83 0.01 0.03 1.16 v delaybuf_1_core_clock/Z (CLKBUF_X3) delaynet_1_core_clock (net) 0.01 0.00 1.16 v clkbuf_regs_0_core_clock/A (CLKBUF_X3) 1 1.56 0.01 0.03 1.19 v clkbuf_regs_0_core_clock/Z (CLKBUF_X3) clk_i_regs (net) 0.01 0.00 1.19 v clkbuf_0_clk_i_regs/A (CLKBUF_X3) 16 59.98 0.05 0.08 1.26 v clkbuf_0_clk_i_regs/Z (CLKBUF_X3) clknet_0_clk_i_regs (net) 0.05 0.00 1.27 v clkbuf_4_15_0_clk_i_regs/A (CLKBUF_X3) 12 26.44 0.02 0.07 1.34 v clkbuf_4_15_0_clk_i_regs/Z (CLKBUF_X3) clknet_4_15_0_clk_i_regs (net) 0.02 0.00 1.34 v clkbuf_leaf_73_clk_i_regs/A (CLKBUF_X3) 6 11.03 0.01 0.04 1.38 v clkbuf_leaf_73_clk_i_regs/Z (CLKBUF_X3) clknet_leaf_73_clk_i_regs (net) 0.01 0.00 1.38 v core_clock_gate_i.en_latch$_DLATCH_N_/GN (DLL_X1) 1 18.50 0.04 0.09 1.48 ^ core_clock_gate_i.en_latch$_DLATCH_N_/Q (DLL_X1) core_clock_gate_i.en_latch (net) 0.04 0.00 1.48 ^ _27049_/A1 (AND2_X1) 1.48 data arrival time 1.10 1.10 clock core_clock (fall edge) 0.00 1.10 clock source latency 2 20.11 0.00 0.00 1.10 v clk_i (in) clk_i (net) 0.00 0.00 1.10 v clkbuf_0_clk_i/A (CLKBUF_X3) 1 1.85 0.01 0.03 1.13 v clkbuf_0_clk_i/Z (CLKBUF_X3) clknet_0_clk_i (net) 0.01 0.00 1.13 v clkbuf_1_0__f_clk_i/A (CLKBUF_X3) 1 1.62 0.01 0.03 1.15 v clkbuf_1_0__f_clk_i/Z (CLKBUF_X3) clknet_1_0__leaf_clk_i (net) 0.01 0.00 1.15 v _27049_/A2 (AND2_X1) 0.00 1.15 clock reconvergence pessimism 0.00 1.15 clock gating hold time 1.15 data required time ----------------------------------------------------------------------------- 1.15 data required time -1.48 data arrival time ----------------------------------------------------------------------------- 0.33 slack (MET) Startpoint: id_stage_i.controller_i.ctrl_fsm_cs[0]$_DFF_PN1_ (rising edge-triggered flip-flop clocked by core_clock) Endpoint: id_stage_i.controller_i.ctrl_fsm_cs[5]$_DFF_PN0_ (rising edge-triggered flip-flop clocked by core_clock) Path Group: core_clock Path Type: min Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 clock core_clock (rise edge) 0.00 0.00 clock source latency 2 20.45 0.00 0.00 0.00 ^ clk_i (in) clk_i (net) 0.00 0.00 0.00 ^ clkbuf_0_clk_i/A (CLKBUF_X3) 1 2.02 0.01 0.02 0.03 ^ clkbuf_0_clk_i/Z (CLKBUF_X3) clknet_0_clk_i (net) 0.01 0.00 0.03 ^ clkbuf_1_0__f_clk_i/A (CLKBUF_X3) 1 1.70 0.01 0.03 0.05 ^ clkbuf_1_0__f_clk_i/Z (CLKBUF_X3) clknet_1_0__leaf_clk_i (net) 0.01 0.00 0.05 ^ _27049_/A2 (AND2_X1) 1 1.44 0.01 0.03 0.08 ^ _27049_/ZN (AND2_X1) clk (net) 0.01 0.00 0.08 ^ clkbuf_0_clk/A (CLKBUF_X3) 8 42.52 0.03 0.06 0.14 ^ clkbuf_0_clk/Z (CLKBUF_X3) clknet_0_clk (net) 0.03 0.01 0.15 ^ clkbuf_3_4_0_clk/A (CLKBUF_X3) 2 10.45 0.01 0.05 0.19 ^ clkbuf_3_4_0_clk/Z (CLKBUF_X3) clknet_3_4_0_clk (net) 0.01 0.00 0.19 ^ clkbuf_4_8__f_clk/A (CLKBUF_X3) 10 26.54 0.02 0.05 0.24 ^ clkbuf_4_8__f_clk/Z (CLKBUF_X3) clknet_4_8__leaf_clk (net) 0.02 0.00 0.24 ^ clkbuf_leaf_22_clk/A (CLKBUF_X3) 7 9.70 0.01 0.04 0.28 ^ clkbuf_leaf_22_clk/Z (CLKBUF_X3) clknet_leaf_22_clk (net) 0.01 0.00 0.28 ^ id_stage_i.controller_i.ctrl_fsm_cs[0]$_DFF_PN1_/CK (DFFS_X1) 3 4.03 0.01 0.09 0.37 v id_stage_i.controller_i.ctrl_fsm_cs[0]$_DFF_PN1_/Q (DFFS_X1) id_stage_i.controller_i.ctrl_fsm_cs[0] (net) 0.01 0.00 0.37 v id_stage_i.controller_i.ctrl_fsm_cs[5]$_DFF_PN0_/D (DFFR_X1) 0.37 data arrival time 0.00 0.00 clock core_clock (rise edge) 0.00 0.00 clock source latency 2 20.45 0.00 0.00 0.00 ^ clk_i (in) clk_i (net) 0.00 0.00 0.00 ^ clkbuf_0_clk_i/A (CLKBUF_X3) 1 2.02 0.01 0.02 0.03 ^ clkbuf_0_clk_i/Z (CLKBUF_X3) clknet_0_clk_i (net) 0.01 0.00 0.03 ^ clkbuf_1_0__f_clk_i/A (CLKBUF_X3) 1 1.70 0.01 0.03 0.05 ^ clkbuf_1_0__f_clk_i/Z (CLKBUF_X3) clknet_1_0__leaf_clk_i (net) 0.01 0.00 0.05 ^ _27049_/A2 (AND2_X1) 1 1.44 0.01 0.03 0.08 ^ _27049_/ZN (AND2_X1) clk (net) 0.01 0.00 0.08 ^ clkbuf_0_clk/A (CLKBUF_X3) 8 42.52 0.03 0.06 0.14 ^ clkbuf_0_clk/Z (CLKBUF_X3) clknet_0_clk (net) 0.03 0.01 0.15 ^ clkbuf_3_4_0_clk/A (CLKBUF_X3) 2 10.45 0.01 0.05 0.19 ^ clkbuf_3_4_0_clk/Z (CLKBUF_X3) clknet_3_4_0_clk (net) 0.01 0.00 0.19 ^ clkbuf_4_8__f_clk/A (CLKBUF_X3) 10 26.54 0.02 0.05 0.24 ^ clkbuf_4_8__f_clk/Z (CLKBUF_X3) clknet_4_8__leaf_clk (net) 0.02 0.00 0.24 ^ clkbuf_leaf_22_clk/A (CLKBUF_X3) 7 9.70 0.01 0.04 0.28 ^ clkbuf_leaf_22_clk/Z (CLKBUF_X3) clknet_leaf_22_clk (net) 0.01 0.00 0.28 ^ id_stage_i.controller_i.ctrl_fsm_cs[5]$_DFF_PN0_/CK (DFFR_X1) 0.00 0.28 clock reconvergence pessimism 0.00 0.29 library hold time 0.29 data required time ----------------------------------------------------------------------------- 0.29 data required time -0.37 data arrival time ----------------------------------------------------------------------------- 0.09 slack (MET) Startpoint: fetch_enable_q$_DFFE_PN0P_ (rising edge-triggered flip-flop clocked by core_clock) Endpoint: core_sleep_o (output port clocked by vclk_core_clock) Path Group: vclk_core_clock Path Type: min Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 clock core_clock (rise edge) 0.00 0.00 clock source latency 2 20.45 0.00 0.00 0.00 ^ clk_i (in) clk_i (net) 0.00 0.00 0.00 ^ delaybuf_0_core_clock/A (CLKBUF_X3) 1 4.23 0.01 0.03 0.03 ^ delaybuf_0_core_clock/Z (CLKBUF_X3) delaynet_0_core_clock (net) 0.01 0.00 0.03 ^ delaybuf_1_core_clock/A (CLKBUF_X3) 1 5.00 0.01 0.03 0.06 ^ delaybuf_1_core_clock/Z (CLKBUF_X3) delaynet_1_core_clock (net) 0.01 0.00 0.06 ^ clkbuf_regs_0_core_clock/A (CLKBUF_X3) 1 1.74 0.01 0.03 0.08 ^ clkbuf_regs_0_core_clock/Z (CLKBUF_X3) clk_i_regs (net) 0.01 0.00 0.08 ^ clkbuf_0_clk_i_regs/A (CLKBUF_X3) 16 62.73 0.05 0.08 0.16 ^ clkbuf_0_clk_i_regs/Z (CLKBUF_X3) clknet_0_clk_i_regs (net) 0.05 0.00 0.16 ^ clkbuf_4_15_0_clk_i_regs/A (CLKBUF_X3) 12 28.50 0.02 0.06 0.23 ^ clkbuf_4_15_0_clk_i_regs/Z (CLKBUF_X3) clknet_4_15_0_clk_i_regs (net) 0.02 0.00 0.23 ^ clkbuf_leaf_73_clk_i_regs/A (CLKBUF_X3) 6 11.81 0.01 0.04 0.27 ^ clkbuf_leaf_73_clk_i_regs/Z (CLKBUF_X3) clknet_leaf_73_clk_i_regs (net) 0.01 0.00 0.27 ^ fetch_enable_q$_DFFE_PN0P_/CK (DFFR_X1) 2 2.64 0.01 0.09 0.36 v fetch_enable_q$_DFFE_PN0P_/Q (DFFR_X1) fetch_enable_q (net) 0.01 0.00 0.36 v _27045_/A (OAI21_X1) 2 7.57 0.02 0.03 0.40 ^ _27045_/ZN (OAI21_X1) net156 (net) 0.02 0.00 0.40 ^ output157/A (BUF_X1) 1 0.23 0.00 0.02 0.42 ^ output157/Z (BUF_X1) core_sleep_o (net) 0.00 0.00 0.42 ^ core_sleep_o (out) 0.42 data arrival time 0.00 0.00 0.00 clock vclk_core_clock (rise edge) 0.28 0.28 clock network delay (ideal) 0.00 0.28 clock reconvergence pessimism -0.44 -0.15 output external delay -0.15 data required time ----------------------------------------------------------------------------- -0.15 data required time -0.42 data arrival time ----------------------------------------------------------------------------- 0.57 slack (MET) ========================================================================== finish report_checks -path_delay max -------------------------------------------------------------------------- Startpoint: rst_ni (input port clocked by vclk_core_clock) Endpoint: gen_regfile_ff.register_file_i.rf_reg[935]$_DFFE_PN0P_ (recovery check against rising-edge clock core_clock) Path Group: asynchronous Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 0.00 clock vclk_core_clock (rise edge) 0.28 0.28 clock network delay (ideal) 0.44 0.72 ^ input external delay 1 7.29 0.00 0.00 0.72 ^ rst_ni (in) rst_ni (net) 0.00 0.00 0.73 ^ input155/A (CLKBUF_X3) 18 77.01 0.05 0.06 0.79 ^ input155/Z (CLKBUF_X3) net154 (net) 0.07 0.04 0.83 ^ place2997/A (BUF_X2) 31 77.06 0.08 0.11 0.94 ^ place2997/Z (BUF_X2) net2996 (net) 0.09 0.02 0.96 ^ place2996/A (BUF_X2) 31 68.65 0.08 0.11 1.06 ^ place2996/Z (BUF_X2) net2995 (net) 0.08 0.00 1.07 ^ place2995/A (BUF_X2) 29 60.44 0.07 0.10 1.16 ^ place2995/Z (BUF_X2) net2994 (net) 0.07 0.01 1.17 ^ place2994/A (BUF_X1) 21 44.79 0.10 0.13 1.31 ^ place2994/Z (BUF_X1) net2993 (net) 0.10 0.00 1.31 ^ gen_regfile_ff.register_file_i.rf_reg[935]$_DFFE_PN0P_/RN (DFFR_X1) 1.31 data arrival time 2.20 2.20 clock core_clock (rise edge) 0.00 2.20 clock source latency 2 20.45 0.00 0.00 2.20 ^ clk_i (in) clk_i (net) 0.00 0.00 2.20 ^ delaybuf_0_core_clock/A (CLKBUF_X3) 1 4.23 0.01 0.03 2.23 ^ delaybuf_0_core_clock/Z (CLKBUF_X3) delaynet_0_core_clock (net) 0.01 0.00 2.23 ^ delaybuf_1_core_clock/A (CLKBUF_X3) 1 5.00 0.01 0.03 2.26 ^ delaybuf_1_core_clock/Z (CLKBUF_X3) delaynet_1_core_clock (net) 0.01 0.00 2.26 ^ clkbuf_regs_0_core_clock/A (CLKBUF_X3) 1 1.74 0.01 0.03 2.28 ^ clkbuf_regs_0_core_clock/Z (CLKBUF_X3) clk_i_regs (net) 0.01 0.00 2.28 ^ clkbuf_0_clk_i_regs/A (CLKBUF_X3) 16 62.73 0.05 0.08 2.36 ^ clkbuf_0_clk_i_regs/Z (CLKBUF_X3) clknet_0_clk_i_regs (net) 0.05 0.00 2.36 ^ clkbuf_4_8_0_clk_i_regs/A (CLKBUF_X3) 8 22.73 0.02 0.06 2.42 ^ clkbuf_4_8_0_clk_i_regs/Z (CLKBUF_X3) clknet_4_8_0_clk_i_regs (net) 0.02 0.00 2.42 ^ clkbuf_leaf_29_clk_i_regs/A (CLKBUF_X3) 8 9.94 0.01 0.04 2.46 ^ clkbuf_leaf_29_clk_i_regs/Z (CLKBUF_X3) clknet_leaf_29_clk_i_regs (net) 0.01 0.00 2.46 ^ gen_regfile_ff.register_file_i.rf_reg[935]$_DFFE_PN0P_/CK (DFFR_X1) 0.00 2.46 clock reconvergence pessimism 0.04 2.50 library recovery time 2.50 data required time ----------------------------------------------------------------------------- 2.50 data required time -1.31 data arrival time ----------------------------------------------------------------------------- 1.19 slack (MET) Startpoint: core_clock_gate_i.en_latch$_DLATCH_N_ (negative level-sensitive latch clocked by core_clock) Endpoint: _27049_ (rising clock gating-check end-point clocked by core_clock) Path Group: gated clock Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 1.10 1.10 clock core_clock (fall edge) 0.00 1.10 clock source latency 2 20.11 0.00 0.00 1.10 v clk_i (in) clk_i (net) 0.00 0.00 1.10 v delaybuf_0_core_clock/A (CLKBUF_X3) 1 4.06 0.01 0.03 1.13 v delaybuf_0_core_clock/Z (CLKBUF_X3) delaynet_0_core_clock (net) 0.01 0.00 1.13 v delaybuf_1_core_clock/A (CLKBUF_X3) 1 4.83 0.01 0.03 1.16 v delaybuf_1_core_clock/Z (CLKBUF_X3) delaynet_1_core_clock (net) 0.01 0.00 1.16 v clkbuf_regs_0_core_clock/A (CLKBUF_X3) 1 1.56 0.01 0.03 1.19 v clkbuf_regs_0_core_clock/Z (CLKBUF_X3) clk_i_regs (net) 0.01 0.00 1.19 v clkbuf_0_clk_i_regs/A (CLKBUF_X3) 16 59.98 0.05 0.08 1.26 v clkbuf_0_clk_i_regs/Z (CLKBUF_X3) clknet_0_clk_i_regs (net) 0.05 0.00 1.27 v clkbuf_4_15_0_clk_i_regs/A (CLKBUF_X3) 12 26.44 0.02 0.07 1.34 v clkbuf_4_15_0_clk_i_regs/Z (CLKBUF_X3) clknet_4_15_0_clk_i_regs (net) 0.02 0.00 1.34 v clkbuf_leaf_73_clk_i_regs/A (CLKBUF_X3) 6 11.03 0.01 0.04 1.38 v clkbuf_leaf_73_clk_i_regs/Z (CLKBUF_X3) clknet_leaf_73_clk_i_regs (net) 0.01 0.00 1.38 v core_clock_gate_i.en_latch$_DLATCH_N_/GN (DLL_X1) 1 18.46 0.03 0.10 1.49 v core_clock_gate_i.en_latch$_DLATCH_N_/Q (DLL_X1) core_clock_gate_i.en_latch (net) 0.03 0.00 1.49 v _27049_/A1 (AND2_X1) 1.49 data arrival time 2.20 2.20 clock core_clock (rise edge) 0.00 2.20 clock source latency 2 20.45 0.00 0.00 2.20 ^ clk_i (in) clk_i (net) 0.00 0.00 2.20 ^ clkbuf_0_clk_i/A (CLKBUF_X3) 1 2.02 0.01 0.02 2.23 ^ clkbuf_0_clk_i/Z (CLKBUF_X3) clknet_0_clk_i (net) 0.01 0.00 2.23 ^ clkbuf_1_0__f_clk_i/A (CLKBUF_X3) 1 1.70 0.01 0.03 2.25 ^ clkbuf_1_0__f_clk_i/Z (CLKBUF_X3) clknet_1_0__leaf_clk_i (net) 0.01 0.00 2.25 ^ _27049_/A2 (AND2_X1) 0.00 2.25 clock reconvergence pessimism 0.00 2.25 clock gating setup time 2.25 data required time ----------------------------------------------------------------------------- 2.25 data required time -1.49 data arrival time ----------------------------------------------------------------------------- 0.76 slack (MET) Startpoint: if_stage_i.instr_rdata_id_o[20]$_DFFE_PP_ (rising edge-triggered flip-flop clocked by core_clock) Endpoint: gen_regfile_ff.register_file_i.rf_reg[566]$_DFFE_PN0P_ (rising edge-triggered flip-flop clocked by core_clock) Path Group: core_clock Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 clock core_clock (rise edge) 0.00 0.00 clock source latency 2 20.45 0.00 0.00 0.00 ^ clk_i (in) clk_i (net) 0.00 0.00 0.00 ^ clkbuf_0_clk_i/A (CLKBUF_X3) 1 2.02 0.01 0.02 0.03 ^ clkbuf_0_clk_i/Z (CLKBUF_X3) clknet_0_clk_i (net) 0.01 0.00 0.03 ^ clkbuf_1_0__f_clk_i/A (CLKBUF_X3) 1 1.70 0.01 0.03 0.05 ^ clkbuf_1_0__f_clk_i/Z (CLKBUF_X3) clknet_1_0__leaf_clk_i (net) 0.01 0.00 0.05 ^ _27049_/A2 (AND2_X1) 1 1.44 0.01 0.03 0.08 ^ _27049_/ZN (AND2_X1) clk (net) 0.01 0.00 0.08 ^ clkbuf_0_clk/A (CLKBUF_X3) 8 42.52 0.03 0.06 0.14 ^ clkbuf_0_clk/Z (CLKBUF_X3) clknet_0_clk (net) 0.03 0.00 0.14 ^ clkbuf_3_3_0_clk/A (CLKBUF_X3) 2 11.17 0.01 0.05 0.19 ^ clkbuf_3_3_0_clk/Z (CLKBUF_X3) clknet_3_3_0_clk (net) 0.01 0.00 0.19 ^ clkbuf_4_6__f_clk/A (CLKBUF_X3) 7 19.11 0.02 0.04 0.24 ^ clkbuf_4_6__f_clk/Z (CLKBUF_X3) clknet_4_6__leaf_clk (net) 0.02 0.00 0.24 ^ clkbuf_leaf_2_clk/A (CLKBUF_X3) 8 10.45 0.01 0.04 0.28 ^ clkbuf_leaf_2_clk/Z (CLKBUF_X3) clknet_leaf_2_clk (net) 0.01 0.00 0.28 ^ if_stage_i.instr_rdata_id_o[20]$_DFFE_PP_/CK (DFF_X2) 5 41.48 0.05 0.15 0.43 ^ if_stage_i.instr_rdata_id_o[20]$_DFFE_PP_/Q (DFF_X2) gen_regfile_ff.register_file_i.raddr_b_i[0] (net) 0.05 0.00 0.43 ^ place2861/A (BUF_X16) 36 111.12 0.01 0.03 0.47 ^ place2861/Z (BUF_X16) net2860 (net) 0.04 0.03 0.50 ^ place2859/A (BUF_X2) 16 37.46 0.04 0.07 0.57 ^ place2859/Z (BUF_X2) net2858 (net) 0.04 0.00 0.57 ^ _15920_/S (MUX2_X1) 1 1.26 0.01 0.06 0.63 v _15920_/Z (MUX2_X1) _08909_ (net) 0.01 0.00 0.63 v _15922_/A (MUX2_X1) 1 1.14 0.01 0.06 0.69 v _15922_/Z (MUX2_X1) _08911_ (net) 0.01 0.00 0.69 v _15923_/B (MUX2_X1) 1 1.30 0.01 0.06 0.74 v _15923_/Z (MUX2_X1) _08912_ (net) 0.01 0.00 0.74 v _15924_/B (MUX2_X1) 1 6.77 0.02 0.07 0.81 v _15924_/Z (MUX2_X1) _08913_ (net) 0.02 0.00 0.81 v _15940_/A (MUX2_X1) 4 14.76 0.02 0.08 0.90 v _15940_/Z (MUX2_X1) _08929_ (net) 0.02 0.00 0.90 v _15942_/A (INV_X1) 2 3.99 0.01 0.02 0.93 ^ _15942_/ZN (INV_X1) _08931_ (net) 0.01 0.00 0.93 ^ _15943_/A2 (NOR2_X1) 1 1.80 0.01 0.01 0.94 v _15943_/ZN (NOR2_X1) _08932_ (net) 0.01 0.00 0.94 v _15978_/A (AOI21_X1) 1 4.75 0.04 0.06 0.99 ^ _15978_/ZN (AOI21_X1) _08967_ (net) 0.04 0.00 0.99 ^ place2445/A (BUF_X4) 5 18.39 0.01 0.03 1.02 ^ place2445/Z (BUF_X4) net2444 (net) 0.01 0.00 1.03 ^ _16719_/A1 (NOR2_X1) 1 3.52 0.01 0.01 1.04 v _16719_/ZN (NOR2_X1) _00314_ (net) 0.01 0.00 1.04 v _27596_/B (FA_X1) 1 3.82 0.02 0.12 1.16 ^ _27596_/S (FA_X1) _14511_ (net) 0.02 0.00 1.17 ^ _27475_/B (FA_X1) 1 4.14 0.02 0.10 1.26 v _27475_/S (FA_X1) _14513_ (net) 0.02 0.00 1.26 v _27654_/B (FA_X1) 1 4.93 0.02 0.13 1.39 ^ _27654_/S (FA_X1) _14748_ (net) 0.02 0.00 1.39 ^ _27580_/B (FA_X1) 1 4.72 0.02 0.10 1.49 v _27580_/S (FA_X1) _14552_ (net) 0.02 0.00 1.49 v _27489_/B (FA_X1) 1 3.81 0.02 0.13 1.62 ^ _27489_/S (FA_X1) _14555_ (net) 0.02 0.00 1.62 ^ _27616_/B (FA_X1) 1 4.30 0.02 0.10 1.72 v _27616_/S (FA_X1) _14839_ (net) 0.02 0.00 1.72 v _27792_/B (HA_X1) 3 4.45 0.01 0.06 1.79 v _27792_/S (HA_X1) _00473_ (net) 0.01 0.00 1.79 v _20244_/A (INV_X1) 2 3.24 0.01 0.02 1.80 ^ _20244_/ZN (INV_X1) _02879_ (net) 0.01 0.00 1.81 ^ _20246_/A1 (NOR2_X1) 1 1.73 0.01 0.01 1.81 v _20246_/ZN (NOR2_X1) _02881_ (net) 0.01 0.00 1.81 v _20247_/B2 (OAI21_X1) 2 5.20 0.03 0.05 1.86 ^ _20247_/ZN (OAI21_X1) _02882_ (net) 0.03 0.00 1.86 ^ _20255_/A (OAI21_X2) 3 6.84 0.01 0.03 1.89 v _20255_/ZN (OAI21_X2) _02890_ (net) 0.01 0.00 1.89 v _20256_/B2 (OAI21_X1) 2 5.17 0.03 0.05 1.94 ^ _20256_/ZN (OAI21_X1) _02891_ (net) 0.03 0.00 1.94 ^ place2188/A (BUF_X1) 2 3.65 0.01 0.03 1.98 ^ place2188/Z (BUF_X1) net2187 (net) 0.01 0.00 1.98 ^ _21033_/B1 (OAI21_X1) 1 2.51 0.01 0.02 1.99 v _21033_/ZN (OAI21_X1) _03660_ (net) 0.01 0.00 1.99 v _21034_/B (XNOR2_X1) 1 4.16 0.01 0.04 2.04 v _21034_/ZN (XNOR2_X1) _03661_ (net) 0.01 0.00 2.04 v _21035_/B (MUX2_X1) 2 2.11 0.01 0.06 2.10 v _21035_/Z (MUX2_X1) _03662_ (net) 0.01 0.00 2.10 v _21036_/A3 (OR3_X1) 1 1.68 0.01 0.08 2.18 v _21036_/ZN (OR3_X1) _03663_ (net) 0.01 0.00 2.18 v _21037_/A (OAI21_X1) 1 11.75 0.06 0.05 2.23 ^ _21037_/ZN (OAI21_X1) _03664_ (net) 0.06 0.00 2.23 ^ _21038_/B2 (OAI21_X1) 1 14.69 0.04 0.06 2.29 v _21038_/ZN (OAI21_X1) _03665_ (net) 0.04 0.00 2.29 v _21053_/B1 (AOI21_X2) 1 7.62 0.03 0.05 2.34 ^ _21053_/ZN (AOI21_X2) _03680_ (net) 0.03 0.00 2.34 ^ place2012/A (BUF_X8) 31 49.47 0.01 0.03 2.37 ^ place2012/Z (BUF_X8) net2011 (net) 0.02 0.01 2.39 ^ _23783_/A (MUX2_X1) 1 1.59 0.01 0.04 2.43 ^ _23783_/Z (MUX2_X1) _01279_ (net) 0.01 0.00 2.43 ^ gen_regfile_ff.register_file_i.rf_reg[566]$_DFFE_PN0P_/D (DFFR_X1) 2.43 data arrival time 2.20 2.20 clock core_clock (rise edge) 0.00 2.20 clock source latency 2 20.45 0.00 0.00 2.20 ^ clk_i (in) clk_i (net) 0.00 0.00 2.20 ^ delaybuf_0_core_clock/A (CLKBUF_X3) 1 4.23 0.01 0.03 2.23 ^ delaybuf_0_core_clock/Z (CLKBUF_X3) delaynet_0_core_clock (net) 0.01 0.00 2.23 ^ delaybuf_1_core_clock/A (CLKBUF_X3) 1 5.00 0.01 0.03 2.26 ^ delaybuf_1_core_clock/Z (CLKBUF_X3) delaynet_1_core_clock (net) 0.01 0.00 2.26 ^ clkbuf_regs_0_core_clock/A (CLKBUF_X3) 1 1.74 0.01 0.03 2.28 ^ clkbuf_regs_0_core_clock/Z (CLKBUF_X3) clk_i_regs (net) 0.01 0.00 2.28 ^ clkbuf_0_clk_i_regs/A (CLKBUF_X3) 16 62.73 0.05 0.08 2.36 ^ clkbuf_0_clk_i_regs/Z (CLKBUF_X3) clknet_0_clk_i_regs (net) 0.05 0.00 2.36 ^ clkbuf_4_12_0_clk_i_regs/A (CLKBUF_X3) 9 26.56 0.02 0.06 2.42 ^ clkbuf_4_12_0_clk_i_regs/Z (CLKBUF_X3) clknet_4_12_0_clk_i_regs (net) 0.02 0.00 2.43 ^ clkbuf_leaf_53_clk_i_regs/A (CLKBUF_X3) 8 10.97 0.01 0.04 2.47 ^ clkbuf_leaf_53_clk_i_regs/Z (CLKBUF_X3) clknet_leaf_53_clk_i_regs (net) 0.01 0.00 2.47 ^ gen_regfile_ff.register_file_i.rf_reg[566]$_DFFE_PN0P_/CK (DFFR_X1) 0.00 2.47 clock reconvergence pessimism -0.03 2.44 library setup time 2.44 data required time ----------------------------------------------------------------------------- 2.44 data required time -2.43 data arrival time ----------------------------------------------------------------------------- 0.01 slack (MET) Startpoint: if_stage_i.instr_rdata_id_o[20]$_DFFE_PP_ (rising edge-triggered flip-flop clocked by core_clock) Endpoint: instr_addr_o[31] (output port clocked by vclk_core_clock) Path Group: vclk_core_clock Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 clock core_clock (rise edge) 0.00 0.00 clock source latency 2 20.45 0.00 0.00 0.00 ^ clk_i (in) clk_i (net) 0.00 0.00 0.00 ^ clkbuf_0_clk_i/A (CLKBUF_X3) 1 2.02 0.01 0.02 0.03 ^ clkbuf_0_clk_i/Z (CLKBUF_X3) clknet_0_clk_i (net) 0.01 0.00 0.03 ^ clkbuf_1_0__f_clk_i/A (CLKBUF_X3) 1 1.70 0.01 0.03 0.05 ^ clkbuf_1_0__f_clk_i/Z (CLKBUF_X3) clknet_1_0__leaf_clk_i (net) 0.01 0.00 0.05 ^ _27049_/A2 (AND2_X1) 1 1.44 0.01 0.03 0.08 ^ _27049_/ZN (AND2_X1) clk (net) 0.01 0.00 0.08 ^ clkbuf_0_clk/A (CLKBUF_X3) 8 42.52 0.03 0.06 0.14 ^ clkbuf_0_clk/Z (CLKBUF_X3) clknet_0_clk (net) 0.03 0.00 0.14 ^ clkbuf_3_3_0_clk/A (CLKBUF_X3) 2 11.17 0.01 0.05 0.19 ^ clkbuf_3_3_0_clk/Z (CLKBUF_X3) clknet_3_3_0_clk (net) 0.01 0.00 0.19 ^ clkbuf_4_6__f_clk/A (CLKBUF_X3) 7 19.11 0.02 0.04 0.24 ^ clkbuf_4_6__f_clk/Z (CLKBUF_X3) clknet_4_6__leaf_clk (net) 0.02 0.00 0.24 ^ clkbuf_leaf_2_clk/A (CLKBUF_X3) 8 10.45 0.01 0.04 0.28 ^ clkbuf_leaf_2_clk/Z (CLKBUF_X3) clknet_leaf_2_clk (net) 0.01 0.00 0.28 ^ if_stage_i.instr_rdata_id_o[20]$_DFFE_PP_/CK (DFF_X2) 5 41.48 0.05 0.15 0.43 ^ if_stage_i.instr_rdata_id_o[20]$_DFFE_PP_/Q (DFF_X2) gen_regfile_ff.register_file_i.raddr_b_i[0] (net) 0.05 0.01 0.44 ^ place2868/A (BUF_X8) 28 72.45 0.02 0.04 0.48 ^ place2868/Z (BUF_X8) net2867 (net) 0.02 0.00 0.48 ^ place2863/A (BUF_X2) 15 36.00 0.04 0.06 0.54 ^ place2863/Z (BUF_X2) net2862 (net) 0.04 0.00 0.54 ^ place2862/A (BUF_X1) 4 8.95 0.02 0.05 0.59 ^ place2862/Z (BUF_X1) net2861 (net) 0.02 0.00 0.59 ^ _17145_/S (MUX2_X1) 1 1.08 0.01 0.06 0.65 v _17145_/Z (MUX2_X1) _10091_ (net) 0.01 0.00 0.65 v _17146_/B (MUX2_X1) 1 0.99 0.01 0.06 0.71 v _17146_/Z (MUX2_X1) _10092_ (net) 0.01 0.00 0.71 v _17147_/B (MUX2_X1) 1 2.19 0.01 0.06 0.77 v _17147_/Z (MUX2_X1) _10093_ (net) 0.01 0.00 0.77 v _17155_/A (MUX2_X1) 1 3.00 0.01 0.06 0.83 v _17155_/Z (MUX2_X1) _10101_ (net) 0.01 0.00 0.83 v _17171_/A (MUX2_X1) 2 15.88 0.02 0.08 0.91 v _17171_/Z (MUX2_X1) _10117_ (net) 0.02 0.00 0.91 v place2613/A (BUF_X1) 7 32.36 0.03 0.07 0.99 v place2613/Z (BUF_X1) net2612 (net) 0.03 0.00 0.99 v _17421_/B1 (AOI21_X1) 4 14.95 0.08 0.10 1.09 ^ _17421_/ZN (AOI21_X1) ex_block_i.alu_i.operand_b_neg[26] (net) 0.08 0.00 1.10 ^ _19695_/A1 (NAND2_X1) 1 1.63 0.02 0.02 1.11 v _19695_/ZN (NAND2_X1) _12179_ (net) 0.02 0.00 1.11 v _19699_/A (OAI221_X1) 1 6.92 0.06 0.04 1.15 ^ _19699_/ZN (OAI221_X1) ex_block_i.alu_i.adder_in_b[26] (net) 0.06 0.00 1.16 ^ _27683_/B (HA_X1) 7 13.53 0.07 0.11 1.27 ^ _27683_/S (HA_X1) _00355_ (net) 0.07 0.00 1.27 ^ _18226_/A3 (AND4_X1) 2 3.03 0.02 0.07 1.34 ^ _18226_/ZN (AND4_X1) _11049_ (net) 0.02 0.00 1.34 ^ _18227_/A2 (AND2_X1) 3 6.05 0.02 0.04 1.39 ^ _18227_/ZN (AND2_X1) _11050_ (net) 0.02 0.00 1.39 ^ _18228_/A2 (AND2_X1) 3 5.68 0.02 0.04 1.43 ^ _18228_/ZN (AND2_X1) _11051_ (net) 0.02 0.00 1.43 ^ _18264_/A3 (NAND3_X1) 1 1.55 0.02 0.02 1.46 v _18264_/ZN (NAND3_X1) _11087_ (net) 0.02 0.00 1.46 v _18275_/A1 (AND3_X1) 2 2.82 0.01 0.04 1.49 v _18275_/ZN (AND3_X1) _11098_ (net) 0.01 0.00 1.49 v _18276_/B2 (AOI21_X1) 3 9.29 0.06 0.07 1.56 ^ _18276_/ZN (AOI21_X1) _11099_ (net) 0.06 0.00 1.56 ^ _18277_/B2 (OAI21_X1) 4 6.86 0.03 0.04 1.61 v _18277_/ZN (OAI21_X1) _11100_ (net) 0.03 0.00 1.61 v _18348_/A1 (AND2_X1) 2 5.37 0.01 0.04 1.65 v _18348_/ZN (AND2_X1) _11169_ (net) 0.01 0.00 1.65 v _18349_/A3 (NOR3_X2) 3 8.80 0.05 0.07 1.72 ^ _18349_/ZN (NOR3_X2) _11170_ (net) 0.05 0.00 1.72 ^ _18350_/A2 (NOR2_X2) 2 15.12 0.02 0.03 1.75 v _18350_/ZN (NOR2_X2) net179 (net) 0.02 0.00 1.75 v _26998_/B2 (AOI221_X1) 1 4.81 0.06 0.11 1.86 ^ _26998_/ZN (AOI221_X1) _07782_ (net) 0.06 0.00 1.86 ^ _27000_/A1 (NOR2_X1) 3 12.16 0.02 0.04 1.89 v _27000_/ZN (NOR2_X1) _07784_ (net) 0.02 0.00 1.90 v _27001_/A (AOI21_X1) 2 5.84 0.04 0.07 1.96 ^ _27001_/ZN (AOI21_X1) _07785_ (net) 0.04 0.00 1.96 ^ _27217_/B1 (AOI21_X1) 2 3.17 0.02 0.03 1.99 v _27217_/ZN (AOI21_X1) net247 (net) 0.02 0.00 1.99 v output248/A (BUF_X1) 1 0.18 0.00 0.03 2.02 v output248/Z (BUF_X1) instr_addr_o[31] (net) 0.00 0.00 2.02 v instr_addr_o[31] (out) 2.02 data arrival time 0.00 2.20 2.20 clock vclk_core_clock (rise edge) 0.28 2.49 clock network delay (ideal) 0.00 2.49 clock reconvergence pessimism -0.44 2.05 output external delay 2.05 data required time ----------------------------------------------------------------------------- 2.05 data required time -2.02 data arrival time ----------------------------------------------------------------------------- 0.03 slack (MET) ========================================================================== finish report_checks -unconstrained -------------------------------------------------------------------------- Startpoint: rst_ni (input port clocked by vclk_core_clock) Endpoint: gen_regfile_ff.register_file_i.rf_reg[935]$_DFFE_PN0P_ (recovery check against rising-edge clock core_clock) Path Group: asynchronous Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 0.00 clock vclk_core_clock (rise edge) 0.28 0.28 clock network delay (ideal) 0.44 0.72 ^ input external delay 1 7.29 0.00 0.00 0.72 ^ rst_ni (in) rst_ni (net) 0.00 0.00 0.73 ^ input155/A (CLKBUF_X3) 18 77.01 0.05 0.06 0.79 ^ input155/Z (CLKBUF_X3) net154 (net) 0.07 0.04 0.83 ^ place2997/A (BUF_X2) 31 77.06 0.08 0.11 0.94 ^ place2997/Z (BUF_X2) net2996 (net) 0.09 0.02 0.96 ^ place2996/A (BUF_X2) 31 68.65 0.08 0.11 1.06 ^ place2996/Z (BUF_X2) net2995 (net) 0.08 0.00 1.07 ^ place2995/A (BUF_X2) 29 60.44 0.07 0.10 1.16 ^ place2995/Z (BUF_X2) net2994 (net) 0.07 0.01 1.17 ^ place2994/A (BUF_X1) 21 44.79 0.10 0.13 1.31 ^ place2994/Z (BUF_X1) net2993 (net) 0.10 0.00 1.31 ^ gen_regfile_ff.register_file_i.rf_reg[935]$_DFFE_PN0P_/RN (DFFR_X1) 1.31 data arrival time 2.20 2.20 clock core_clock (rise edge) 0.00 2.20 clock source latency 2 20.45 0.00 0.00 2.20 ^ clk_i (in) clk_i (net) 0.00 0.00 2.20 ^ delaybuf_0_core_clock/A (CLKBUF_X3) 1 4.23 0.01 0.03 2.23 ^ delaybuf_0_core_clock/Z (CLKBUF_X3) delaynet_0_core_clock (net) 0.01 0.00 2.23 ^ delaybuf_1_core_clock/A (CLKBUF_X3) 1 5.00 0.01 0.03 2.26 ^ delaybuf_1_core_clock/Z (CLKBUF_X3) delaynet_1_core_clock (net) 0.01 0.00 2.26 ^ clkbuf_regs_0_core_clock/A (CLKBUF_X3) 1 1.74 0.01 0.03 2.28 ^ clkbuf_regs_0_core_clock/Z (CLKBUF_X3) clk_i_regs (net) 0.01 0.00 2.28 ^ clkbuf_0_clk_i_regs/A (CLKBUF_X3) 16 62.73 0.05 0.08 2.36 ^ clkbuf_0_clk_i_regs/Z (CLKBUF_X3) clknet_0_clk_i_regs (net) 0.05 0.00 2.36 ^ clkbuf_4_8_0_clk_i_regs/A (CLKBUF_X3) 8 22.73 0.02 0.06 2.42 ^ clkbuf_4_8_0_clk_i_regs/Z (CLKBUF_X3) clknet_4_8_0_clk_i_regs (net) 0.02 0.00 2.42 ^ clkbuf_leaf_29_clk_i_regs/A (CLKBUF_X3) 8 9.94 0.01 0.04 2.46 ^ clkbuf_leaf_29_clk_i_regs/Z (CLKBUF_X3) clknet_leaf_29_clk_i_regs (net) 0.01 0.00 2.46 ^ gen_regfile_ff.register_file_i.rf_reg[935]$_DFFE_PN0P_/CK (DFFR_X1) 0.00 2.46 clock reconvergence pessimism 0.04 2.50 library recovery time 2.50 data required time ----------------------------------------------------------------------------- 2.50 data required time -1.31 data arrival time ----------------------------------------------------------------------------- 1.19 slack (MET) Startpoint: core_clock_gate_i.en_latch$_DLATCH_N_ (negative level-sensitive latch clocked by core_clock) Endpoint: _27049_ (rising clock gating-check end-point clocked by core_clock) Path Group: gated clock Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 1.10 1.10 clock core_clock (fall edge) 0.00 1.10 clock source latency 2 20.11 0.00 0.00 1.10 v clk_i (in) clk_i (net) 0.00 0.00 1.10 v delaybuf_0_core_clock/A (CLKBUF_X3) 1 4.06 0.01 0.03 1.13 v delaybuf_0_core_clock/Z (CLKBUF_X3) delaynet_0_core_clock (net) 0.01 0.00 1.13 v delaybuf_1_core_clock/A (CLKBUF_X3) 1 4.83 0.01 0.03 1.16 v delaybuf_1_core_clock/Z (CLKBUF_X3) delaynet_1_core_clock (net) 0.01 0.00 1.16 v clkbuf_regs_0_core_clock/A (CLKBUF_X3) 1 1.56 0.01 0.03 1.19 v clkbuf_regs_0_core_clock/Z (CLKBUF_X3) clk_i_regs (net) 0.01 0.00 1.19 v clkbuf_0_clk_i_regs/A (CLKBUF_X3) 16 59.98 0.05 0.08 1.26 v clkbuf_0_clk_i_regs/Z (CLKBUF_X3) clknet_0_clk_i_regs (net) 0.05 0.00 1.27 v clkbuf_4_15_0_clk_i_regs/A (CLKBUF_X3) 12 26.44 0.02 0.07 1.34 v clkbuf_4_15_0_clk_i_regs/Z (CLKBUF_X3) clknet_4_15_0_clk_i_regs (net) 0.02 0.00 1.34 v clkbuf_leaf_73_clk_i_regs/A (CLKBUF_X3) 6 11.03 0.01 0.04 1.38 v clkbuf_leaf_73_clk_i_regs/Z (CLKBUF_X3) clknet_leaf_73_clk_i_regs (net) 0.01 0.00 1.38 v core_clock_gate_i.en_latch$_DLATCH_N_/GN (DLL_X1) 1 18.46 0.03 0.10 1.49 v core_clock_gate_i.en_latch$_DLATCH_N_/Q (DLL_X1) core_clock_gate_i.en_latch (net) 0.03 0.00 1.49 v _27049_/A1 (AND2_X1) 1.49 data arrival time 2.20 2.20 clock core_clock (rise edge) 0.00 2.20 clock source latency 2 20.45 0.00 0.00 2.20 ^ clk_i (in) clk_i (net) 0.00 0.00 2.20 ^ clkbuf_0_clk_i/A (CLKBUF_X3) 1 2.02 0.01 0.02 2.23 ^ clkbuf_0_clk_i/Z (CLKBUF_X3) clknet_0_clk_i (net) 0.01 0.00 2.23 ^ clkbuf_1_0__f_clk_i/A (CLKBUF_X3) 1 1.70 0.01 0.03 2.25 ^ clkbuf_1_0__f_clk_i/Z (CLKBUF_X3) clknet_1_0__leaf_clk_i (net) 0.01 0.00 2.25 ^ _27049_/A2 (AND2_X1) 0.00 2.25 clock reconvergence pessimism 0.00 2.25 clock gating setup time 2.25 data required time ----------------------------------------------------------------------------- 2.25 data required time -1.49 data arrival time ----------------------------------------------------------------------------- 0.76 slack (MET) Startpoint: if_stage_i.instr_rdata_id_o[20]$_DFFE_PP_ (rising edge-triggered flip-flop clocked by core_clock) Endpoint: gen_regfile_ff.register_file_i.rf_reg[566]$_DFFE_PN0P_ (rising edge-triggered flip-flop clocked by core_clock) Path Group: core_clock Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 clock core_clock (rise edge) 0.00 0.00 clock source latency 2 20.45 0.00 0.00 0.00 ^ clk_i (in) clk_i (net) 0.00 0.00 0.00 ^ clkbuf_0_clk_i/A (CLKBUF_X3) 1 2.02 0.01 0.02 0.03 ^ clkbuf_0_clk_i/Z (CLKBUF_X3) clknet_0_clk_i (net) 0.01 0.00 0.03 ^ clkbuf_1_0__f_clk_i/A (CLKBUF_X3) 1 1.70 0.01 0.03 0.05 ^ clkbuf_1_0__f_clk_i/Z (CLKBUF_X3) clknet_1_0__leaf_clk_i (net) 0.01 0.00 0.05 ^ _27049_/A2 (AND2_X1) 1 1.44 0.01 0.03 0.08 ^ _27049_/ZN (AND2_X1) clk (net) 0.01 0.00 0.08 ^ clkbuf_0_clk/A (CLKBUF_X3) 8 42.52 0.03 0.06 0.14 ^ clkbuf_0_clk/Z (CLKBUF_X3) clknet_0_clk (net) 0.03 0.00 0.14 ^ clkbuf_3_3_0_clk/A (CLKBUF_X3) 2 11.17 0.01 0.05 0.19 ^ clkbuf_3_3_0_clk/Z (CLKBUF_X3) clknet_3_3_0_clk (net) 0.01 0.00 0.19 ^ clkbuf_4_6__f_clk/A (CLKBUF_X3) 7 19.11 0.02 0.04 0.24 ^ clkbuf_4_6__f_clk/Z (CLKBUF_X3) clknet_4_6__leaf_clk (net) 0.02 0.00 0.24 ^ clkbuf_leaf_2_clk/A (CLKBUF_X3) 8 10.45 0.01 0.04 0.28 ^ clkbuf_leaf_2_clk/Z (CLKBUF_X3) clknet_leaf_2_clk (net) 0.01 0.00 0.28 ^ if_stage_i.instr_rdata_id_o[20]$_DFFE_PP_/CK (DFF_X2) 5 41.48 0.05 0.15 0.43 ^ if_stage_i.instr_rdata_id_o[20]$_DFFE_PP_/Q (DFF_X2) gen_regfile_ff.register_file_i.raddr_b_i[0] (net) 0.05 0.00 0.43 ^ place2861/A (BUF_X16) 36 111.12 0.01 0.03 0.47 ^ place2861/Z (BUF_X16) net2860 (net) 0.04 0.03 0.50 ^ place2859/A (BUF_X2) 16 37.46 0.04 0.07 0.57 ^ place2859/Z (BUF_X2) net2858 (net) 0.04 0.00 0.57 ^ _15920_/S (MUX2_X1) 1 1.26 0.01 0.06 0.63 v _15920_/Z (MUX2_X1) _08909_ (net) 0.01 0.00 0.63 v _15922_/A (MUX2_X1) 1 1.14 0.01 0.06 0.69 v _15922_/Z (MUX2_X1) _08911_ (net) 0.01 0.00 0.69 v _15923_/B (MUX2_X1) 1 1.30 0.01 0.06 0.74 v _15923_/Z (MUX2_X1) _08912_ (net) 0.01 0.00 0.74 v _15924_/B (MUX2_X1) 1 6.77 0.02 0.07 0.81 v _15924_/Z (MUX2_X1) _08913_ (net) 0.02 0.00 0.81 v _15940_/A (MUX2_X1) 4 14.76 0.02 0.08 0.90 v _15940_/Z (MUX2_X1) _08929_ (net) 0.02 0.00 0.90 v _15942_/A (INV_X1) 2 3.99 0.01 0.02 0.93 ^ _15942_/ZN (INV_X1) _08931_ (net) 0.01 0.00 0.93 ^ _15943_/A2 (NOR2_X1) 1 1.80 0.01 0.01 0.94 v _15943_/ZN (NOR2_X1) _08932_ (net) 0.01 0.00 0.94 v _15978_/A (AOI21_X1) 1 4.75 0.04 0.06 0.99 ^ _15978_/ZN (AOI21_X1) _08967_ (net) 0.04 0.00 0.99 ^ place2445/A (BUF_X4) 5 18.39 0.01 0.03 1.02 ^ place2445/Z (BUF_X4) net2444 (net) 0.01 0.00 1.03 ^ _16719_/A1 (NOR2_X1) 1 3.52 0.01 0.01 1.04 v _16719_/ZN (NOR2_X1) _00314_ (net) 0.01 0.00 1.04 v _27596_/B (FA_X1) 1 3.82 0.02 0.12 1.16 ^ _27596_/S (FA_X1) _14511_ (net) 0.02 0.00 1.17 ^ _27475_/B (FA_X1) 1 4.14 0.02 0.10 1.26 v _27475_/S (FA_X1) _14513_ (net) 0.02 0.00 1.26 v _27654_/B (FA_X1) 1 4.93 0.02 0.13 1.39 ^ _27654_/S (FA_X1) _14748_ (net) 0.02 0.00 1.39 ^ _27580_/B (FA_X1) 1 4.72 0.02 0.10 1.49 v _27580_/S (FA_X1) _14552_ (net) 0.02 0.00 1.49 v _27489_/B (FA_X1) 1 3.81 0.02 0.13 1.62 ^ _27489_/S (FA_X1) _14555_ (net) 0.02 0.00 1.62 ^ _27616_/B (FA_X1) 1 4.30 0.02 0.10 1.72 v _27616_/S (FA_X1) _14839_ (net) 0.02 0.00 1.72 v _27792_/B (HA_X1) 3 4.45 0.01 0.06 1.79 v _27792_/S (HA_X1) _00473_ (net) 0.01 0.00 1.79 v _20244_/A (INV_X1) 2 3.24 0.01 0.02 1.80 ^ _20244_/ZN (INV_X1) _02879_ (net) 0.01 0.00 1.81 ^ _20246_/A1 (NOR2_X1) 1 1.73 0.01 0.01 1.81 v _20246_/ZN (NOR2_X1) _02881_ (net) 0.01 0.00 1.81 v _20247_/B2 (OAI21_X1) 2 5.20 0.03 0.05 1.86 ^ _20247_/ZN (OAI21_X1) _02882_ (net) 0.03 0.00 1.86 ^ _20255_/A (OAI21_X2) 3 6.84 0.01 0.03 1.89 v _20255_/ZN (OAI21_X2) _02890_ (net) 0.01 0.00 1.89 v _20256_/B2 (OAI21_X1) 2 5.17 0.03 0.05 1.94 ^ _20256_/ZN (OAI21_X1) _02891_ (net) 0.03 0.00 1.94 ^ place2188/A (BUF_X1) 2 3.65 0.01 0.03 1.98 ^ place2188/Z (BUF_X1) net2187 (net) 0.01 0.00 1.98 ^ _21033_/B1 (OAI21_X1) 1 2.51 0.01 0.02 1.99 v _21033_/ZN (OAI21_X1) _03660_ (net) 0.01 0.00 1.99 v _21034_/B (XNOR2_X1) 1 4.16 0.01 0.04 2.04 v _21034_/ZN (XNOR2_X1) _03661_ (net) 0.01 0.00 2.04 v _21035_/B (MUX2_X1) 2 2.11 0.01 0.06 2.10 v _21035_/Z (MUX2_X1) _03662_ (net) 0.01 0.00 2.10 v _21036_/A3 (OR3_X1) 1 1.68 0.01 0.08 2.18 v _21036_/ZN (OR3_X1) _03663_ (net) 0.01 0.00 2.18 v _21037_/A (OAI21_X1) 1 11.75 0.06 0.05 2.23 ^ _21037_/ZN (OAI21_X1) _03664_ (net) 0.06 0.00 2.23 ^ _21038_/B2 (OAI21_X1) 1 14.69 0.04 0.06 2.29 v _21038_/ZN (OAI21_X1) _03665_ (net) 0.04 0.00 2.29 v _21053_/B1 (AOI21_X2) 1 7.62 0.03 0.05 2.34 ^ _21053_/ZN (AOI21_X2) _03680_ (net) 0.03 0.00 2.34 ^ place2012/A (BUF_X8) 31 49.47 0.01 0.03 2.37 ^ place2012/Z (BUF_X8) net2011 (net) 0.02 0.01 2.39 ^ _23783_/A (MUX2_X1) 1 1.59 0.01 0.04 2.43 ^ _23783_/Z (MUX2_X1) _01279_ (net) 0.01 0.00 2.43 ^ gen_regfile_ff.register_file_i.rf_reg[566]$_DFFE_PN0P_/D (DFFR_X1) 2.43 data arrival time 2.20 2.20 clock core_clock (rise edge) 0.00 2.20 clock source latency 2 20.45 0.00 0.00 2.20 ^ clk_i (in) clk_i (net) 0.00 0.00 2.20 ^ delaybuf_0_core_clock/A (CLKBUF_X3) 1 4.23 0.01 0.03 2.23 ^ delaybuf_0_core_clock/Z (CLKBUF_X3) delaynet_0_core_clock (net) 0.01 0.00 2.23 ^ delaybuf_1_core_clock/A (CLKBUF_X3) 1 5.00 0.01 0.03 2.26 ^ delaybuf_1_core_clock/Z (CLKBUF_X3) delaynet_1_core_clock (net) 0.01 0.00 2.26 ^ clkbuf_regs_0_core_clock/A (CLKBUF_X3) 1 1.74 0.01 0.03 2.28 ^ clkbuf_regs_0_core_clock/Z (CLKBUF_X3) clk_i_regs (net) 0.01 0.00 2.28 ^ clkbuf_0_clk_i_regs/A (CLKBUF_X3) 16 62.73 0.05 0.08 2.36 ^ clkbuf_0_clk_i_regs/Z (CLKBUF_X3) clknet_0_clk_i_regs (net) 0.05 0.00 2.36 ^ clkbuf_4_12_0_clk_i_regs/A (CLKBUF_X3) 9 26.56 0.02 0.06 2.42 ^ clkbuf_4_12_0_clk_i_regs/Z (CLKBUF_X3) clknet_4_12_0_clk_i_regs (net) 0.02 0.00 2.43 ^ clkbuf_leaf_53_clk_i_regs/A (CLKBUF_X3) 8 10.97 0.01 0.04 2.47 ^ clkbuf_leaf_53_clk_i_regs/Z (CLKBUF_X3) clknet_leaf_53_clk_i_regs (net) 0.01 0.00 2.47 ^ gen_regfile_ff.register_file_i.rf_reg[566]$_DFFE_PN0P_/CK (DFFR_X1) 0.00 2.47 clock reconvergence pessimism -0.03 2.44 library setup time 2.44 data required time ----------------------------------------------------------------------------- 2.44 data required time -2.43 data arrival time ----------------------------------------------------------------------------- 0.01 slack (MET) Startpoint: if_stage_i.instr_rdata_id_o[20]$_DFFE_PP_ (rising edge-triggered flip-flop clocked by core_clock) Endpoint: instr_addr_o[31] (output port clocked by vclk_core_clock) Path Group: vclk_core_clock Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 clock core_clock (rise edge) 0.00 0.00 clock source latency 2 20.45 0.00 0.00 0.00 ^ clk_i (in) clk_i (net) 0.00 0.00 0.00 ^ clkbuf_0_clk_i/A (CLKBUF_X3) 1 2.02 0.01 0.02 0.03 ^ clkbuf_0_clk_i/Z (CLKBUF_X3) clknet_0_clk_i (net) 0.01 0.00 0.03 ^ clkbuf_1_0__f_clk_i/A (CLKBUF_X3) 1 1.70 0.01 0.03 0.05 ^ clkbuf_1_0__f_clk_i/Z (CLKBUF_X3) clknet_1_0__leaf_clk_i (net) 0.01 0.00 0.05 ^ _27049_/A2 (AND2_X1) 1 1.44 0.01 0.03 0.08 ^ _27049_/ZN (AND2_X1) clk (net) 0.01 0.00 0.08 ^ clkbuf_0_clk/A (CLKBUF_X3) 8 42.52 0.03 0.06 0.14 ^ clkbuf_0_clk/Z (CLKBUF_X3) clknet_0_clk (net) 0.03 0.00 0.14 ^ clkbuf_3_3_0_clk/A (CLKBUF_X3) 2 11.17 0.01 0.05 0.19 ^ clkbuf_3_3_0_clk/Z (CLKBUF_X3) clknet_3_3_0_clk (net) 0.01 0.00 0.19 ^ clkbuf_4_6__f_clk/A (CLKBUF_X3) 7 19.11 0.02 0.04 0.24 ^ clkbuf_4_6__f_clk/Z (CLKBUF_X3) clknet_4_6__leaf_clk (net) 0.02 0.00 0.24 ^ clkbuf_leaf_2_clk/A (CLKBUF_X3) 8 10.45 0.01 0.04 0.28 ^ clkbuf_leaf_2_clk/Z (CLKBUF_X3) clknet_leaf_2_clk (net) 0.01 0.00 0.28 ^ if_stage_i.instr_rdata_id_o[20]$_DFFE_PP_/CK (DFF_X2) 5 41.48 0.05 0.15 0.43 ^ if_stage_i.instr_rdata_id_o[20]$_DFFE_PP_/Q (DFF_X2) gen_regfile_ff.register_file_i.raddr_b_i[0] (net) 0.05 0.01 0.44 ^ place2868/A (BUF_X8) 28 72.45 0.02 0.04 0.48 ^ place2868/Z (BUF_X8) net2867 (net) 0.02 0.00 0.48 ^ place2863/A (BUF_X2) 15 36.00 0.04 0.06 0.54 ^ place2863/Z (BUF_X2) net2862 (net) 0.04 0.00 0.54 ^ place2862/A (BUF_X1) 4 8.95 0.02 0.05 0.59 ^ place2862/Z (BUF_X1) net2861 (net) 0.02 0.00 0.59 ^ _17145_/S (MUX2_X1) 1 1.08 0.01 0.06 0.65 v _17145_/Z (MUX2_X1) _10091_ (net) 0.01 0.00 0.65 v _17146_/B (MUX2_X1) 1 0.99 0.01 0.06 0.71 v _17146_/Z (MUX2_X1) _10092_ (net) 0.01 0.00 0.71 v _17147_/B (MUX2_X1) 1 2.19 0.01 0.06 0.77 v _17147_/Z (MUX2_X1) _10093_ (net) 0.01 0.00 0.77 v _17155_/A (MUX2_X1) 1 3.00 0.01 0.06 0.83 v _17155_/Z (MUX2_X1) _10101_ (net) 0.01 0.00 0.83 v _17171_/A (MUX2_X1) 2 15.88 0.02 0.08 0.91 v _17171_/Z (MUX2_X1) _10117_ (net) 0.02 0.00 0.91 v place2613/A (BUF_X1) 7 32.36 0.03 0.07 0.99 v place2613/Z (BUF_X1) net2612 (net) 0.03 0.00 0.99 v _17421_/B1 (AOI21_X1) 4 14.95 0.08 0.10 1.09 ^ _17421_/ZN (AOI21_X1) ex_block_i.alu_i.operand_b_neg[26] (net) 0.08 0.00 1.10 ^ _19695_/A1 (NAND2_X1) 1 1.63 0.02 0.02 1.11 v _19695_/ZN (NAND2_X1) _12179_ (net) 0.02 0.00 1.11 v _19699_/A (OAI221_X1) 1 6.92 0.06 0.04 1.15 ^ _19699_/ZN (OAI221_X1) ex_block_i.alu_i.adder_in_b[26] (net) 0.06 0.00 1.16 ^ _27683_/B (HA_X1) 7 13.53 0.07 0.11 1.27 ^ _27683_/S (HA_X1) _00355_ (net) 0.07 0.00 1.27 ^ _18226_/A3 (AND4_X1) 2 3.03 0.02 0.07 1.34 ^ _18226_/ZN (AND4_X1) _11049_ (net) 0.02 0.00 1.34 ^ _18227_/A2 (AND2_X1) 3 6.05 0.02 0.04 1.39 ^ _18227_/ZN (AND2_X1) _11050_ (net) 0.02 0.00 1.39 ^ _18228_/A2 (AND2_X1) 3 5.68 0.02 0.04 1.43 ^ _18228_/ZN (AND2_X1) _11051_ (net) 0.02 0.00 1.43 ^ _18264_/A3 (NAND3_X1) 1 1.55 0.02 0.02 1.46 v _18264_/ZN (NAND3_X1) _11087_ (net) 0.02 0.00 1.46 v _18275_/A1 (AND3_X1) 2 2.82 0.01 0.04 1.49 v _18275_/ZN (AND3_X1) _11098_ (net) 0.01 0.00 1.49 v _18276_/B2 (AOI21_X1) 3 9.29 0.06 0.07 1.56 ^ _18276_/ZN (AOI21_X1) _11099_ (net) 0.06 0.00 1.56 ^ _18277_/B2 (OAI21_X1) 4 6.86 0.03 0.04 1.61 v _18277_/ZN (OAI21_X1) _11100_ (net) 0.03 0.00 1.61 v _18348_/A1 (AND2_X1) 2 5.37 0.01 0.04 1.65 v _18348_/ZN (AND2_X1) _11169_ (net) 0.01 0.00 1.65 v _18349_/A3 (NOR3_X2) 3 8.80 0.05 0.07 1.72 ^ _18349_/ZN (NOR3_X2) _11170_ (net) 0.05 0.00 1.72 ^ _18350_/A2 (NOR2_X2) 2 15.12 0.02 0.03 1.75 v _18350_/ZN (NOR2_X2) net179 (net) 0.02 0.00 1.75 v _26998_/B2 (AOI221_X1) 1 4.81 0.06 0.11 1.86 ^ _26998_/ZN (AOI221_X1) _07782_ (net) 0.06 0.00 1.86 ^ _27000_/A1 (NOR2_X1) 3 12.16 0.02 0.04 1.89 v _27000_/ZN (NOR2_X1) _07784_ (net) 0.02 0.00 1.90 v _27001_/A (AOI21_X1) 2 5.84 0.04 0.07 1.96 ^ _27001_/ZN (AOI21_X1) _07785_ (net) 0.04 0.00 1.96 ^ _27217_/B1 (AOI21_X1) 2 3.17 0.02 0.03 1.99 v _27217_/ZN (AOI21_X1) net247 (net) 0.02 0.00 1.99 v output248/A (BUF_X1) 1 0.18 0.00 0.03 2.02 v output248/Z (BUF_X1) instr_addr_o[31] (net) 0.00 0.00 2.02 v instr_addr_o[31] (out) 2.02 data arrival time 0.00 2.20 2.20 clock vclk_core_clock (rise edge) 0.28 2.49 clock network delay (ideal) 0.00 2.49 clock reconvergence pessimism -0.44 2.05 output external delay 2.05 data required time ----------------------------------------------------------------------------- 2.05 data required time -2.02 data arrival time ----------------------------------------------------------------------------- 0.03 slack (MET) ========================================================================== finish report_check_types -max_slew -max_cap -max_fanout -violators -------------------------------------------------------------------------- ========================================================================== finish max_slew_check_slack -------------------------------------------------------------------------- 0.0701238363981247 ========================================================================== finish max_slew_check_limit -------------------------------------------------------------------------- 0.1985349953174591 ========================================================================== finish max_slew_check_slack_limit -------------------------------------------------------------------------- 0.3532 ========================================================================== finish max_fanout_check_slack -------------------------------------------------------------------------- 1.0000000150474662e+30 ========================================================================== finish max_fanout_check_limit -------------------------------------------------------------------------- 1.0000000150474662e+30 ========================================================================== finish max_capacitance_check_slack -------------------------------------------------------------------------- -0.48827892541885376 ========================================================================== finish max_capacitance_check_limit -------------------------------------------------------------------------- 13.008099555969238 ========================================================================== finish max_capacitance_check_slack_limit -------------------------------------------------------------------------- -0.0375 ========================================================================== finish max_slew_violation_count -------------------------------------------------------------------------- max slew violation count 0 ========================================================================== finish max_fanout_violation_count -------------------------------------------------------------------------- max fanout violation count 0 ========================================================================== finish max_cap_violation_count -------------------------------------------------------------------------- max cap violation count 0 ========================================================================== finish setup_violation_count -------------------------------------------------------------------------- setup violation count 0 ========================================================================== finish hold_violation_count -------------------------------------------------------------------------- hold violation count 0 ========================================================================== finish report_checks -path_delay max reg to reg -------------------------------------------------------------------------- Startpoint: if_stage_i.instr_rdata_id_o[20]$_DFFE_PP_ (rising edge-triggered flip-flop clocked by core_clock) Endpoint: gen_regfile_ff.register_file_i.rf_reg[566]$_DFFE_PN0P_ (rising edge-triggered flip-flop clocked by core_clock) Path Group: core_clock Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock core_clock (rise edge) 0.00 0.00 clock source latency 0.00 0.00 ^ clk_i (in) 0.03 0.03 ^ clkbuf_0_clk_i/Z (CLKBUF_X3) 0.03 0.05 ^ clkbuf_1_0__f_clk_i/Z (CLKBUF_X3) 0.03 0.08 ^ _27049_/ZN (AND2_X1) 0.06 0.14 ^ clkbuf_0_clk/Z (CLKBUF_X3) 0.05 0.19 ^ clkbuf_3_3_0_clk/Z (CLKBUF_X3) 0.05 0.24 ^ clkbuf_4_6__f_clk/Z (CLKBUF_X3) 0.04 0.28 ^ clkbuf_leaf_2_clk/Z (CLKBUF_X3) 0.00 0.28 ^ if_stage_i.instr_rdata_id_o[20]$_DFFE_PP_/CK (DFF_X2) 0.15 0.43 ^ if_stage_i.instr_rdata_id_o[20]$_DFFE_PP_/Q (DFF_X2) 0.03 0.47 ^ place2861/Z (BUF_X16) 0.10 0.57 ^ place2859/Z (BUF_X2) 0.06 0.63 v _15920_/Z (MUX2_X1) 0.06 0.69 v _15922_/Z (MUX2_X1) 0.06 0.74 v _15923_/Z (MUX2_X1) 0.07 0.81 v _15924_/Z (MUX2_X1) 0.08 0.90 v _15940_/Z (MUX2_X1) 0.03 0.93 ^ _15942_/ZN (INV_X1) 0.01 0.94 v _15943_/ZN (NOR2_X1) 0.06 0.99 ^ _15978_/ZN (AOI21_X1) 0.03 1.02 ^ place2445/Z (BUF_X4) 0.02 1.04 v _16719_/ZN (NOR2_X1) 0.12 1.16 ^ _27596_/S (FA_X1) 0.10 1.26 v _27475_/S (FA_X1) 0.13 1.39 ^ _27654_/S (FA_X1) 0.10 1.49 v _27580_/S (FA_X1) 0.13 1.62 ^ _27489_/S (FA_X1) 0.10 1.72 v _27616_/S (FA_X1) 0.06 1.79 v _27792_/S (HA_X1) 0.02 1.80 ^ _20244_/ZN (INV_X1) 0.01 1.81 v _20246_/ZN (NOR2_X1) 0.05 1.86 ^ _20247_/ZN (OAI21_X1) 0.03 1.89 v _20255_/ZN (OAI21_X2) 0.05 1.94 ^ _20256_/ZN (OAI21_X1) 0.03 1.98 ^ place2188/Z (BUF_X1) 0.02 1.99 v _21033_/ZN (OAI21_X1) 0.04 2.04 v _21034_/ZN (XNOR2_X1) 0.06 2.10 v _21035_/Z (MUX2_X1) 0.08 2.18 v _21036_/ZN (OR3_X1) 0.05 2.23 ^ _21037_/ZN (OAI21_X1) 0.06 2.29 v _21038_/ZN (OAI21_X1) 0.05 2.34 ^ _21053_/ZN (AOI21_X2) 0.03 2.37 ^ place2012/Z (BUF_X8) 0.05 2.43 ^ _23783_/Z (MUX2_X1) 0.00 2.43 ^ gen_regfile_ff.register_file_i.rf_reg[566]$_DFFE_PN0P_/D (DFFR_X1) 2.43 data arrival time 2.20 2.20 clock core_clock (rise edge) 0.00 2.20 clock source latency 0.00 2.20 ^ clk_i (in) 0.03 2.23 ^ delaybuf_0_core_clock/Z (CLKBUF_X3) 0.03 2.26 ^ delaybuf_1_core_clock/Z (CLKBUF_X3) 0.03 2.28 ^ clkbuf_regs_0_core_clock/Z (CLKBUF_X3) 0.08 2.36 ^ clkbuf_0_clk_i_regs/Z (CLKBUF_X3) 0.07 2.42 ^ clkbuf_4_12_0_clk_i_regs/Z (CLKBUF_X3) 0.04 2.47 ^ clkbuf_leaf_53_clk_i_regs/Z (CLKBUF_X3) 0.00 2.47 ^ gen_regfile_ff.register_file_i.rf_reg[566]$_DFFE_PN0P_/CK (DFFR_X1) 0.00 2.47 clock reconvergence pessimism -0.03 2.44 library setup time 2.44 data required time --------------------------------------------------------- 2.44 data required time -2.43 data arrival time --------------------------------------------------------- 0.01 slack (MET) ========================================================================== finish report_checks -path_delay min reg to reg -------------------------------------------------------------------------- Startpoint: id_stage_i.controller_i.ctrl_fsm_cs[0]$_DFF_PN1_ (rising edge-triggered flip-flop clocked by core_clock) Endpoint: id_stage_i.controller_i.ctrl_fsm_cs[5]$_DFF_PN0_ (rising edge-triggered flip-flop clocked by core_clock) Path Group: core_clock Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock core_clock (rise edge) 0.00 0.00 clock source latency 0.00 0.00 ^ clk_i (in) 0.03 0.03 ^ clkbuf_0_clk_i/Z (CLKBUF_X3) 0.03 0.05 ^ clkbuf_1_0__f_clk_i/Z (CLKBUF_X3) 0.03 0.08 ^ _27049_/ZN (AND2_X1) 0.06 0.14 ^ clkbuf_0_clk/Z (CLKBUF_X3) 0.05 0.19 ^ clkbuf_3_4_0_clk/Z (CLKBUF_X3) 0.05 0.24 ^ clkbuf_4_8__f_clk/Z (CLKBUF_X3) 0.04 0.28 ^ clkbuf_leaf_22_clk/Z (CLKBUF_X3) 0.00 0.28 ^ id_stage_i.controller_i.ctrl_fsm_cs[0]$_DFF_PN1_/CK (DFFS_X1) 0.09 0.37 v id_stage_i.controller_i.ctrl_fsm_cs[0]$_DFF_PN1_/Q (DFFS_X1) 0.00 0.37 v id_stage_i.controller_i.ctrl_fsm_cs[5]$_DFF_PN0_/D (DFFR_X1) 0.37 data arrival time 0.00 0.00 clock core_clock (rise edge) 0.00 0.00 clock source latency 0.00 0.00 ^ clk_i (in) 0.03 0.03 ^ clkbuf_0_clk_i/Z (CLKBUF_X3) 0.03 0.05 ^ clkbuf_1_0__f_clk_i/Z (CLKBUF_X3) 0.03 0.08 ^ _27049_/ZN (AND2_X1) 0.06 0.14 ^ clkbuf_0_clk/Z (CLKBUF_X3) 0.05 0.19 ^ clkbuf_3_4_0_clk/Z (CLKBUF_X3) 0.05 0.24 ^ clkbuf_4_8__f_clk/Z (CLKBUF_X3) 0.04 0.28 ^ clkbuf_leaf_22_clk/Z (CLKBUF_X3) 0.00 0.28 ^ id_stage_i.controller_i.ctrl_fsm_cs[5]$_DFF_PN0_/CK (DFFR_X1) 0.00 0.28 clock reconvergence pessimism 0.00 0.29 library hold time 0.29 data required time --------------------------------------------------------- 0.29 data required time -0.37 data arrival time --------------------------------------------------------- 0.09 slack (MET) ========================================================================== finish critical path target clock latency max path -------------------------------------------------------------------------- 0.2626 ========================================================================== finish critical path target clock latency min path -------------------------------------------------------------------------- 0.2681 ========================================================================== finish critical path source clock latency min path -------------------------------------------------------------------------- 0.2850 ========================================================================== finish critical path delay -------------------------------------------------------------------------- 2.4262 ========================================================================== finish critical path slack -------------------------------------------------------------------------- 0.0090 ========================================================================== finish slack div critical path delay -------------------------------------------------------------------------- 0.370950 ========================================================================== finish report_power -------------------------------------------------------------------------- Group Internal Switching Leakage Total Power Power Power Power (Watts) ---------------------------------------------------------------- Sequential 7.23e-03 5.24e-04 1.55e-04 7.91e-03 24.7% Combinational 8.15e-03 1.14e-02 3.88e-04 2.00e-02 62.4% Clock 1.89e-03 2.25e-03 1.41e-05 4.15e-03 13.0% Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0% Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0% ---------------------------------------------------------------- Total 1.73e-02 1.42e-02 5.57e-04 3.20e-02 100.0% 53.9% 44.4% 1.7%