========================================================================== finish report_tns -------------------------------------------------------------------------- tns max 0.00 ========================================================================== finish report_wns -------------------------------------------------------------------------- wns max 0.00 ========================================================================== finish report_worst_slack -------------------------------------------------------------------------- worst slack max 0.02 ========================================================================== finish report_clock_min_period -------------------------------------------------------------------------- core_clock period_min = 2.18 fmax = 459.20 vclk_core_clock period_min = 1.94 fmax = 514.49 ========================================================================== finish report_clock_skew -------------------------------------------------------------------------- Clock core_clock 0.30 source latency load_store_unit_i.addr_last_o[8]$_DFFE_PN0P_/CK ^ -0.25 target latency gen_regfile_ff.register_file_i.rf_reg[601]$_DFFE_PN0P_/CK ^ 0.00 CRPR -------------- 0.05 setup skew Clock vclk_core_clock No launch/capture paths found. ========================================================================== finish report_checks -path_delay min -------------------------------------------------------------------------- Startpoint: rst_ni (input port clocked by vclk_core_clock) Endpoint: cs_registers_i.mcycle_counter_i.counter_val_o[53]$_DFFE_PN0P_ (removal check against rising-edge clock core_clock) Path Group: asynchronous Path Type: min Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 0.00 clock vclk_core_clock (rise edge) 0.28 0.28 clock network delay (ideal) 0.44 0.72 ^ input external delay 1 2.07 0.00 0.00 0.72 ^ rst_ni (in) rst_ni (net) 0.00 0.00 0.73 ^ input155/A (CLKBUF_X3) 15 67.27 0.05 0.07 0.79 ^ input155/Z (CLKBUF_X3) net154 (net) 0.05 0.01 0.80 ^ cs_registers_i.mcycle_counter_i.counter_val_o[53]$_DFFE_PN0P_/RN (DFFR_X1) 0.80 data arrival time 0.00 0.00 clock core_clock (rise edge) 0.00 0.00 clock source latency 2 21.41 0.00 0.00 0.00 ^ clk_i (in) clk_i (net) 0.00 0.00 0.00 ^ clkbuf_0_clk_i/A (CLKBUF_X3) 1 2.27 0.01 0.02 0.03 ^ clkbuf_0_clk_i/Z (CLKBUF_X3) clknet_0_clk_i (net) 0.01 0.00 0.03 ^ clkbuf_1_0__f_clk_i/A (CLKBUF_X3) 1 1.70 0.01 0.03 0.05 ^ clkbuf_1_0__f_clk_i/Z (CLKBUF_X3) clknet_1_0__leaf_clk_i (net) 0.01 0.00 0.05 ^ _27049_/A2 (AND2_X1) 1 1.64 0.01 0.03 0.08 ^ _27049_/ZN (AND2_X1) clk (net) 0.01 0.00 0.08 ^ clkbuf_0_clk/A (CLKBUF_X3) 16 71.97 0.05 0.08 0.17 ^ clkbuf_0_clk/Z (CLKBUF_X3) clknet_0_clk (net) 0.06 0.01 0.17 ^ clkbuf_4_15_0_clk/A (CLKBUF_X3) 14 37.37 0.03 0.07 0.25 ^ clkbuf_4_15_0_clk/Z (CLKBUF_X3) clknet_4_15_0_clk (net) 0.03 0.00 0.25 ^ clkbuf_leaf_72_clk/A (CLKBUF_X3) 8 12.77 0.01 0.05 0.29 ^ clkbuf_leaf_72_clk/Z (CLKBUF_X3) clknet_leaf_72_clk (net) 0.01 0.00 0.29 ^ cs_registers_i.mcycle_counter_i.counter_val_o[53]$_DFFE_PN0P_/CK (DFFR_X1) 0.00 0.29 clock reconvergence pessimism 0.25 0.54 library removal time 0.54 data required time ----------------------------------------------------------------------------- 0.54 data required time -0.80 data arrival time ----------------------------------------------------------------------------- 0.26 slack (MET) Startpoint: core_clock_gate_i.en_latch$_DLATCH_N_ (negative level-sensitive latch clocked by core_clock) Endpoint: _27049_ (rising clock gating-check end-point clocked by core_clock) Path Group: gated clock Path Type: min Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 1.10 1.10 clock core_clock (fall edge) 0.00 1.10 clock source latency 2 21.07 0.00 0.00 1.10 v clk_i (in) clk_i (net) 0.00 0.00 1.10 v delaybuf_0_core_clock/A (CLKBUF_X3) 1 8.56 0.01 0.03 1.13 v delaybuf_0_core_clock/Z (CLKBUF_X3) delaynet_0_core_clock (net) 0.01 0.00 1.13 v clkbuf_regs_0_core_clock/A (CLKBUF_X3) 1 1.63 0.01 0.03 1.16 v clkbuf_regs_0_core_clock/Z (CLKBUF_X3) clk_i_regs (net) 0.01 0.00 1.16 v clkbuf_0_clk_i_regs/A (CLKBUF_X3) 16 64.41 0.05 0.08 1.24 v clkbuf_0_clk_i_regs/Z (CLKBUF_X3) clknet_0_clk_i_regs (net) 0.05 0.01 1.25 v clkbuf_4_6_0_clk_i_regs/A (CLKBUF_X3) 10 36.48 0.03 0.08 1.32 v clkbuf_4_6_0_clk_i_regs/Z (CLKBUF_X3) clknet_4_6_0_clk_i_regs (net) 0.03 0.00 1.33 v clkbuf_leaf_56_clk_i_regs/A (CLKBUF_X3) 4 9.78 0.01 0.05 1.37 v clkbuf_leaf_56_clk_i_regs/Z (CLKBUF_X3) clknet_leaf_56_clk_i_regs (net) 0.01 0.00 1.37 v core_clock_gate_i.en_latch$_DLATCH_N_/GN (DLL_X1) 1 15.33 0.04 0.09 1.46 ^ core_clock_gate_i.en_latch$_DLATCH_N_/Q (DLL_X1) core_clock_gate_i.en_latch (net) 0.04 0.00 1.46 ^ _27049_/A1 (AND2_X1) 1.46 data arrival time 1.10 1.10 clock core_clock (fall edge) 0.00 1.10 clock source latency 2 21.07 0.00 0.00 1.10 v clk_i (in) clk_i (net) 0.00 0.00 1.10 v clkbuf_0_clk_i/A (CLKBUF_X3) 1 2.10 0.01 0.03 1.13 v clkbuf_0_clk_i/Z (CLKBUF_X3) clknet_0_clk_i (net) 0.01 0.00 1.13 v clkbuf_1_0__f_clk_i/A (CLKBUF_X3) 1 1.62 0.01 0.03 1.16 v clkbuf_1_0__f_clk_i/Z (CLKBUF_X3) clknet_1_0__leaf_clk_i (net) 0.01 0.00 1.16 v _27049_/A2 (AND2_X1) 0.00 1.16 clock reconvergence pessimism 0.00 1.16 clock gating hold time 1.16 data required time ----------------------------------------------------------------------------- 1.16 data required time -1.46 data arrival time ----------------------------------------------------------------------------- 0.31 slack (MET) Startpoint: cs_registers_i.u_dcsr_csr.rd_data_o[2]$_DFFE_PN0P_ (rising edge-triggered flip-flop clocked by core_clock) Endpoint: cs_registers_i.u_dcsr_csr.rd_data_o[6]$_DFFE_PN0P_ (rising edge-triggered flip-flop clocked by core_clock) Path Group: core_clock Path Type: min Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 clock core_clock (rise edge) 0.00 0.00 clock source latency 2 21.41 0.00 0.00 0.00 ^ clk_i (in) clk_i (net) 0.00 0.00 0.00 ^ clkbuf_0_clk_i/A (CLKBUF_X3) 1 2.27 0.01 0.02 0.03 ^ clkbuf_0_clk_i/Z (CLKBUF_X3) clknet_0_clk_i (net) 0.01 0.00 0.03 ^ clkbuf_1_0__f_clk_i/A (CLKBUF_X3) 1 1.70 0.01 0.03 0.05 ^ clkbuf_1_0__f_clk_i/Z (CLKBUF_X3) clknet_1_0__leaf_clk_i (net) 0.01 0.00 0.05 ^ _27049_/A2 (AND2_X1) 1 1.64 0.01 0.03 0.08 ^ _27049_/ZN (AND2_X1) clk (net) 0.01 0.00 0.08 ^ clkbuf_0_clk/A (CLKBUF_X3) 16 71.97 0.05 0.08 0.17 ^ clkbuf_0_clk/Z (CLKBUF_X3) clknet_0_clk (net) 0.05 0.00 0.17 ^ clkbuf_4_7_0_clk/A (CLKBUF_X3) 9 26.49 0.02 0.06 0.24 ^ clkbuf_4_7_0_clk/Z (CLKBUF_X3) clknet_4_7_0_clk (net) 0.02 0.00 0.24 ^ clkbuf_leaf_101_clk/A (CLKBUF_X3) 8 10.63 0.01 0.04 0.28 ^ clkbuf_leaf_101_clk/Z (CLKBUF_X3) clknet_leaf_101_clk (net) 0.01 0.00 0.28 ^ cs_registers_i.u_dcsr_csr.rd_data_o[2]$_DFFE_PN0P_/CK (DFFR_X1) 2 5.19 0.02 0.08 0.36 ^ cs_registers_i.u_dcsr_csr.rd_data_o[2]$_DFFE_PN0P_/QN (DFFR_X1) _00017_ (net) 0.02 0.00 0.36 ^ _26634_/A (INV_X1) 1 1.64 0.01 0.01 0.37 v _26634_/ZN (INV_X1) _07534_ (net) 0.01 0.00 0.37 v _26636_/A1 (AOI22_X1) 1 1.49 0.01 0.02 0.39 ^ _26636_/ZN (AOI22_X1) _02347_ (net) 0.01 0.00 0.39 ^ cs_registers_i.u_dcsr_csr.rd_data_o[6]$_DFFE_PN0P_/D (DFFR_X1) 0.39 data arrival time 0.00 0.00 clock core_clock (rise edge) 0.00 0.00 clock source latency 2 21.41 0.00 0.00 0.00 ^ clk_i (in) clk_i (net) 0.00 0.00 0.00 ^ clkbuf_0_clk_i/A (CLKBUF_X3) 1 2.27 0.01 0.02 0.03 ^ clkbuf_0_clk_i/Z (CLKBUF_X3) clknet_0_clk_i (net) 0.01 0.00 0.03 ^ clkbuf_1_0__f_clk_i/A (CLKBUF_X3) 1 1.70 0.01 0.03 0.05 ^ clkbuf_1_0__f_clk_i/Z (CLKBUF_X3) clknet_1_0__leaf_clk_i (net) 0.01 0.00 0.05 ^ _27049_/A2 (AND2_X1) 1 1.64 0.01 0.03 0.08 ^ _27049_/ZN (AND2_X1) clk (net) 0.01 0.00 0.08 ^ clkbuf_0_clk/A (CLKBUF_X3) 16 71.97 0.05 0.08 0.17 ^ clkbuf_0_clk/Z (CLKBUF_X3) clknet_0_clk (net) 0.06 0.01 0.17 ^ clkbuf_4_13_0_clk/A (CLKBUF_X3) 14 37.38 0.03 0.07 0.25 ^ clkbuf_4_13_0_clk/Z (CLKBUF_X3) clknet_4_13_0_clk (net) 0.03 0.00 0.25 ^ clkbuf_leaf_103_clk/A (CLKBUF_X3) 7 10.67 0.01 0.04 0.29 ^ clkbuf_leaf_103_clk/Z (CLKBUF_X3) clknet_leaf_103_clk (net) 0.01 0.00 0.29 ^ cs_registers_i.u_dcsr_csr.rd_data_o[6]$_DFFE_PN0P_/CK (DFFR_X1) 0.00 0.29 clock reconvergence pessimism 0.01 0.30 library hold time 0.30 data required time ----------------------------------------------------------------------------- 0.30 data required time -0.39 data arrival time ----------------------------------------------------------------------------- 0.08 slack (MET) Startpoint: fetch_enable_q$_DFFE_PN0P_ (rising edge-triggered flip-flop clocked by core_clock) Endpoint: core_sleep_o (output port clocked by vclk_core_clock) Path Group: vclk_core_clock Path Type: min Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 clock core_clock (rise edge) 0.00 0.00 clock source latency 2 21.41 0.00 0.00 0.00 ^ clk_i (in) clk_i (net) 0.00 0.00 0.00 ^ delaybuf_0_core_clock/A (CLKBUF_X3) 1 8.73 0.01 0.03 0.03 ^ delaybuf_0_core_clock/Z (CLKBUF_X3) delaynet_0_core_clock (net) 0.01 0.00 0.03 ^ clkbuf_regs_0_core_clock/A (CLKBUF_X3) 1 1.80 0.01 0.03 0.06 ^ clkbuf_regs_0_core_clock/Z (CLKBUF_X3) clk_i_regs (net) 0.01 0.00 0.06 ^ clkbuf_0_clk_i_regs/A (CLKBUF_X3) 16 67.17 0.05 0.08 0.14 ^ clkbuf_0_clk_i_regs/Z (CLKBUF_X3) clknet_0_clk_i_regs (net) 0.05 0.01 0.14 ^ clkbuf_4_6_0_clk_i_regs/A (CLKBUF_X3) 10 38.59 0.03 0.07 0.22 ^ clkbuf_4_6_0_clk_i_regs/Z (CLKBUF_X3) clknet_4_6_0_clk_i_regs (net) 0.03 0.00 0.22 ^ clkbuf_leaf_56_clk_i_regs/A (CLKBUF_X3) 4 10.62 0.01 0.04 0.26 ^ clkbuf_leaf_56_clk_i_regs/Z (CLKBUF_X3) clknet_leaf_56_clk_i_regs (net) 0.01 0.00 0.26 ^ fetch_enable_q$_DFFE_PN0P_/CK (DFFR_X1) 2 3.06 0.01 0.09 0.35 v fetch_enable_q$_DFFE_PN0P_/Q (DFFR_X1) fetch_enable_q (net) 0.01 0.00 0.35 v _27045_/A (OAI21_X1) 2 3.78 0.02 0.02 0.38 ^ _27045_/ZN (OAI21_X1) net156 (net) 0.02 0.00 0.38 ^ output157/A (BUF_X1) 1 0.14 0.00 0.02 0.40 ^ output157/Z (BUF_X1) core_sleep_o (net) 0.00 0.00 0.40 ^ core_sleep_o (out) 0.40 data arrival time 0.00 0.00 0.00 clock vclk_core_clock (rise edge) 0.28 0.28 clock network delay (ideal) 0.00 0.28 clock reconvergence pessimism -0.44 -0.15 output external delay -0.15 data required time ----------------------------------------------------------------------------- -0.15 data required time -0.40 data arrival time ----------------------------------------------------------------------------- 0.55 slack (MET) ========================================================================== finish report_checks -path_delay max -------------------------------------------------------------------------- Startpoint: rst_ni (input port clocked by vclk_core_clock) Endpoint: gen_regfile_ff.register_file_i.rf_reg[646]$_DFFE_PN0P_ (recovery check against rising-edge clock core_clock) Path Group: asynchronous Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 0.00 clock vclk_core_clock (rise edge) 0.28 0.28 clock network delay (ideal) 0.44 0.72 ^ input external delay 1 2.07 0.00 0.00 0.72 ^ rst_ni (in) rst_ni (net) 0.00 0.00 0.73 ^ input155/A (CLKBUF_X3) 15 67.27 0.05 0.07 0.79 ^ input155/Z (CLKBUF_X3) net154 (net) 0.05 0.01 0.81 ^ place2616/A (BUF_X1) 4 19.32 0.04 0.07 0.88 ^ place2616/Z (BUF_X1) net2615 (net) 0.04 0.00 0.88 ^ place2615/A (BUF_X2) 19 46.34 0.05 0.08 0.96 ^ place2615/Z (BUF_X2) net2614 (net) 0.05 0.00 0.96 ^ place2607/A (BUF_X2) 36 77.37 0.09 0.11 1.08 ^ place2607/Z (BUF_X2) net2606 (net) 0.09 0.00 1.08 ^ place2605/A (BUF_X2) 30 63.00 0.07 0.10 1.18 ^ place2605/Z (BUF_X2) net2604 (net) 0.07 0.01 1.19 ^ place2604/A (BUF_X2) 33 69.55 0.08 0.11 1.29 ^ place2604/Z (BUF_X2) net2603 (net) 0.08 0.01 1.30 ^ gen_regfile_ff.register_file_i.rf_reg[646]$_DFFE_PN0P_/RN (DFFR_X1) 1.30 data arrival time 2.20 2.20 clock core_clock (rise edge) 0.00 2.20 clock source latency 2 21.41 0.00 0.00 2.20 ^ clk_i (in) clk_i (net) 0.00 0.00 2.20 ^ delaybuf_0_core_clock/A (CLKBUF_X3) 1 8.73 0.01 0.03 2.23 ^ delaybuf_0_core_clock/Z (CLKBUF_X3) delaynet_0_core_clock (net) 0.01 0.00 2.23 ^ clkbuf_regs_0_core_clock/A (CLKBUF_X3) 1 1.80 0.01 0.03 2.26 ^ clkbuf_regs_0_core_clock/Z (CLKBUF_X3) clk_i_regs (net) 0.01 0.00 2.26 ^ clkbuf_0_clk_i_regs/A (CLKBUF_X3) 16 67.17 0.05 0.08 2.34 ^ clkbuf_0_clk_i_regs/Z (CLKBUF_X3) clknet_0_clk_i_regs (net) 0.05 0.01 2.34 ^ clkbuf_4_5_0_clk_i_regs/A (CLKBUF_X3) 15 36.93 0.03 0.07 2.42 ^ clkbuf_4_5_0_clk_i_regs/Z (CLKBUF_X3) clknet_4_5_0_clk_i_regs (net) 0.03 0.00 2.42 ^ clkbuf_leaf_79_clk_i_regs/A (CLKBUF_X3) 9 10.76 0.01 0.04 2.46 ^ clkbuf_leaf_79_clk_i_regs/Z (CLKBUF_X3) clknet_leaf_79_clk_i_regs (net) 0.01 0.00 2.46 ^ gen_regfile_ff.register_file_i.rf_reg[646]$_DFFE_PN0P_/CK (DFFR_X1) 0.00 2.46 clock reconvergence pessimism 0.05 2.51 library recovery time 2.51 data required time ----------------------------------------------------------------------------- 2.51 data required time -1.30 data arrival time ----------------------------------------------------------------------------- 1.21 slack (MET) Startpoint: core_clock_gate_i.en_latch$_DLATCH_N_ (negative level-sensitive latch clocked by core_clock) Endpoint: _27049_ (rising clock gating-check end-point clocked by core_clock) Path Group: gated clock Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 1.10 1.10 clock core_clock (fall edge) 0.00 1.10 clock source latency 2 21.07 0.00 0.00 1.10 v clk_i (in) clk_i (net) 0.00 0.00 1.10 v delaybuf_0_core_clock/A (CLKBUF_X3) 1 8.56 0.01 0.03 1.13 v delaybuf_0_core_clock/Z (CLKBUF_X3) delaynet_0_core_clock (net) 0.01 0.00 1.13 v clkbuf_regs_0_core_clock/A (CLKBUF_X3) 1 1.63 0.01 0.03 1.16 v clkbuf_regs_0_core_clock/Z (CLKBUF_X3) clk_i_regs (net) 0.01 0.00 1.16 v clkbuf_0_clk_i_regs/A (CLKBUF_X3) 16 64.41 0.05 0.08 1.24 v clkbuf_0_clk_i_regs/Z (CLKBUF_X3) clknet_0_clk_i_regs (net) 0.05 0.01 1.25 v clkbuf_4_6_0_clk_i_regs/A (CLKBUF_X3) 10 36.48 0.03 0.08 1.32 v clkbuf_4_6_0_clk_i_regs/Z (CLKBUF_X3) clknet_4_6_0_clk_i_regs (net) 0.03 0.00 1.33 v clkbuf_leaf_56_clk_i_regs/A (CLKBUF_X3) 4 9.78 0.01 0.05 1.37 v clkbuf_leaf_56_clk_i_regs/Z (CLKBUF_X3) clknet_leaf_56_clk_i_regs (net) 0.01 0.00 1.37 v core_clock_gate_i.en_latch$_DLATCH_N_/GN (DLL_X1) 1 15.29 0.02 0.10 1.47 v core_clock_gate_i.en_latch$_DLATCH_N_/Q (DLL_X1) core_clock_gate_i.en_latch (net) 0.02 0.00 1.48 v _27049_/A1 (AND2_X1) 1.48 data arrival time 2.20 2.20 clock core_clock (rise edge) 0.00 2.20 clock source latency 2 21.41 0.00 0.00 2.20 ^ clk_i (in) clk_i (net) 0.00 0.00 2.20 ^ clkbuf_0_clk_i/A (CLKBUF_X3) 1 2.27 0.01 0.02 2.23 ^ clkbuf_0_clk_i/Z (CLKBUF_X3) clknet_0_clk_i (net) 0.01 0.00 2.23 ^ clkbuf_1_0__f_clk_i/A (CLKBUF_X3) 1 1.70 0.01 0.03 2.25 ^ clkbuf_1_0__f_clk_i/Z (CLKBUF_X3) clknet_1_0__leaf_clk_i (net) 0.01 0.00 2.25 ^ _27049_/A2 (AND2_X1) 0.00 2.25 clock reconvergence pessimism 0.00 2.25 clock gating setup time 2.25 data required time ----------------------------------------------------------------------------- 2.25 data required time -1.48 data arrival time ----------------------------------------------------------------------------- 0.78 slack (MET) Startpoint: if_stage_i.instr_rdata_id_o[20]$_DFFE_PP_ (rising edge-triggered flip-flop clocked by core_clock) Endpoint: gen_regfile_ff.register_file_i.rf_reg[444]$_DFFE_PN0P_ (rising edge-triggered flip-flop clocked by core_clock) Path Group: core_clock Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 clock core_clock (rise edge) 0.00 0.00 clock source latency 2 21.41 0.00 0.00 0.00 ^ clk_i (in) clk_i (net) 0.00 0.00 0.00 ^ clkbuf_0_clk_i/A (CLKBUF_X3) 1 2.27 0.01 0.02 0.03 ^ clkbuf_0_clk_i/Z (CLKBUF_X3) clknet_0_clk_i (net) 0.01 0.00 0.03 ^ clkbuf_1_0__f_clk_i/A (CLKBUF_X3) 1 1.70 0.01 0.03 0.05 ^ clkbuf_1_0__f_clk_i/Z (CLKBUF_X3) clknet_1_0__leaf_clk_i (net) 0.01 0.00 0.05 ^ _27049_/A2 (AND2_X1) 1 1.64 0.01 0.03 0.08 ^ _27049_/ZN (AND2_X1) clk (net) 0.01 0.00 0.08 ^ clkbuf_0_clk/A (CLKBUF_X3) 16 71.97 0.05 0.08 0.17 ^ clkbuf_0_clk/Z (CLKBUF_X3) clknet_0_clk (net) 0.05 0.00 0.17 ^ clkbuf_4_3_0_clk/A (CLKBUF_X3) 5 21.66 0.02 0.06 0.23 ^ clkbuf_4_3_0_clk/Z (CLKBUF_X3) clknet_4_3_0_clk (net) 0.02 0.00 0.23 ^ clkbuf_leaf_135_clk/A (CLKBUF_X3) 7 11.37 0.01 0.04 0.27 ^ clkbuf_leaf_135_clk/Z (CLKBUF_X3) clknet_leaf_135_clk (net) 0.01 0.00 0.27 ^ if_stage_i.instr_rdata_id_o[20]$_DFFE_PP_/CK (DFF_X2) 3 12.71 0.02 0.13 0.40 ^ if_stage_i.instr_rdata_id_o[20]$_DFFE_PP_/Q (DFF_X2) gen_regfile_ff.register_file_i.raddr_b_i[0] (net) 0.02 0.00 0.40 ^ rebuffer2617/A (BUF_X8) 4 39.92 0.01 0.03 0.43 ^ rebuffer2617/Z (BUF_X8) net2616 (net) 0.01 0.00 0.44 ^ place2488/A (BUF_X16) 78 191.04 0.01 0.03 0.46 ^ place2488/Z (BUF_X16) net2487 (net) 0.12 0.09 0.56 ^ _15916_/S (MUX2_X1) 1 1.13 0.01 0.06 0.62 v _15916_/Z (MUX2_X1) _08905_ (net) 0.01 0.00 0.62 v _15919_/A (MUX2_X1) 1 1.66 0.01 0.06 0.68 v _15919_/Z (MUX2_X1) _08908_ (net) 0.01 0.00 0.68 v _15923_/A (MUX2_X1) 1 2.22 0.01 0.06 0.74 v _15923_/Z (MUX2_X1) _08912_ (net) 0.01 0.00 0.74 v _15924_/B (MUX2_X1) 1 4.20 0.01 0.06 0.80 v _15924_/Z (MUX2_X1) _08913_ (net) 0.01 0.00 0.80 v _15940_/A (MUX2_X2) 7 26.77 0.02 0.08 0.88 v _15940_/Z (MUX2_X2) _08929_ (net) 0.02 0.00 0.88 v _15942_/A (INV_X1) 2 4.15 0.01 0.02 0.91 ^ _15942_/ZN (INV_X1) _08931_ (net) 0.01 0.00 0.91 ^ _15943_/A2 (NOR2_X1) 1 1.59 0.01 0.01 0.92 v _15943_/ZN (NOR2_X1) _08932_ (net) 0.01 0.00 0.92 v _15978_/A (AOI21_X1) 1 7.21 0.05 0.07 0.99 ^ _15978_/ZN (AOI21_X1) _08967_ (net) 0.05 0.00 0.99 ^ place2174/A (BUF_X4) 12 35.66 0.02 0.04 1.03 ^ place2174/Z (BUF_X4) net2173 (net) 0.03 0.01 1.04 ^ _16719_/A1 (NOR2_X1) 1 3.54 0.01 0.01 1.05 v _16719_/ZN (NOR2_X1) _00314_ (net) 0.01 0.00 1.05 v _27596_/B (FA_X1) 1 3.56 0.01 0.13 1.18 ^ _27596_/S (FA_X1) _14511_ (net) 0.01 0.00 1.18 ^ _27475_/B (FA_X1) 1 3.55 0.02 0.10 1.28 v _27475_/S (FA_X1) _14513_ (net) 0.02 0.00 1.28 v _27654_/B (FA_X1) 1 4.40 0.02 0.13 1.41 ^ _27654_/S (FA_X1) _14748_ (net) 0.02 0.00 1.41 ^ _27580_/B (FA_X1) 1 3.65 0.02 0.10 1.50 v _27580_/S (FA_X1) _14552_ (net) 0.02 0.00 1.50 v _27489_/B (FA_X1) 1 3.69 0.02 0.13 1.63 ^ _27489_/S (FA_X1) _14555_ (net) 0.02 0.00 1.63 ^ _27616_/B (FA_X1) 1 4.01 0.02 0.10 1.73 v _27616_/S (FA_X1) _14839_ (net) 0.02 0.00 1.73 v _27792_/B (HA_X1) 3 5.75 0.02 0.07 1.79 v _27792_/S (HA_X1) _00473_ (net) 0.02 0.00 1.79 v _20244_/A (INV_X1) 2 4.53 0.01 0.02 1.82 ^ _20244_/ZN (INV_X1) _02879_ (net) 0.01 0.00 1.82 ^ _20246_/A1 (NOR2_X1) 1 1.64 0.01 0.01 1.83 v _20246_/ZN (NOR2_X1) _02881_ (net) 0.01 0.00 1.83 v _20247_/B2 (OAI21_X1) 2 3.79 0.03 0.04 1.87 ^ _20247_/ZN (OAI21_X1) _02882_ (net) 0.03 0.00 1.87 ^ _20255_/A (OAI21_X1) 2 2.96 0.01 0.03 1.89 v _20255_/ZN (OAI21_X1) _02890_ (net) 0.01 0.00 1.89 v _20256_/B2 (OAI21_X1) 2 5.37 0.03 0.05 1.95 ^ _20256_/ZN (OAI21_X1) _02891_ (net) 0.03 0.00 1.95 ^ _20258_/C1 (OAI211_X2) 2 3.77 0.02 0.03 1.97 v _20258_/ZN (OAI211_X2) _02893_ (net) 0.02 0.00 1.97 v _20686_/A1 (NAND2_X1) 2 4.36 0.02 0.02 2.00 ^ _20686_/ZN (NAND2_X1) _03319_ (net) 0.02 0.00 2.00 ^ _20687_/B2 (OAI21_X1) 1 1.55 0.01 0.02 2.02 v _20687_/ZN (OAI21_X1) _03320_ (net) 0.01 0.00 2.02 v _20688_/B1 (AOI21_X1) 1 2.69 0.03 0.03 2.05 ^ _20688_/ZN (AOI21_X1) _03321_ (net) 0.03 0.00 2.05 ^ _20689_/B (XNOR2_X1) 1 3.66 0.01 0.03 2.07 v _20689_/ZN (XNOR2_X1) _03322_ (net) 0.01 0.00 2.07 v _20690_/B (MUX2_X1) 2 3.61 0.01 0.07 2.14 v _20690_/Z (MUX2_X1) _03323_ (net) 0.01 0.00 2.14 v _20691_/B2 (AOI22_X1) 1 2.44 0.03 0.05 2.19 ^ _20691_/ZN (AOI22_X1) _03324_ (net) 0.03 0.00 2.19 ^ _20692_/C1 (OAI221_X1) 1 4.89 0.03 0.04 2.23 v _20692_/ZN (OAI221_X1) _03325_ (net) 0.03 0.00 2.23 v _20693_/B2 (OAI22_X2) 1 3.65 0.03 0.05 2.28 ^ _20693_/ZN (OAI22_X2) _03326_ (net) 0.03 0.00 2.28 ^ place1839/A (BUF_X4) 6 33.40 0.02 0.04 2.32 ^ place1839/Z (BUF_X4) net1838 (net) 0.02 0.01 2.33 ^ place1838/A (BUF_X8) 26 57.21 0.02 0.03 2.36 ^ place1838/Z (BUF_X8) net1837 (net) 0.02 0.01 2.37 ^ _22214_/B2 (OAI21_X1) 1 1.21 0.02 0.02 2.39 v _22214_/ZN (OAI21_X1) _00844_ (net) 0.02 0.00 2.39 v gen_regfile_ff.register_file_i.rf_reg[444]$_DFFE_PN0P_/D (DFFR_X1) 2.39 data arrival time 2.20 2.20 clock core_clock (rise edge) 0.00 2.20 clock source latency 2 21.41 0.00 0.00 2.20 ^ clk_i (in) clk_i (net) 0.00 0.00 2.20 ^ delaybuf_0_core_clock/A (CLKBUF_X3) 1 8.73 0.01 0.03 2.23 ^ delaybuf_0_core_clock/Z (CLKBUF_X3) delaynet_0_core_clock (net) 0.01 0.00 2.23 ^ clkbuf_regs_0_core_clock/A (CLKBUF_X3) 1 1.80 0.01 0.03 2.26 ^ clkbuf_regs_0_core_clock/Z (CLKBUF_X3) clk_i_regs (net) 0.01 0.00 2.26 ^ clkbuf_0_clk_i_regs/A (CLKBUF_X3) 16 67.17 0.05 0.08 2.34 ^ clkbuf_0_clk_i_regs/Z (CLKBUF_X3) clknet_0_clk_i_regs (net) 0.05 0.01 2.34 ^ clkbuf_4_7_0_clk_i_regs/A (CLKBUF_X3) 10 30.15 0.03 0.07 2.41 ^ clkbuf_4_7_0_clk_i_regs/Z (CLKBUF_X3) clknet_4_7_0_clk_i_regs (net) 0.03 0.00 2.41 ^ clkbuf_leaf_64_clk_i_regs/A (CLKBUF_X3) 8 11.32 0.01 0.04 2.45 ^ clkbuf_leaf_64_clk_i_regs/Z (CLKBUF_X3) clknet_leaf_64_clk_i_regs (net) 0.01 0.00 2.45 ^ gen_regfile_ff.register_file_i.rf_reg[444]$_DFFE_PN0P_/CK (DFFR_X1) 0.00 2.45 clock reconvergence pessimism -0.04 2.41 library setup time 2.41 data required time ----------------------------------------------------------------------------- 2.41 data required time -2.39 data arrival time ----------------------------------------------------------------------------- 0.02 slack (MET) Startpoint: if_stage_i.instr_rdata_id_o[31]$_DFFE_PP_ (rising edge-triggered flip-flop clocked by core_clock) Endpoint: instr_addr_o[31] (output port clocked by vclk_core_clock) Path Group: vclk_core_clock Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 clock core_clock (rise edge) 0.00 0.00 clock source latency 2 21.41 0.00 0.00 0.00 ^ clk_i (in) clk_i (net) 0.00 0.00 0.00 ^ clkbuf_0_clk_i/A (CLKBUF_X3) 1 2.27 0.01 0.02 0.03 ^ clkbuf_0_clk_i/Z (CLKBUF_X3) clknet_0_clk_i (net) 0.01 0.00 0.03 ^ clkbuf_1_0__f_clk_i/A (CLKBUF_X3) 1 1.70 0.01 0.03 0.05 ^ clkbuf_1_0__f_clk_i/Z (CLKBUF_X3) clknet_1_0__leaf_clk_i (net) 0.01 0.00 0.05 ^ _27049_/A2 (AND2_X1) 1 1.64 0.01 0.03 0.08 ^ _27049_/ZN (AND2_X1) clk (net) 0.01 0.00 0.08 ^ clkbuf_0_clk/A (CLKBUF_X3) 16 71.97 0.05 0.08 0.17 ^ clkbuf_0_clk/Z (CLKBUF_X3) clknet_0_clk (net) 0.05 0.00 0.17 ^ clkbuf_4_5_0_clk/A (CLKBUF_X3) 9 34.58 0.03 0.07 0.24 ^ clkbuf_4_5_0_clk/Z (CLKBUF_X3) clknet_4_5_0_clk (net) 0.03 0.00 0.24 ^ clkbuf_leaf_139_clk/A (CLKBUF_X3) 9 11.70 0.01 0.04 0.29 ^ clkbuf_leaf_139_clk/Z (CLKBUF_X3) clknet_leaf_139_clk (net) 0.01 0.00 0.29 ^ if_stage_i.instr_rdata_id_o[31]$_DFFE_PP_/CK (DFF_X1) 17 41.33 0.04 0.13 0.42 v if_stage_i.instr_rdata_id_o[31]$_DFFE_PP_/Q (DFF_X1) id_stage_i.controller_i.instr_i[31] (net) 0.04 0.00 0.42 v _15855_/A3 (NOR4_X2) 5 11.53 0.08 0.13 0.55 ^ _15855_/ZN (NOR4_X2) _08844_ (net) 0.08 0.00 0.55 ^ _17582_/A1 (AOI222_X1) 2 3.08 0.03 0.03 0.58 v _17582_/ZN (AOI222_X1) _10510_ (net) 0.03 0.00 0.58 v _17586_/A3 (AND4_X1) 1 1.90 0.01 0.05 0.63 v _17586_/ZN (AND4_X1) _10514_ (net) 0.01 0.00 0.63 v _17587_/B2 (OAI21_X1) 8 18.89 0.09 0.12 0.75 ^ _17587_/ZN (OAI21_X1) _10515_ (net) 0.09 0.00 0.75 ^ _17674_/A1 (NAND4_X2) 4 18.25 0.05 0.08 0.83 v _17674_/ZN (NAND4_X2) _10602_ (net) 0.05 0.00 0.83 v _17684_/A1 (OAI22_X4) 7 17.71 0.04 0.06 0.89 ^ _17684_/ZN (OAI22_X4) _10612_ (net) 0.04 0.00 0.89 ^ _18329_/A2 (NOR2_X1) 4 6.62 0.02 0.03 0.92 v _18329_/ZN (NOR2_X1) _11150_ (net) 0.02 0.00 0.92 v _18749_/A1 (NAND2_X1) 12 26.37 0.06 0.08 1.00 ^ _18749_/ZN (NAND2_X1) _11454_ (net) 0.06 0.00 1.00 ^ place2167/A (BUF_X2) 20 41.99 0.05 0.07 1.07 ^ place2167/Z (BUF_X2) net2166 (net) 0.05 0.01 1.08 ^ _19765_/B2 (OAI221_X1) 1 5.17 0.04 0.05 1.13 v _19765_/ZN (OAI221_X1) ex_block_i.alu_i.adder_in_b[14] (net) 0.04 0.00 1.13 v _27676_/B (HA_X1) 2 2.85 0.03 0.05 1.18 ^ _27676_/S (HA_X1) _00350_ (net) 0.03 0.00 1.18 ^ _18244_/A3 (NAND3_X1) 2 3.85 0.03 0.03 1.21 v _18244_/ZN (NAND3_X1) _11067_ (net) 0.03 0.00 1.21 v _18245_/A3 (OR3_X1) 1 1.66 0.01 0.09 1.30 v _18245_/ZN (OR3_X1) _11068_ (net) 0.01 0.00 1.30 v _18246_/A3 (NOR3_X1) 3 6.20 0.06 0.09 1.38 ^ _18246_/ZN (NOR3_X1) _11069_ (net) 0.06 0.00 1.38 ^ _18262_/A1 (OR3_X1) 2 3.03 0.01 0.04 1.42 ^ _18262_/ZN (OR3_X1) _11085_ (net) 0.01 0.00 1.42 ^ _18263_/A4 (NAND4_X1) 2 3.07 0.02 0.04 1.46 v _18263_/ZN (NAND4_X1) _11086_ (net) 0.02 0.00 1.46 v _18276_/B1 (AOI21_X1) 3 5.18 0.04 0.05 1.51 ^ _18276_/ZN (AOI21_X1) _11099_ (net) 0.04 0.00 1.51 ^ _18277_/B2 (OAI21_X1) 2 8.62 0.02 0.04 1.55 v _18277_/ZN (OAI21_X1) _11100_ (net) 0.02 0.00 1.55 v _18348_/A1 (AND2_X1) 2 5.22 0.01 0.04 1.59 v _18348_/ZN (AND2_X1) _11169_ (net) 0.01 0.00 1.59 v _18349_/A3 (NOR3_X2) 3 7.47 0.04 0.07 1.66 ^ _18349_/ZN (NOR3_X2) _11170_ (net) 0.04 0.00 1.66 ^ _18350_/A2 (NOR2_X2) 2 12.89 0.02 0.03 1.68 v _18350_/ZN (NOR2_X2) net179 (net) 0.02 0.00 1.68 v _26998_/B2 (AOI221_X1) 1 8.06 0.09 0.13 1.82 ^ _26998_/ZN (AOI221_X1) _07782_ (net) 0.09 0.00 1.82 ^ _27000_/A1 (NOR2_X1) 3 9.20 0.03 0.03 1.85 v _27000_/ZN (NOR2_X1) _07784_ (net) 0.03 0.00 1.85 v _27001_/A (AOI21_X1) 2 9.16 0.05 0.08 1.93 ^ _27001_/ZN (AOI21_X1) _07785_ (net) 0.05 0.00 1.94 ^ _27217_/B1 (AOI21_X1) 2 2.06 0.02 0.02 1.96 v _27217_/ZN (AOI21_X1) net247 (net) 0.02 0.00 1.96 v output248/A (BUF_X1) 1 0.17 0.00 0.03 1.99 v output248/Z (BUF_X1) instr_addr_o[31] (net) 0.00 0.00 1.99 v instr_addr_o[31] (out) 1.99 data arrival time 0.00 2.20 2.20 clock vclk_core_clock (rise edge) 0.28 2.49 clock network delay (ideal) 0.00 2.49 clock reconvergence pessimism -0.44 2.05 output external delay 2.05 data required time ----------------------------------------------------------------------------- 2.05 data required time -1.99 data arrival time ----------------------------------------------------------------------------- 0.06 slack (MET) ========================================================================== finish report_checks -unconstrained -------------------------------------------------------------------------- Startpoint: rst_ni (input port clocked by vclk_core_clock) Endpoint: gen_regfile_ff.register_file_i.rf_reg[646]$_DFFE_PN0P_ (recovery check against rising-edge clock core_clock) Path Group: asynchronous Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 0.00 clock vclk_core_clock (rise edge) 0.28 0.28 clock network delay (ideal) 0.44 0.72 ^ input external delay 1 2.07 0.00 0.00 0.72 ^ rst_ni (in) rst_ni (net) 0.00 0.00 0.73 ^ input155/A (CLKBUF_X3) 15 67.27 0.05 0.07 0.79 ^ input155/Z (CLKBUF_X3) net154 (net) 0.05 0.01 0.81 ^ place2616/A (BUF_X1) 4 19.32 0.04 0.07 0.88 ^ place2616/Z (BUF_X1) net2615 (net) 0.04 0.00 0.88 ^ place2615/A (BUF_X2) 19 46.34 0.05 0.08 0.96 ^ place2615/Z (BUF_X2) net2614 (net) 0.05 0.00 0.96 ^ place2607/A (BUF_X2) 36 77.37 0.09 0.11 1.08 ^ place2607/Z (BUF_X2) net2606 (net) 0.09 0.00 1.08 ^ place2605/A (BUF_X2) 30 63.00 0.07 0.10 1.18 ^ place2605/Z (BUF_X2) net2604 (net) 0.07 0.01 1.19 ^ place2604/A (BUF_X2) 33 69.55 0.08 0.11 1.29 ^ place2604/Z (BUF_X2) net2603 (net) 0.08 0.01 1.30 ^ gen_regfile_ff.register_file_i.rf_reg[646]$_DFFE_PN0P_/RN (DFFR_X1) 1.30 data arrival time 2.20 2.20 clock core_clock (rise edge) 0.00 2.20 clock source latency 2 21.41 0.00 0.00 2.20 ^ clk_i (in) clk_i (net) 0.00 0.00 2.20 ^ delaybuf_0_core_clock/A (CLKBUF_X3) 1 8.73 0.01 0.03 2.23 ^ delaybuf_0_core_clock/Z (CLKBUF_X3) delaynet_0_core_clock (net) 0.01 0.00 2.23 ^ clkbuf_regs_0_core_clock/A (CLKBUF_X3) 1 1.80 0.01 0.03 2.26 ^ clkbuf_regs_0_core_clock/Z (CLKBUF_X3) clk_i_regs (net) 0.01 0.00 2.26 ^ clkbuf_0_clk_i_regs/A (CLKBUF_X3) 16 67.17 0.05 0.08 2.34 ^ clkbuf_0_clk_i_regs/Z (CLKBUF_X3) clknet_0_clk_i_regs (net) 0.05 0.01 2.34 ^ clkbuf_4_5_0_clk_i_regs/A (CLKBUF_X3) 15 36.93 0.03 0.07 2.42 ^ clkbuf_4_5_0_clk_i_regs/Z (CLKBUF_X3) clknet_4_5_0_clk_i_regs (net) 0.03 0.00 2.42 ^ clkbuf_leaf_79_clk_i_regs/A (CLKBUF_X3) 9 10.76 0.01 0.04 2.46 ^ clkbuf_leaf_79_clk_i_regs/Z (CLKBUF_X3) clknet_leaf_79_clk_i_regs (net) 0.01 0.00 2.46 ^ gen_regfile_ff.register_file_i.rf_reg[646]$_DFFE_PN0P_/CK (DFFR_X1) 0.00 2.46 clock reconvergence pessimism 0.05 2.51 library recovery time 2.51 data required time ----------------------------------------------------------------------------- 2.51 data required time -1.30 data arrival time ----------------------------------------------------------------------------- 1.21 slack (MET) Startpoint: core_clock_gate_i.en_latch$_DLATCH_N_ (negative level-sensitive latch clocked by core_clock) Endpoint: _27049_ (rising clock gating-check end-point clocked by core_clock) Path Group: gated clock Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 1.10 1.10 clock core_clock (fall edge) 0.00 1.10 clock source latency 2 21.07 0.00 0.00 1.10 v clk_i (in) clk_i (net) 0.00 0.00 1.10 v delaybuf_0_core_clock/A (CLKBUF_X3) 1 8.56 0.01 0.03 1.13 v delaybuf_0_core_clock/Z (CLKBUF_X3) delaynet_0_core_clock (net) 0.01 0.00 1.13 v clkbuf_regs_0_core_clock/A (CLKBUF_X3) 1 1.63 0.01 0.03 1.16 v clkbuf_regs_0_core_clock/Z (CLKBUF_X3) clk_i_regs (net) 0.01 0.00 1.16 v clkbuf_0_clk_i_regs/A (CLKBUF_X3) 16 64.41 0.05 0.08 1.24 v clkbuf_0_clk_i_regs/Z (CLKBUF_X3) clknet_0_clk_i_regs (net) 0.05 0.01 1.25 v clkbuf_4_6_0_clk_i_regs/A (CLKBUF_X3) 10 36.48 0.03 0.08 1.32 v clkbuf_4_6_0_clk_i_regs/Z (CLKBUF_X3) clknet_4_6_0_clk_i_regs (net) 0.03 0.00 1.33 v clkbuf_leaf_56_clk_i_regs/A (CLKBUF_X3) 4 9.78 0.01 0.05 1.37 v clkbuf_leaf_56_clk_i_regs/Z (CLKBUF_X3) clknet_leaf_56_clk_i_regs (net) 0.01 0.00 1.37 v core_clock_gate_i.en_latch$_DLATCH_N_/GN (DLL_X1) 1 15.29 0.02 0.10 1.47 v core_clock_gate_i.en_latch$_DLATCH_N_/Q (DLL_X1) core_clock_gate_i.en_latch (net) 0.02 0.00 1.48 v _27049_/A1 (AND2_X1) 1.48 data arrival time 2.20 2.20 clock core_clock (rise edge) 0.00 2.20 clock source latency 2 21.41 0.00 0.00 2.20 ^ clk_i (in) clk_i (net) 0.00 0.00 2.20 ^ clkbuf_0_clk_i/A (CLKBUF_X3) 1 2.27 0.01 0.02 2.23 ^ clkbuf_0_clk_i/Z (CLKBUF_X3) clknet_0_clk_i (net) 0.01 0.00 2.23 ^ clkbuf_1_0__f_clk_i/A (CLKBUF_X3) 1 1.70 0.01 0.03 2.25 ^ clkbuf_1_0__f_clk_i/Z (CLKBUF_X3) clknet_1_0__leaf_clk_i (net) 0.01 0.00 2.25 ^ _27049_/A2 (AND2_X1) 0.00 2.25 clock reconvergence pessimism 0.00 2.25 clock gating setup time 2.25 data required time ----------------------------------------------------------------------------- 2.25 data required time -1.48 data arrival time ----------------------------------------------------------------------------- 0.78 slack (MET) Startpoint: if_stage_i.instr_rdata_id_o[20]$_DFFE_PP_ (rising edge-triggered flip-flop clocked by core_clock) Endpoint: gen_regfile_ff.register_file_i.rf_reg[444]$_DFFE_PN0P_ (rising edge-triggered flip-flop clocked by core_clock) Path Group: core_clock Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 clock core_clock (rise edge) 0.00 0.00 clock source latency 2 21.41 0.00 0.00 0.00 ^ clk_i (in) clk_i (net) 0.00 0.00 0.00 ^ clkbuf_0_clk_i/A (CLKBUF_X3) 1 2.27 0.01 0.02 0.03 ^ clkbuf_0_clk_i/Z (CLKBUF_X3) clknet_0_clk_i (net) 0.01 0.00 0.03 ^ clkbuf_1_0__f_clk_i/A (CLKBUF_X3) 1 1.70 0.01 0.03 0.05 ^ clkbuf_1_0__f_clk_i/Z (CLKBUF_X3) clknet_1_0__leaf_clk_i (net) 0.01 0.00 0.05 ^ _27049_/A2 (AND2_X1) 1 1.64 0.01 0.03 0.08 ^ _27049_/ZN (AND2_X1) clk (net) 0.01 0.00 0.08 ^ clkbuf_0_clk/A (CLKBUF_X3) 16 71.97 0.05 0.08 0.17 ^ clkbuf_0_clk/Z (CLKBUF_X3) clknet_0_clk (net) 0.05 0.00 0.17 ^ clkbuf_4_3_0_clk/A (CLKBUF_X3) 5 21.66 0.02 0.06 0.23 ^ clkbuf_4_3_0_clk/Z (CLKBUF_X3) clknet_4_3_0_clk (net) 0.02 0.00 0.23 ^ clkbuf_leaf_135_clk/A (CLKBUF_X3) 7 11.37 0.01 0.04 0.27 ^ clkbuf_leaf_135_clk/Z (CLKBUF_X3) clknet_leaf_135_clk (net) 0.01 0.00 0.27 ^ if_stage_i.instr_rdata_id_o[20]$_DFFE_PP_/CK (DFF_X2) 3 12.71 0.02 0.13 0.40 ^ if_stage_i.instr_rdata_id_o[20]$_DFFE_PP_/Q (DFF_X2) gen_regfile_ff.register_file_i.raddr_b_i[0] (net) 0.02 0.00 0.40 ^ rebuffer2617/A (BUF_X8) 4 39.92 0.01 0.03 0.43 ^ rebuffer2617/Z (BUF_X8) net2616 (net) 0.01 0.00 0.44 ^ place2488/A (BUF_X16) 78 191.04 0.01 0.03 0.46 ^ place2488/Z (BUF_X16) net2487 (net) 0.12 0.09 0.56 ^ _15916_/S (MUX2_X1) 1 1.13 0.01 0.06 0.62 v _15916_/Z (MUX2_X1) _08905_ (net) 0.01 0.00 0.62 v _15919_/A (MUX2_X1) 1 1.66 0.01 0.06 0.68 v _15919_/Z (MUX2_X1) _08908_ (net) 0.01 0.00 0.68 v _15923_/A (MUX2_X1) 1 2.22 0.01 0.06 0.74 v _15923_/Z (MUX2_X1) _08912_ (net) 0.01 0.00 0.74 v _15924_/B (MUX2_X1) 1 4.20 0.01 0.06 0.80 v _15924_/Z (MUX2_X1) _08913_ (net) 0.01 0.00 0.80 v _15940_/A (MUX2_X2) 7 26.77 0.02 0.08 0.88 v _15940_/Z (MUX2_X2) _08929_ (net) 0.02 0.00 0.88 v _15942_/A (INV_X1) 2 4.15 0.01 0.02 0.91 ^ _15942_/ZN (INV_X1) _08931_ (net) 0.01 0.00 0.91 ^ _15943_/A2 (NOR2_X1) 1 1.59 0.01 0.01 0.92 v _15943_/ZN (NOR2_X1) _08932_ (net) 0.01 0.00 0.92 v _15978_/A (AOI21_X1) 1 7.21 0.05 0.07 0.99 ^ _15978_/ZN (AOI21_X1) _08967_ (net) 0.05 0.00 0.99 ^ place2174/A (BUF_X4) 12 35.66 0.02 0.04 1.03 ^ place2174/Z (BUF_X4) net2173 (net) 0.03 0.01 1.04 ^ _16719_/A1 (NOR2_X1) 1 3.54 0.01 0.01 1.05 v _16719_/ZN (NOR2_X1) _00314_ (net) 0.01 0.00 1.05 v _27596_/B (FA_X1) 1 3.56 0.01 0.13 1.18 ^ _27596_/S (FA_X1) _14511_ (net) 0.01 0.00 1.18 ^ _27475_/B (FA_X1) 1 3.55 0.02 0.10 1.28 v _27475_/S (FA_X1) _14513_ (net) 0.02 0.00 1.28 v _27654_/B (FA_X1) 1 4.40 0.02 0.13 1.41 ^ _27654_/S (FA_X1) _14748_ (net) 0.02 0.00 1.41 ^ _27580_/B (FA_X1) 1 3.65 0.02 0.10 1.50 v _27580_/S (FA_X1) _14552_ (net) 0.02 0.00 1.50 v _27489_/B (FA_X1) 1 3.69 0.02 0.13 1.63 ^ _27489_/S (FA_X1) _14555_ (net) 0.02 0.00 1.63 ^ _27616_/B (FA_X1) 1 4.01 0.02 0.10 1.73 v _27616_/S (FA_X1) _14839_ (net) 0.02 0.00 1.73 v _27792_/B (HA_X1) 3 5.75 0.02 0.07 1.79 v _27792_/S (HA_X1) _00473_ (net) 0.02 0.00 1.79 v _20244_/A (INV_X1) 2 4.53 0.01 0.02 1.82 ^ _20244_/ZN (INV_X1) _02879_ (net) 0.01 0.00 1.82 ^ _20246_/A1 (NOR2_X1) 1 1.64 0.01 0.01 1.83 v _20246_/ZN (NOR2_X1) _02881_ (net) 0.01 0.00 1.83 v _20247_/B2 (OAI21_X1) 2 3.79 0.03 0.04 1.87 ^ _20247_/ZN (OAI21_X1) _02882_ (net) 0.03 0.00 1.87 ^ _20255_/A (OAI21_X1) 2 2.96 0.01 0.03 1.89 v _20255_/ZN (OAI21_X1) _02890_ (net) 0.01 0.00 1.89 v _20256_/B2 (OAI21_X1) 2 5.37 0.03 0.05 1.95 ^ _20256_/ZN (OAI21_X1) _02891_ (net) 0.03 0.00 1.95 ^ _20258_/C1 (OAI211_X2) 2 3.77 0.02 0.03 1.97 v _20258_/ZN (OAI211_X2) _02893_ (net) 0.02 0.00 1.97 v _20686_/A1 (NAND2_X1) 2 4.36 0.02 0.02 2.00 ^ _20686_/ZN (NAND2_X1) _03319_ (net) 0.02 0.00 2.00 ^ _20687_/B2 (OAI21_X1) 1 1.55 0.01 0.02 2.02 v _20687_/ZN (OAI21_X1) _03320_ (net) 0.01 0.00 2.02 v _20688_/B1 (AOI21_X1) 1 2.69 0.03 0.03 2.05 ^ _20688_/ZN (AOI21_X1) _03321_ (net) 0.03 0.00 2.05 ^ _20689_/B (XNOR2_X1) 1 3.66 0.01 0.03 2.07 v _20689_/ZN (XNOR2_X1) _03322_ (net) 0.01 0.00 2.07 v _20690_/B (MUX2_X1) 2 3.61 0.01 0.07 2.14 v _20690_/Z (MUX2_X1) _03323_ (net) 0.01 0.00 2.14 v _20691_/B2 (AOI22_X1) 1 2.44 0.03 0.05 2.19 ^ _20691_/ZN (AOI22_X1) _03324_ (net) 0.03 0.00 2.19 ^ _20692_/C1 (OAI221_X1) 1 4.89 0.03 0.04 2.23 v _20692_/ZN (OAI221_X1) _03325_ (net) 0.03 0.00 2.23 v _20693_/B2 (OAI22_X2) 1 3.65 0.03 0.05 2.28 ^ _20693_/ZN (OAI22_X2) _03326_ (net) 0.03 0.00 2.28 ^ place1839/A (BUF_X4) 6 33.40 0.02 0.04 2.32 ^ place1839/Z (BUF_X4) net1838 (net) 0.02 0.01 2.33 ^ place1838/A (BUF_X8) 26 57.21 0.02 0.03 2.36 ^ place1838/Z (BUF_X8) net1837 (net) 0.02 0.01 2.37 ^ _22214_/B2 (OAI21_X1) 1 1.21 0.02 0.02 2.39 v _22214_/ZN (OAI21_X1) _00844_ (net) 0.02 0.00 2.39 v gen_regfile_ff.register_file_i.rf_reg[444]$_DFFE_PN0P_/D (DFFR_X1) 2.39 data arrival time 2.20 2.20 clock core_clock (rise edge) 0.00 2.20 clock source latency 2 21.41 0.00 0.00 2.20 ^ clk_i (in) clk_i (net) 0.00 0.00 2.20 ^ delaybuf_0_core_clock/A (CLKBUF_X3) 1 8.73 0.01 0.03 2.23 ^ delaybuf_0_core_clock/Z (CLKBUF_X3) delaynet_0_core_clock (net) 0.01 0.00 2.23 ^ clkbuf_regs_0_core_clock/A (CLKBUF_X3) 1 1.80 0.01 0.03 2.26 ^ clkbuf_regs_0_core_clock/Z (CLKBUF_X3) clk_i_regs (net) 0.01 0.00 2.26 ^ clkbuf_0_clk_i_regs/A (CLKBUF_X3) 16 67.17 0.05 0.08 2.34 ^ clkbuf_0_clk_i_regs/Z (CLKBUF_X3) clknet_0_clk_i_regs (net) 0.05 0.01 2.34 ^ clkbuf_4_7_0_clk_i_regs/A (CLKBUF_X3) 10 30.15 0.03 0.07 2.41 ^ clkbuf_4_7_0_clk_i_regs/Z (CLKBUF_X3) clknet_4_7_0_clk_i_regs (net) 0.03 0.00 2.41 ^ clkbuf_leaf_64_clk_i_regs/A (CLKBUF_X3) 8 11.32 0.01 0.04 2.45 ^ clkbuf_leaf_64_clk_i_regs/Z (CLKBUF_X3) clknet_leaf_64_clk_i_regs (net) 0.01 0.00 2.45 ^ gen_regfile_ff.register_file_i.rf_reg[444]$_DFFE_PN0P_/CK (DFFR_X1) 0.00 2.45 clock reconvergence pessimism -0.04 2.41 library setup time 2.41 data required time ----------------------------------------------------------------------------- 2.41 data required time -2.39 data arrival time ----------------------------------------------------------------------------- 0.02 slack (MET) Startpoint: if_stage_i.instr_rdata_id_o[31]$_DFFE_PP_ (rising edge-triggered flip-flop clocked by core_clock) Endpoint: instr_addr_o[31] (output port clocked by vclk_core_clock) Path Group: vclk_core_clock Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 clock core_clock (rise edge) 0.00 0.00 clock source latency 2 21.41 0.00 0.00 0.00 ^ clk_i (in) clk_i (net) 0.00 0.00 0.00 ^ clkbuf_0_clk_i/A (CLKBUF_X3) 1 2.27 0.01 0.02 0.03 ^ clkbuf_0_clk_i/Z (CLKBUF_X3) clknet_0_clk_i (net) 0.01 0.00 0.03 ^ clkbuf_1_0__f_clk_i/A (CLKBUF_X3) 1 1.70 0.01 0.03 0.05 ^ clkbuf_1_0__f_clk_i/Z (CLKBUF_X3) clknet_1_0__leaf_clk_i (net) 0.01 0.00 0.05 ^ _27049_/A2 (AND2_X1) 1 1.64 0.01 0.03 0.08 ^ _27049_/ZN (AND2_X1) clk (net) 0.01 0.00 0.08 ^ clkbuf_0_clk/A (CLKBUF_X3) 16 71.97 0.05 0.08 0.17 ^ clkbuf_0_clk/Z (CLKBUF_X3) clknet_0_clk (net) 0.05 0.00 0.17 ^ clkbuf_4_5_0_clk/A (CLKBUF_X3) 9 34.58 0.03 0.07 0.24 ^ clkbuf_4_5_0_clk/Z (CLKBUF_X3) clknet_4_5_0_clk (net) 0.03 0.00 0.24 ^ clkbuf_leaf_139_clk/A (CLKBUF_X3) 9 11.70 0.01 0.04 0.29 ^ clkbuf_leaf_139_clk/Z (CLKBUF_X3) clknet_leaf_139_clk (net) 0.01 0.00 0.29 ^ if_stage_i.instr_rdata_id_o[31]$_DFFE_PP_/CK (DFF_X1) 17 41.33 0.04 0.13 0.42 v if_stage_i.instr_rdata_id_o[31]$_DFFE_PP_/Q (DFF_X1) id_stage_i.controller_i.instr_i[31] (net) 0.04 0.00 0.42 v _15855_/A3 (NOR4_X2) 5 11.53 0.08 0.13 0.55 ^ _15855_/ZN (NOR4_X2) _08844_ (net) 0.08 0.00 0.55 ^ _17582_/A1 (AOI222_X1) 2 3.08 0.03 0.03 0.58 v _17582_/ZN (AOI222_X1) _10510_ (net) 0.03 0.00 0.58 v _17586_/A3 (AND4_X1) 1 1.90 0.01 0.05 0.63 v _17586_/ZN (AND4_X1) _10514_ (net) 0.01 0.00 0.63 v _17587_/B2 (OAI21_X1) 8 18.89 0.09 0.12 0.75 ^ _17587_/ZN (OAI21_X1) _10515_ (net) 0.09 0.00 0.75 ^ _17674_/A1 (NAND4_X2) 4 18.25 0.05 0.08 0.83 v _17674_/ZN (NAND4_X2) _10602_ (net) 0.05 0.00 0.83 v _17684_/A1 (OAI22_X4) 7 17.71 0.04 0.06 0.89 ^ _17684_/ZN (OAI22_X4) _10612_ (net) 0.04 0.00 0.89 ^ _18329_/A2 (NOR2_X1) 4 6.62 0.02 0.03 0.92 v _18329_/ZN (NOR2_X1) _11150_ (net) 0.02 0.00 0.92 v _18749_/A1 (NAND2_X1) 12 26.37 0.06 0.08 1.00 ^ _18749_/ZN (NAND2_X1) _11454_ (net) 0.06 0.00 1.00 ^ place2167/A (BUF_X2) 20 41.99 0.05 0.07 1.07 ^ place2167/Z (BUF_X2) net2166 (net) 0.05 0.01 1.08 ^ _19765_/B2 (OAI221_X1) 1 5.17 0.04 0.05 1.13 v _19765_/ZN (OAI221_X1) ex_block_i.alu_i.adder_in_b[14] (net) 0.04 0.00 1.13 v _27676_/B (HA_X1) 2 2.85 0.03 0.05 1.18 ^ _27676_/S (HA_X1) _00350_ (net) 0.03 0.00 1.18 ^ _18244_/A3 (NAND3_X1) 2 3.85 0.03 0.03 1.21 v _18244_/ZN (NAND3_X1) _11067_ (net) 0.03 0.00 1.21 v _18245_/A3 (OR3_X1) 1 1.66 0.01 0.09 1.30 v _18245_/ZN (OR3_X1) _11068_ (net) 0.01 0.00 1.30 v _18246_/A3 (NOR3_X1) 3 6.20 0.06 0.09 1.38 ^ _18246_/ZN (NOR3_X1) _11069_ (net) 0.06 0.00 1.38 ^ _18262_/A1 (OR3_X1) 2 3.03 0.01 0.04 1.42 ^ _18262_/ZN (OR3_X1) _11085_ (net) 0.01 0.00 1.42 ^ _18263_/A4 (NAND4_X1) 2 3.07 0.02 0.04 1.46 v _18263_/ZN (NAND4_X1) _11086_ (net) 0.02 0.00 1.46 v _18276_/B1 (AOI21_X1) 3 5.18 0.04 0.05 1.51 ^ _18276_/ZN (AOI21_X1) _11099_ (net) 0.04 0.00 1.51 ^ _18277_/B2 (OAI21_X1) 2 8.62 0.02 0.04 1.55 v _18277_/ZN (OAI21_X1) _11100_ (net) 0.02 0.00 1.55 v _18348_/A1 (AND2_X1) 2 5.22 0.01 0.04 1.59 v _18348_/ZN (AND2_X1) _11169_ (net) 0.01 0.00 1.59 v _18349_/A3 (NOR3_X2) 3 7.47 0.04 0.07 1.66 ^ _18349_/ZN (NOR3_X2) _11170_ (net) 0.04 0.00 1.66 ^ _18350_/A2 (NOR2_X2) 2 12.89 0.02 0.03 1.68 v _18350_/ZN (NOR2_X2) net179 (net) 0.02 0.00 1.68 v _26998_/B2 (AOI221_X1) 1 8.06 0.09 0.13 1.82 ^ _26998_/ZN (AOI221_X1) _07782_ (net) 0.09 0.00 1.82 ^ _27000_/A1 (NOR2_X1) 3 9.20 0.03 0.03 1.85 v _27000_/ZN (NOR2_X1) _07784_ (net) 0.03 0.00 1.85 v _27001_/A (AOI21_X1) 2 9.16 0.05 0.08 1.93 ^ _27001_/ZN (AOI21_X1) _07785_ (net) 0.05 0.00 1.94 ^ _27217_/B1 (AOI21_X1) 2 2.06 0.02 0.02 1.96 v _27217_/ZN (AOI21_X1) net247 (net) 0.02 0.00 1.96 v output248/A (BUF_X1) 1 0.17 0.00 0.03 1.99 v output248/Z (BUF_X1) instr_addr_o[31] (net) 0.00 0.00 1.99 v instr_addr_o[31] (out) 1.99 data arrival time 0.00 2.20 2.20 clock vclk_core_clock (rise edge) 0.28 2.49 clock network delay (ideal) 0.00 2.49 clock reconvergence pessimism -0.44 2.05 output external delay 2.05 data required time ----------------------------------------------------------------------------- 2.05 data required time -1.99 data arrival time ----------------------------------------------------------------------------- 0.06 slack (MET) ========================================================================== finish report_check_types -max_slew -max_cap -max_fanout -violators -------------------------------------------------------------------------- ========================================================================== finish max_slew_check_slack -------------------------------------------------------------------------- 0.08291537314653397 ========================================================================== finish max_slew_check_limit -------------------------------------------------------------------------- 0.1985349953174591 ========================================================================== finish max_slew_check_slack_limit -------------------------------------------------------------------------- 0.4176 ========================================================================== finish max_fanout_check_slack -------------------------------------------------------------------------- 1.0000000150474662e+30 ========================================================================== finish max_fanout_check_limit -------------------------------------------------------------------------- 1.0000000150474662e+30 ========================================================================== finish max_capacitance_check_slack -------------------------------------------------------------------------- 0.779668390750885 ========================================================================== finish max_capacitance_check_limit -------------------------------------------------------------------------- 10.47130012512207 ========================================================================== finish max_capacitance_check_slack_limit -------------------------------------------------------------------------- 0.0745 ========================================================================== finish max_slew_violation_count -------------------------------------------------------------------------- max slew violation count 0 ========================================================================== finish max_fanout_violation_count -------------------------------------------------------------------------- max fanout violation count 0 ========================================================================== finish max_cap_violation_count -------------------------------------------------------------------------- max cap violation count 0 ========================================================================== finish setup_violation_count -------------------------------------------------------------------------- setup violation count 0 ========================================================================== finish hold_violation_count -------------------------------------------------------------------------- hold violation count 0 ========================================================================== finish report_checks -path_delay max reg to reg -------------------------------------------------------------------------- Startpoint: if_stage_i.instr_rdata_id_o[20]$_DFFE_PP_ (rising edge-triggered flip-flop clocked by core_clock) Endpoint: gen_regfile_ff.register_file_i.rf_reg[444]$_DFFE_PN0P_ (rising edge-triggered flip-flop clocked by core_clock) Path Group: core_clock Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock core_clock (rise edge) 0.00 0.00 clock source latency 0.00 0.00 ^ clk_i (in) 0.03 0.03 ^ clkbuf_0_clk_i/Z (CLKBUF_X3) 0.03 0.05 ^ clkbuf_1_0__f_clk_i/Z (CLKBUF_X3) 0.03 0.08 ^ _27049_/ZN (AND2_X1) 0.08 0.17 ^ clkbuf_0_clk/Z (CLKBUF_X3) 0.06 0.23 ^ clkbuf_4_3_0_clk/Z (CLKBUF_X3) 0.04 0.27 ^ clkbuf_leaf_135_clk/Z (CLKBUF_X3) 0.00 0.27 ^ if_stage_i.instr_rdata_id_o[20]$_DFFE_PP_/CK (DFF_X2) 0.13 0.40 ^ if_stage_i.instr_rdata_id_o[20]$_DFFE_PP_/Q (DFF_X2) 0.03 0.43 ^ rebuffer2617/Z (BUF_X8) 0.03 0.46 ^ place2488/Z (BUF_X16) 0.16 0.62 v _15916_/Z (MUX2_X1) 0.06 0.68 v _15919_/Z (MUX2_X1) 0.06 0.74 v _15923_/Z (MUX2_X1) 0.07 0.80 v _15924_/Z (MUX2_X1) 0.08 0.88 v _15940_/Z (MUX2_X2) 0.03 0.91 ^ _15942_/ZN (INV_X1) 0.01 0.92 v _15943_/ZN (NOR2_X1) 0.07 0.99 ^ _15978_/ZN (AOI21_X1) 0.04 1.03 ^ place2174/Z (BUF_X4) 0.03 1.05 v _16719_/ZN (NOR2_X1) 0.13 1.18 ^ _27596_/S (FA_X1) 0.10 1.28 v _27475_/S (FA_X1) 0.13 1.41 ^ _27654_/S (FA_X1) 0.10 1.50 v _27580_/S (FA_X1) 0.13 1.63 ^ _27489_/S (FA_X1) 0.10 1.73 v _27616_/S (FA_X1) 0.07 1.79 v _27792_/S (HA_X1) 0.02 1.82 ^ _20244_/ZN (INV_X1) 0.01 1.83 v _20246_/ZN (NOR2_X1) 0.04 1.87 ^ _20247_/ZN (OAI21_X1) 0.03 1.89 v _20255_/ZN (OAI21_X1) 0.05 1.95 ^ _20256_/ZN (OAI21_X1) 0.03 1.97 v _20258_/ZN (OAI211_X2) 0.03 2.00 ^ _20686_/ZN (NAND2_X1) 0.02 2.02 v _20687_/ZN (OAI21_X1) 0.03 2.05 ^ _20688_/ZN (AOI21_X1) 0.03 2.07 v _20689_/ZN (XNOR2_X1) 0.07 2.14 v _20690_/Z (MUX2_X1) 0.05 2.19 ^ _20691_/ZN (AOI22_X1) 0.04 2.23 v _20692_/ZN (OAI221_X1) 0.05 2.28 ^ _20693_/ZN (OAI22_X2) 0.04 2.32 ^ place1839/Z (BUF_X4) 0.04 2.36 ^ place1838/Z (BUF_X8) 0.03 2.39 v _22214_/ZN (OAI21_X1) 0.00 2.39 v gen_regfile_ff.register_file_i.rf_reg[444]$_DFFE_PN0P_/D (DFFR_X1) 2.39 data arrival time 2.20 2.20 clock core_clock (rise edge) 0.00 2.20 clock source latency 0.00 2.20 ^ clk_i (in) 0.03 2.23 ^ delaybuf_0_core_clock/Z (CLKBUF_X3) 0.03 2.26 ^ clkbuf_regs_0_core_clock/Z (CLKBUF_X3) 0.08 2.34 ^ clkbuf_0_clk_i_regs/Z (CLKBUF_X3) 0.07 2.41 ^ clkbuf_4_7_0_clk_i_regs/Z (CLKBUF_X3) 0.04 2.45 ^ clkbuf_leaf_64_clk_i_regs/Z (CLKBUF_X3) 0.00 2.45 ^ gen_regfile_ff.register_file_i.rf_reg[444]$_DFFE_PN0P_/CK (DFFR_X1) 0.00 2.45 clock reconvergence pessimism -0.04 2.41 library setup time 2.41 data required time --------------------------------------------------------- 2.41 data required time -2.39 data arrival time --------------------------------------------------------- 0.02 slack (MET) ========================================================================== finish report_checks -path_delay min reg to reg -------------------------------------------------------------------------- Startpoint: cs_registers_i.u_dcsr_csr.rd_data_o[2]$_DFFE_PN0P_ (rising edge-triggered flip-flop clocked by core_clock) Endpoint: cs_registers_i.u_dcsr_csr.rd_data_o[6]$_DFFE_PN0P_ (rising edge-triggered flip-flop clocked by core_clock) Path Group: core_clock Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock core_clock (rise edge) 0.00 0.00 clock source latency 0.00 0.00 ^ clk_i (in) 0.03 0.03 ^ clkbuf_0_clk_i/Z (CLKBUF_X3) 0.03 0.05 ^ clkbuf_1_0__f_clk_i/Z (CLKBUF_X3) 0.03 0.08 ^ _27049_/ZN (AND2_X1) 0.08 0.17 ^ clkbuf_0_clk/Z (CLKBUF_X3) 0.07 0.24 ^ clkbuf_4_7_0_clk/Z (CLKBUF_X3) 0.04 0.28 ^ clkbuf_leaf_101_clk/Z (CLKBUF_X3) 0.00 0.28 ^ cs_registers_i.u_dcsr_csr.rd_data_o[2]$_DFFE_PN0P_/CK (DFFR_X1) 0.08 0.36 ^ cs_registers_i.u_dcsr_csr.rd_data_o[2]$_DFFE_PN0P_/QN (DFFR_X1) 0.01 0.37 v _26634_/ZN (INV_X1) 0.02 0.39 ^ _26636_/ZN (AOI22_X1) 0.00 0.39 ^ cs_registers_i.u_dcsr_csr.rd_data_o[6]$_DFFE_PN0P_/D (DFFR_X1) 0.39 data arrival time 0.00 0.00 clock core_clock (rise edge) 0.00 0.00 clock source latency 0.00 0.00 ^ clk_i (in) 0.03 0.03 ^ clkbuf_0_clk_i/Z (CLKBUF_X3) 0.03 0.05 ^ clkbuf_1_0__f_clk_i/Z (CLKBUF_X3) 0.03 0.08 ^ _27049_/ZN (AND2_X1) 0.08 0.17 ^ clkbuf_0_clk/Z (CLKBUF_X3) 0.08 0.25 ^ clkbuf_4_13_0_clk/Z (CLKBUF_X3) 0.05 0.29 ^ clkbuf_leaf_103_clk/Z (CLKBUF_X3) 0.00 0.29 ^ cs_registers_i.u_dcsr_csr.rd_data_o[6]$_DFFE_PN0P_/CK (DFFR_X1) 0.00 0.29 clock reconvergence pessimism 0.01 0.30 library hold time 0.30 data required time --------------------------------------------------------- 0.30 data required time -0.39 data arrival time --------------------------------------------------------- 0.08 slack (MET) ========================================================================== finish critical path target clock latency max path -------------------------------------------------------------------------- 0.2611 ========================================================================== finish critical path target clock latency min path -------------------------------------------------------------------------- 0.2933 ========================================================================== finish critical path source clock latency min path -------------------------------------------------------------------------- 0.2850 ========================================================================== finish critical path delay -------------------------------------------------------------------------- 2.3898 ========================================================================== finish critical path slack -------------------------------------------------------------------------- 0.0223 ========================================================================== finish slack div critical path delay -------------------------------------------------------------------------- 0.933132 ========================================================================== finish report_power -------------------------------------------------------------------------- Group Internal Switching Leakage Total Power Power Power Power (Watts) ---------------------------------------------------------------- Sequential 7.23e-03 5.53e-04 1.55e-04 7.94e-03 25.6% Combinational 7.71e-03 1.07e-02 3.75e-04 1.88e-02 60.7% Clock 1.95e-03 2.30e-03 1.55e-05 4.27e-03 13.8% Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0% Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0% ---------------------------------------------------------------- Total 1.69e-02 1.36e-02 5.45e-04 3.10e-02 100.0% 54.4% 43.8% 1.8%